From patchwork Fri Jun 29 19:23:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Lakkireddy X-Patchwork-Id: 42001 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DF1851BAFB; Fri, 29 Jun 2018 21:25:36 +0200 (CEST) Received: from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8]) by dpdk.org (Postfix) with ESMTP id 353DB1BAE4; Fri, 29 Jun 2018 21:25:35 +0200 (CEST) Received: from localhost (scalar.blr.asicdesigners.com [10.193.185.94]) by stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id w5TJPVig029002; Fri, 29 Jun 2018 12:25:32 -0700 From: Rahul Lakkireddy To: dev@dpdk.org Cc: surendra@chelsio.com, shaguna@chelsio.com, indranil@chelsio.com, nirranjan@chelsio.com, stable@dpdk.org Date: Sat, 30 Jun 2018 00:53:54 +0530 Message-Id: <41ccf6375f0c888226b103d856e26766a39dae88.1530300158.git.rahul.lakkireddy@chelsio.com> X-Mailer: git-send-email 2.5.3 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 4/5] net/cxgbe: fix Rx channel map and queue type X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Set the Rx channel map and ingress queue type properly to allow firmware to manage the internal mapping correctly. Fixes: 6c2809628cd5 ("net/cxgbe: improve latency for slow traffic") Cc: stable@dpdk.org Signed-off-by: Rahul Lakkireddy --- drivers/net/cxgbe/base/t4fw_interface.h | 8 ++++++++ drivers/net/cxgbe/cxgbe_compat.h | 9 --------- drivers/net/cxgbe/sge.c | 10 +++++++--- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h index 9dc6d8123..5ddde6b59 100644 --- a/drivers/net/cxgbe/base/t4fw_interface.h +++ b/drivers/net/cxgbe/base/t4fw_interface.h @@ -794,6 +794,11 @@ enum fw_iq_type { FW_IQ_TYPE_FL_INT_CAP, }; +enum fw_iq_iqtype { + FW_IQ_IQTYPE_NIC = 1, + FW_IQ_IQTYPE_OFLD, +}; + struct fw_iq_cmd { __be32 op_to_vfn; __be32 alloc_to_len16; @@ -927,6 +932,9 @@ struct fw_iq_cmd { (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) +#define S_FW_IQ_CMD_IQTYPE 24 +#define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE) + #define S_FW_IQ_CMD_FL0CNGCHMAP 20 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) diff --git a/drivers/net/cxgbe/cxgbe_compat.h b/drivers/net/cxgbe/cxgbe_compat.h index 779bcf165..d33452861 100644 --- a/drivers/net/cxgbe/cxgbe_compat.h +++ b/drivers/net/cxgbe/cxgbe_compat.h @@ -198,15 +198,6 @@ static inline int cxgbe_fls(int x) return x ? sizeof(x) * 8 - __builtin_clz(x) : 0; } -/** - * cxgbe_ffs - find first bit set - * @x: the word to search - */ -static inline int cxgbe_ffs(int x) -{ - return x ? __builtin_ffs(x) : 0; -} - static inline unsigned long ilog2(unsigned long n) { unsigned int e = 0; diff --git a/drivers/net/cxgbe/sge.c b/drivers/net/cxgbe/sge.c index 357b4856d..4ea40d191 100644 --- a/drivers/net/cxgbe/sge.c +++ b/drivers/net/cxgbe/sge.c @@ -1889,12 +1889,16 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, F_FW_CMD_WRITE | F_FW_CMD_EXEC); if (is_pf4(adap)) { - pciechan = cong > 0 ? cxgbe_ffs(cong) - 1 : pi->tx_chan; + pciechan = pi->tx_chan; c.op_to_vfn |= htonl(V_FW_IQ_CMD_PFN(adap->pf) | V_FW_IQ_CMD_VFN(0)); if (cong >= 0) - c.iqns_to_fl0congen = htonl(F_FW_IQ_CMD_IQFLINTCONGEN | - F_FW_IQ_CMD_IQRO); + c.iqns_to_fl0congen = + htonl(F_FW_IQ_CMD_IQFLINTCONGEN | + V_FW_IQ_CMD_IQTYPE(cong ? + FW_IQ_IQTYPE_NIC : + FW_IQ_IQTYPE_OFLD) | + F_FW_IQ_CMD_IQRO); } else { pciechan = pi->port_id; }