From patchwork Fri Jun 29 18:12:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Lakkireddy X-Patchwork-Id: 41995 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A503B1BB09; Fri, 29 Jun 2018 20:13:59 +0200 (CEST) Received: from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8]) by dpdk.org (Postfix) with ESMTP id 65CC31B90F for ; Fri, 29 Jun 2018 20:13:56 +0200 (CEST) Received: from localhost (scalar.blr.asicdesigners.com [10.193.185.94]) by stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id w5TIDqu9028635; Fri, 29 Jun 2018 11:13:53 -0700 From: Rahul Lakkireddy To: dev@dpdk.org Cc: shaguna@chelsio.com, indranil@chelsio.com, nirranjan@chelsio.com Date: Fri, 29 Jun 2018 23:42:23 +0530 Message-Id: <165fc0f3fa15ce2728f0a425531964c7063e1c28.1530295732.git.rahul.lakkireddy@chelsio.com> X-Mailer: git-send-email 2.5.3 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 8/9] net/cxgbe: add support to match on ingress physical port X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shagun Agrawal Add support to match packets based on ingress physical port. Signed-off-by: Shagun Agrawal Signed-off-by: Rahul Lakkireddy --- drivers/net/cxgbe/cxgbe_filter.c | 16 +++++++++++++++- drivers/net/cxgbe/cxgbe_flow.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/net/cxgbe/cxgbe_filter.c b/drivers/net/cxgbe/cxgbe_filter.c index ff43488b5..8c5890ea8 100644 --- a/drivers/net/cxgbe/cxgbe_filter.c +++ b/drivers/net/cxgbe/cxgbe_filter.c @@ -65,11 +65,19 @@ int validate_filter(struct adapter *adapter, struct ch_filter_specification *fs) #define U(_mask, _field) \ (!(fconf & (_mask)) && S(_field)) - if (U(F_ETHERTYPE, ethtype) || U(F_PROTOCOL, proto)) + if (U(F_PORT, iport) || U(F_ETHERTYPE, ethtype) || U(F_PROTOCOL, proto)) return -EOPNOTSUPP; #undef S #undef U + + /* + * Don't allow various trivially obvious bogus out-of-range + * values ... + */ + if (fs->val.iport >= adapter->params.nports) + return -ERANGE; + return 0; } @@ -228,6 +236,9 @@ static u64 hash_filter_ntuple(const struct filter_entry *f) u64 ntuple = 0; u16 tcp_proto = IPPROTO_TCP; /* TCP Protocol Number */ + if (tp->port_shift >= 0) + ntuple |= (u64)f->fs.mask.iport << tp->port_shift; + if (tp->protocol_shift >= 0) { if (!f->fs.val.proto) ntuple |= (u64)tcp_proto << tp->protocol_shift; @@ -664,6 +675,9 @@ int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx) cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) | V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id )); + fwr->maci_to_matchtypem = + cpu_to_be32(V_FW_FILTER_WR_PORT(f->fs.val.iport) | + V_FW_FILTER_WR_PORTM(f->fs.mask.iport)); fwr->ptcl = f->fs.val.proto; fwr->ptclm = f->fs.mask.proto; rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip)); diff --git a/drivers/net/cxgbe/cxgbe_flow.c b/drivers/net/cxgbe/cxgbe_flow.c index 4f00ac4c6..823bc720c 100644 --- a/drivers/net/cxgbe/cxgbe_flow.c +++ b/drivers/net/cxgbe/cxgbe_flow.c @@ -93,6 +93,8 @@ cxgbe_fill_filter_region(struct adapter *adap, ntuple_mask |= (u64)fs->mask.proto << tp->protocol_shift; if (tp->ethertype_shift >= 0) ntuple_mask |= (u64)fs->mask.ethtype << tp->ethertype_shift; + if (tp->port_shift >= 0) + ntuple_mask |= (u64)fs->mask.iport << tp->port_shift; if (ntuple_mask != hash_filter_mask) return; @@ -100,6 +102,27 @@ cxgbe_fill_filter_region(struct adapter *adap, fs->cap = 1; /* use hash region */ } +static int +ch_rte_parsetype_port(const void *dmask, const struct rte_flow_item *item, + struct ch_filter_specification *fs, + struct rte_flow_error *e) +{ + const struct rte_flow_item_phy_port *val = item->spec; + const struct rte_flow_item_phy_port *umask = item->mask; + const struct rte_flow_item_phy_port *mask; + + mask = umask ? umask : (const struct rte_flow_item_phy_port *)dmask; + + if (val->index > 0x7) + return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, + item, + "port index upto 0x7 is supported"); + + CXGBE_FILL_FS(val->index, mask->index, iport); + + return 0; +} + static int ch_rte_parsetype_udp(const void *dmask, const struct rte_flow_item *item, struct ch_filter_specification *fs, @@ -357,6 +380,13 @@ cxgbe_rtef_parse_actions(struct rte_flow *flow, } struct chrte_fparse parseitem[] = { + [RTE_FLOW_ITEM_TYPE_PHY_PORT] = { + .fptr = ch_rte_parsetype_port, + .dmask = &(const struct rte_flow_item_phy_port){ + .index = 0x7, + } + }, + [RTE_FLOW_ITEM_TYPE_IPV4] = { .fptr = ch_rte_parsetype_ipv4, .dmask = &rte_flow_item_ipv4_mask,