From patchwork Tue Feb 27 15:13:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gowrishankar X-Patchwork-Id: 35493 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CBFB74C81; Tue, 27 Feb 2018 16:14:06 +0100 (CET) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by dpdk.org (Postfix) with ESMTP id 734654C81 for ; Tue, 27 Feb 2018 16:14:05 +0100 (CET) Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w1RF5Pcf070168 for ; Tue, 27 Feb 2018 10:14:04 -0500 Received: from e06smtp15.uk.ibm.com (e06smtp15.uk.ibm.com [195.75.94.111]) by mx0b-001b2d01.pphosted.com with ESMTP id 2gd97da2ds-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 27 Feb 2018 10:14:04 -0500 Received: from localhost by e06smtp15.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 27 Feb 2018 15:14:03 -0000 Received: from b06cxnps3075.portsmouth.uk.ibm.com (9.149.109.195) by e06smtp15.uk.ibm.com (192.168.101.145) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Tue, 27 Feb 2018 15:14:00 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w1RFE0sB43450406; Tue, 27 Feb 2018 15:14:00 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3DDEB11C064; Tue, 27 Feb 2018 15:06:54 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 296EF11C04A; Tue, 27 Feb 2018 15:06:53 +0000 (GMT) Received: from chozha.in.ibm.com (unknown [9.79.222.185]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 27 Feb 2018 15:06:52 +0000 (GMT) From: Gowrishankar To: dev@dpdk.org Cc: Chao Zhu , stable@dpdk.org, thomas@monjalon.net, Gowrishankar Muthukrishnan Date: Tue, 27 Feb 2018 20:43:58 +0530 X-Mailer: git-send-email 1.9.1 X-TM-AS-GCONF: 00 x-cbid: 18022715-0020-0000-0000-000003FC72AC X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18022715-0021-0000-0000-000042909928 Message-Id: X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-27_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1802270190 Subject: [dpdk-dev] [PATCH] eal/ppc: fix rte_smp_mb for a compilation error with else clause X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Gowrishankar Muthukrishnan This patch fixes the compilation problem with rte_smp_mb, when there is else clause following it, as in test_barrier.c. Fixes: 05c3fd7110 ("eal/ppc: atomic operations for IBM Power") Cc: stable@dpdk.org Signed-off-by: Gowrishankar Muthukrishnan Acked-by: Luca Boccassi Acked-by: Chao Zhu --- lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h index 39fce7b..1821774 100644 --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h @@ -55,7 +55,7 @@ * Guarantees that the LOAD and STORE operations generated before the * barrier occur before the LOAD and STORE operations generated after. */ -#define rte_mb() {asm volatile("sync" : : : "memory"); } +#define rte_mb() asm volatile("sync" : : : "memory") /** * Write memory barrier.