From patchwork Thu Nov 16 08:03:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 31396 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4393A1B2A3; Thu, 16 Nov 2017 09:05:13 +0100 (CET) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 844121B25A for ; Thu, 16 Nov 2017 09:04:59 +0100 (CET) Received: from pure.maildistiller.com (unknown [10.110.50.29]) by dispatch1-us1.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTP id 2781A20052 for ; Thu, 16 Nov 2017 08:04:59 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us4.ppe-hosted.com (unknown [10.110.49.251]) by pure.maildistiller.com (Proofpoint Essentials ESMTP Server) with ESMTPS id 0448F100052 for ; Thu, 16 Nov 2017 08:04:57 +0000 (UTC) Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1-us4.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id 08D44140059 for ; Thu, 16 Nov 2017 08:04:57 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Thu, 16 Nov 2017 00:04:54 -0800 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Thu, 16 Nov 2017 00:04:53 -0800 Received: from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com [10.17.10.10]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id vAG84qtr016607; Thu, 16 Nov 2017 08:04:52 GMT Received: from uklogin.uk.solarflarecom.com (localhost.localdomain [127.0.0.1]) by uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id vAG84qtY006905; Thu, 16 Nov 2017 08:04:52 GMT From: Andrew Rybchenko To: CC: Andrew Jackson Date: Thu, 16 Nov 2017 08:03:49 +0000 Message-ID: <1510819481-6809-2-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.2.3 In-Reply-To: <1510819481-6809-1-git-send-email-arybchenko@solarflare.com> References: <1510819481-6809-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-MDID: 1510819497-y7l2PAzVgvSl Subject: [dpdk-dev] [PATCH 01/53] net/sfc/base: copy new header from firmwaresrc X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Andrew Jackson Signed-off-by: Andrew Jackson Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/siena_flash.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/sfc/base/siena_flash.h b/drivers/net/sfc/base/siena_flash.h index e2700554..5fa3ea4 100644 --- a/drivers/net/sfc/base/siena_flash.h +++ b/drivers/net/sfc/base/siena_flash.h @@ -113,15 +113,21 @@ typedef struct siena_mc_boot_hdr_s { /* GENERATED BY scripts/genfwdef */ efx_word_t checksum; /* of whole header area + firmware image */ efx_word_t firmware_version_d; efx_byte_t mcfw_subtype; - efx_byte_t generation; /* Valid for medford, SBZ for earlier chips */ + efx_byte_t generation; /* MC (Medford and later): MC partition generation when */ + /* written to NVRAM. */ + /* MUM & SUC images: subtype. */ + /* (Otherwise set to 0) */ efx_dword_t firmware_text_offset; /* offset to firmware .text */ efx_dword_t firmware_text_size; /* length of firmware .text, in bytes */ efx_dword_t firmware_data_offset; /* offset to firmware .data */ efx_dword_t firmware_data_size; /* length of firmware .data, in bytes */ efx_byte_t spi_rate; /* SPI rate for reading image, 0 is BootROM default */ efx_byte_t spi_phase_adj; /* SPI SDO/SCL phase adjustment, 0 is default (no adj) */ - efx_word_t xpm_sector; /* The sector that contains the key, or 0xffff if unsigned (medford) SBZ (earlier) */ - efx_dword_t reserved_c[7]; /* (set to 0) */ + efx_word_t xpm_sector; /* XPM (MEDFORD and later): The sector that contains */ + /* the key, or 0xffff if unsigned. (Otherwise set to 0) */ + efx_byte_t mumfw_subtype; /* MUM & SUC images: subtype. (Otherwise set to 0) */ + efx_byte_t reserved_b[3]; /* (set to 0) */ + efx_dword_t reserved_c[6]; /* (set to 0) */ } siena_mc_boot_hdr_t; #define SIENA_MC_BOOT_HDR_PADDING \