From patchwork Tue Jan 6 06:53:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhigang Lu X-Patchwork-Id: 2199 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 4ECC45A40; Tue, 6 Jan 2015 08:02:17 +0100 (CET) Received: from emea01-am1-obe.outbound.protection.outlook.com (mail-am1on0061.outbound.protection.outlook.com [157.56.112.61]) by dpdk.org (Postfix) with ESMTP id 358AE58DD for ; Tue, 6 Jan 2015 08:02:16 +0100 (CET) Received: from DB4PR02CA0037.eurprd02.prod.outlook.com (10.242.174.165) by AM3PR02MB004.eurprd02.prod.outlook.com (10.242.242.26) with Microsoft SMTP Server (TLS) id 15.1.49.12; Tue, 6 Jan 2015 07:02:06 +0000 Received: from DB3FFO11FD046.protection.gbl (2a01:111:f400:7e04::180) by DB4PR02CA0037.outlook.office365.com (2a01:111:e400:983b::37) with Microsoft SMTP Server (TLS) id 15.1.49.12 via Frontend Transport; Tue, 6 Jan 2015 07:02:06 +0000 Received: from bjgfarm-2.internal.tilera.com (124.207.145.166) by DB3FFO11FD046.mail.protection.outlook.com (10.47.217.77) with Microsoft SMTP Server (TLS) id 15.1.49.13 via Frontend Transport; Tue, 6 Jan 2015 07:02:03 +0000 Received: (from zlu@localhost) by bjgfarm-2.internal.tilera.com (8.14.4/8.14.4/Submit) id t0671eGS017218; Tue, 6 Jan 2015 15:01:40 +0800 From: Zhigang Lu To: Date: Tue, 6 Jan 2015 14:53:47 +0800 Message-ID: <1420527230-17037-10-git-send-email-zlu@ezchip.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1420527230-17037-1-git-send-email-zlu@ezchip.com> References: <1420527230-17037-1-git-send-email-zlu@ezchip.com> X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of ezchip.com does not designate 124.207.145.166 as permitted sender) receiver=protection.outlook.com; client-ip=124.207.145.166; helo=bjgfarm-2.internal.tilera.com; Authentication-Results: spf=fail (sender IP is 124.207.145.166) smtp.mailfrom=zlu@ezchip.com; X-Forefront-Antispam-Report: CIP:124.207.145.166; CTRY:CN; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(339900001)(189002)(199003)(97736003)(19580405001)(21056001)(120916001)(229853001)(19580395003)(6806004)(99396003)(36756003)(107046002)(2351001)(62966003)(68736005)(2950100001)(31966008)(106466001)(42186005)(77156002)(105606002)(50466002)(50226001)(4396001)(46102003)(48376002)(110136001)(89996001)(33646002)(84676001)(50986999)(92566001)(104016003)(86362001)(76176999)(64706001)(87936001)(20776003)(47776003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR02MB004; H:bjgfarm-2.internal.tilera.com; FPR:; SPF:Fail; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-DmarcAction: None X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(3005003);SRVR:AM3PR02MB004; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004); SRVR:AM3PR02MB004; X-Forefront-PRVS: 0448A97BF2 X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:;SRVR:AM3PR02MB004; X-OriginatorOrg: ezchip.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jan 2015 07:02:03.3373 (UTC) X-MS-Exchange-CrossTenant-Id: 0fc16e0a-3cd3-4092-8b2f-0a42cff122c3 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0fc16e0a-3cd3-4092-8b2f-0a42cff122c3; Ip=[124.207.145.166] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR02MB004 Subject: [dpdk-dev] [PATCH v2 09/12] eal/tile: add CPU flags operations for TileGx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds empty functions for CPU flags operations to support DPDK, since tile processor doesn't have CPU flag hardware registers. Signed-off-by: Zhigang Lu Signed-off-by: Cyril Chemparathy --- .../common/include/arch/tile/rte_cpuflags.h | 78 ++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 lib/librte_eal/common/include/arch/tile/rte_cpuflags.h diff --git a/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h b/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h new file mode 100644 index 0000000..872e38c --- /dev/null +++ b/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h @@ -0,0 +1,78 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2014 Tilera Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Tilera Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTE_CPUFLAGS_TILE_H_ +#define _RTE_CPUFLAGS_TILE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#include + +#include "generic/rte_cpuflags.h" + +enum rte_cpu_flag_t { + RTE_CPUFLAG_SSE4_1 = 0, /**< SSE4_1 */ + /* The last item */ + RTE_CPUFLAG_NUMFLAGS, /**< This should always be the last! */ +}; + +static const struct feature_entry cpu_feature_table[] = { + FEAT_DEF(SSE4_1, 0x00000000, 0, 0, 0) +}; + +static inline void +rte_cpu_get_features(__rte_unused uint32_t leaf, + __rte_unused uint32_t subleaf, + __rte_unused cpuid_registers_t out) +{ +} + +static inline int +rte_cpu_get_flag_enabled(__rte_unused enum rte_cpu_flag_t feature) +{ + if (feature >= RTE_CPUFLAG_NUMFLAGS) + /* Flag does not match anything in the feature tables */ + return -ENOENT; + + return 0; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_CPUFLAGS_TILE_H_ */