[dpdk-dev,v4,07/29] eal/arm64: fix memory barrier definition for arm64
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Message ID 1484637244-7548-8-git-send-email-jerin.jacob@caviumnetworks.com
State Superseded, archived
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Context Check Description
ci/checkpatch success coding style OK
ci/Intel compilation success Compilation OK

Commit Message

Jerin Jacob Jan. 17, 2017, 7:13 a.m. UTC
dsb instruction based barrier is used for non smp
version of memory barrier.

Fixes: d708f01b7102 ("eal/arm: add atomic operations for ARMv8")

CC: Jianbo Liu <jianbo.liu@linaro.org>
CC: stable@dpdk.org
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Acked-by: Jianbo Liu <jianbo.liu@linaro.org>
---
 lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

Patch
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diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index d854aac..bc7de64 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -43,7 +43,8 @@  extern "C" {
 
 #include "generic/rte_atomic.h"
 
-#define dmb(opt)  do { asm volatile("dmb " #opt : : : "memory"); } while (0)
+#define dsb(opt)  { asm volatile("dsb " #opt : : : "memory"); }
+#define dmb(opt)  { asm volatile("dmb " #opt : : : "memory"); }
 
 /**
  * General memory barrier.
@@ -54,7 +55,7 @@  extern "C" {
  */
 static inline void rte_mb(void)
 {
-	dmb(ish);
+	dsb(sy);
 }
 
 /**
@@ -66,7 +67,7 @@  static inline void rte_mb(void)
  */
 static inline void rte_wmb(void)
 {
-	dmb(ishst);
+	dsb(st);
 }
 
 /**
@@ -78,7 +79,7 @@  static inline void rte_wmb(void)
  */
 static inline void rte_rmb(void)
 {
-	dmb(ishld);
+	dsb(ld);
 }
 
 #define rte_smp_mb() rte_mb()