[dpdk-dev,v2,4/7] net/ixgbe/base: support Marvell 1000BASE-T PHYs

Message ID 1484232811-39257-5-git-send-email-wei.dai@intel.com
State Accepted, archived
Delegated to: Ferruh Yigit
Headers show

Checks

Context Check Description
ci/Intel compilation fail Compilation issues
ci/checkpatch success coding style OK

Commit Message

Wei Dai Jan. 12, 2017, 2:53 p.m.
This patch adds initial support for Marvell 1000BASE-T PHYs
on some X550 platforms.
Firmware owns the link config for Marvell PHYs on these platforms,
software should not touch it.
Also these platforms are not capable of speeds lower than 1Gb.

Signed-off-by: Wei Dai <wei.dai@intel.com>
---
 drivers/net/ixgbe/base/ixgbe_phy.c  | 4 ++++
 drivers/net/ixgbe/base/ixgbe_type.h | 1 +
 drivers/net/ixgbe/base/ixgbe_x550.c | 8 ++++++++
 3 files changed, 13 insertions(+)

Patch

diff --git a/drivers/net/ixgbe/base/ixgbe_phy.c b/drivers/net/ixgbe/base/ixgbe_phy.c
index 5ad4dfe..e0d7125 100644
--- a/drivers/net/ixgbe/base/ixgbe_phy.c
+++ b/drivers/net/ixgbe/base/ixgbe_phy.c
@@ -472,6 +472,10 @@  enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 	case X557_PHY_ID2:
 		phy_type = ixgbe_phy_x550em_ext_t;
 		break;
+	case IXGBE_M88E1500_E_PHY_ID:
+	case IXGBE_M88E1543_E_PHY_ID:
+		phy_type = ixgbe_phy_ext_1g_t;
+		break;
 	default:
 		phy_type = ixgbe_phy_unknown;
 		break;
diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h
index dea210e..bb1f85b 100644
--- a/drivers/net/ixgbe/base/ixgbe_type.h
+++ b/drivers/net/ixgbe/base/ixgbe_type.h
@@ -3647,6 +3647,7 @@  enum ixgbe_phy_type {
 	ixgbe_phy_x550em_kx4,
 	ixgbe_phy_x550em_xfi,
 	ixgbe_phy_x550em_ext_t,
+	ixgbe_phy_ext_1g_t,
 	ixgbe_phy_cu_unknown,
 	ixgbe_phy_qt,
 	ixgbe_phy_xaui,
diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c
index b23d479..1fd7ffb 100644
--- a/drivers/net/ixgbe/base/ixgbe_x550.c
+++ b/drivers/net/ixgbe/base/ixgbe_x550.c
@@ -1975,6 +1975,7 @@  s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
 			*speed = IXGBE_LINK_SPEED_10GB_FULL;
 	} else {
 		switch (hw->phy.type) {
+		case ixgbe_phy_ext_1g_t:
 		case ixgbe_phy_sgmii:
 			*speed = IXGBE_LINK_SPEED_1GB_FULL;
 			break;
@@ -2399,6 +2400,10 @@  s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
 		phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
 		phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
 		break;
+	case ixgbe_phy_ext_1g_t:
+		/* link is managed by FW */
+		phy->ops.setup_link = NULL;
+		break;
 	case ixgbe_phy_x550em_xfi:
 		/* link is managed by HW */
 		phy->ops.setup_link = NULL;
@@ -3706,6 +3711,9 @@  u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
 	case ixgbe_phy_sgmii:
 		physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
 		break;
+	case ixgbe_phy_ext_1g_t:
+		physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
+		break;
 	default:
 		break;
 	}