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dkim=none (message not signed) header.d=none;dpdk.org; dmarc=none action=none header.from=mellanox.com; Received: from AM0PR05MB4866.eurprd05.prod.outlook.com (2603:10a6:208:c0::32) by AM0PR05MB4961.eurprd05.prod.outlook.com (2603:10a6:208:c5::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3195.17; Fri, 17 Jul 2020 13:49:46 +0000 Received: from AM0PR05MB4866.eurprd05.prod.outlook.com ([fe80::d44d:a804:c730:d2b7]) by AM0PR05MB4866.eurprd05.prod.outlook.com ([fe80::d44d:a804:c730:d2b7%2]) with mapi id 15.20.3174.026; Fri, 17 Jul 2020 13:49:46 +0000 From: Parav Pandit To: dev@dpdk.org, grive@u256.net, ferruh.yigit@intel.com, thomas@monjalon.net Cc: rasland@mellanox.com, orika@mellanox.com, matan@mellanox.com, joyce.kong@arm.com, Parav Pandit Date: Fri, 17 Jul 2020 16:49:15 +0300 Message-Id: <20200717134924.922390-1-parav@mellanox.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200610171728.89-2-parav@mellanox.com> References: <20200610171728.89-2-parav@mellanox.com> X-ClientProxiedBy: DM3PR03CA0013.namprd03.prod.outlook.com (2603:10b6:0:50::23) To AM0PR05MB4866.eurprd05.prod.outlook.com (2603:10a6:208:c0::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sw-mtx-036.mtx.labs.mlnx (208.176.44.194) by DM3PR03CA0013.namprd03.prod.outlook.com (2603:10b6:0:50::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3195.19 via Frontend Transport; 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PTR:; CAT:NONE; SFTY:; SFS:(4636009)(136003)(376002)(39860400002)(346002)(396003)(366004)(16526019)(1076003)(186003)(8936002)(2906002)(6506007)(86362001)(26005)(6486002)(2616005)(5660300002)(66946007)(478600001)(66556008)(66476007)(6512007)(107886003)(4326008)(83380400001)(956004)(8676002)(52116002)(66574015)(36756003)(6666004)(316002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: DtbSUdateoIcgeySddNMOD6inBluCjck1FfoO818b5m814XDwzUWrEWM06r99H0u2EY0fr/0rfVgBzsWqPizVJMYoX45Kk5dZTuzp9os1dAvYUczd5E+Xkt34EwZSgoORbS3G5e0Et1YQIxYtbPyuzLW3/EdMVwtRwqQDFb6DbLHrL54fz7xpaomu/QB+8zFDUbe7PO1xQ4KAuz7mZRtGDA/b5uoX3N/WckgPHcg3EbgdGKzUBrErtM6Z1Ffg2ZK3d664TLL51YkMD8iDN0pTsWOF0HUCIj7GAtPae+JRYruJmuUfcIqGdBALI+H9hTXpR6l3lwLk4e4mCG1UeWCExmO4Av+uKP/6ajr8buLyT///V1opqqR1kOjzdnTCS+jILQV5+8GNlNuH274u88QZuzroHOSPo1P8Tmy7TFhdsGfVnGDwhqpq/1G17tXOY5rWVShuQVKviWCh9QTYU0+cohe50wNFe4D9CvBEyzMzmy1AlobXzdb9fWN8XC0y4Vb X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: f9b80e80-8626-4e88-e908-08d82a5843ec X-MS-Exchange-CrossTenant-AuthSource: AM0PR05MB4866.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2020 13:49:46.1111 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: M+1H1Wg6cptSSauf/CmXM4yRYAc+isba+6zLZBonVJlZC+Q/vuFAfVgkoKF8tukYOln3EZVYHXxKY6Yj2QhyaA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR05MB4961 Subject: [dpdk-dev] [PATCH v7 0/9] Improve mlx5 PMD driver framework for multiple classes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This series introduces mlx5 bus to support multiple class of devices for a single PCI device. Motivation and example ---------------------- mlx5 PCI device supports multiple class of devices such as net, vdpa and regex devices. Currently only one pmd (either net or vdpa) can bind to this device. This design limits use of PCI device only for single device class. To support multiple classes simultaneously for a mlx5 PCI device, a new mlx5 PCI bus is created. This bus allows binding multiple class drivers (such as net, vdpa, regex(future)) to bind to the mlx5 PCI bus driver. Change description ------------------ Patch-1 Introduces RTE_BIT() macro Patch-2 Introduces new RTE constructor priority for common initialization Patch-3 Fixes compilation error Patch-4 Define mlx5 class as bit fields Patch-5 Uses new RTE common priority Patch-6 Adds mlx5 PCI bus Patch-7 Implements a mlx5 PCI bus driver Patch-8 Migrates mlx5 net and vdpa driver to use mlx5 PCI bus API instead of rte PCI bus API Patch-9 Removed class check code as its already part of the bus now Design overview --------------- ----------- ------------ ------------- | mlx5 | | mlx5 | | mlx5 | | net pmd | | vdpa pmd | | regex pmd | ----------- ------------ ------------- \ | / \ | / \ ------------- / \______| mlx5 |_____ / | pci bus | ------------- | ----------- | mlx5 | | pci dev | ----------- - mlx5 pci bus driver binds to mlx5 PCI devices defined by PCI ID table of all related mlx5 PCI devices. - mlx5 class driver such as net, vdpa, regex PMD defines its specific PCI ID table and mlx5 bus driver probes matching class drivers. - mlx5 pci bus driver is cental place that validates supported class combinations. - In future as code evolves, more device setup/cleanup and resource creation code moves to mlx5 PCI bus driver. Alternatives considered ----------------------- 1. Instead of creating mlx5 pci bus, a common driver is implemented which exposes class registration API. However, bus model fits better with existing DPDK design similar to ifpga driver. Class registration API need to create a new callbacks and ID signature; instead it is better to utilize current well defined methods. 2. Enhance pci core to allow multiple driver binding to single rte PCI device. This approach is not taken, because peer drivers using one PCI device won't be aware of other's presence. This requires cross-driver syncronization of who initializes common resources (such as irq, eq and more). This also requires refcounting common objects etc among peer drivers. Instead of layered approach delivers and allows putting common resource sharing, setup code in common bus driver. It also eliminates peer blind zone problem as bottom pci bus layer provides necessary setup without any reference counting. 3. In future mlx5 prefers to use RDMA MR cache of the mbuf used between net and regex pmd so that same mbuf use across multiple device can be possible. Examples: -------- A user who wish to use a specific class(es) provides list of classes at command line such as, ./testpmd -w ,class=net:vdpa ./testpmd -w ,class=vdpa In future, ./testpmd -w ,class=net:regex Changelog: v6->v7: - Updated release notes v5->v6: - Fixed compilation failure in parallel build for shared lib v4->v5: - Squash the maintainers update path with other patch which adds the bus - Addressed comments from Morten Brørup - Renamed newly added macro to RTE_BIT64 - Added doxygen comment section for the macro v3->v4: - Fixed dma_map error unwinding flow to follow same order for unmap v2->v3: - Added RTE priority for common driver initialization - Addressed comments from Thomas and Asaf - Fixed compilation error in glue wrapper - Moved pci_driver structure instance as first in driver - Removed white spaces at the end of line in diagram - Address commnts from Matan - Removed CONFIG_RTE_LIBRTE_MLX5_PCI_BUS from config files - Renamed mlx5_valid_class_combo to mlx5_class_combinations - Added cross check for class drivers to support only 3 flags for now - Added full stop at the end of comment block - Using full names in function names - Added new line before function name in multiple functions - Added example string to parse for multiple classes - Dropped mlx5 prefix from static function - Removed empty lines - Fixed issue to remove multiple classes for a driver - Using define for drv_flags at multiple places - Deriving drv_flags based on the class drivers - Fixed alignment for id_table - Perform dma map on best effort basis for all supported drivers - Dynamically build pci id table - Using PCI to mlx5 device helper routines v1->v2: - Addressed most comments from Thomas and Gaetan. - Symbols starting with prefix rte_bus_pci_mlx5 may be confusing as it may appear as it belong to rte_bus_pci module. Hence it is kept as rte_bus_mlx5_pci which matches with other modules as mlx5_vdpa, mlx5_net. - Dropped 2nd patch and replace with new 6th patch. - Avoided new file, added macro to rte_bitops.h - Inheriting ret_pci_driver instead of rte_driver - Added design and description of the mlx5_pci bus - Enhanced driver to honor RTE_PCI_DRV_PROBE_AGAIN drv_flag - Use anonymous structure for class search and code changes around it - Define static for class comination array - Use RTE_DIM to find array size - Added OOM check for strdup() - Renamed copy variable to nstr_orig - Returning negagive error code - Returning directly if match entry found - Use compat condition check - Avoided cutting error message string - Use uint32_t datatype instead of enum mlx5_class - Changed logic to parse device arguments only once during probe() - Added check to fail driver probe if multiple classes register with DMA ops - Renamed function to parse_class_options - Migreate API from rte_driver to rte_pci_driver Parav Pandit (9): eal: introduce macros for getting value for bit eal: introduce RTE common initialization level common/mlx5: fix empty input style in glue wrappers common/mlx5: change mlx5 class enum values as bits common/mlx5: use common rte priority bus/mlx5_pci: add mlx5 PCI bus bus/mlx5_pci: register a PCI driver bus/mlx5_pci: enable net and vDPA to use mlx5 PCI bus driver common/mlx5: remove class checks from individual driver MAINTAINERS | 5 + doc/guides/rel_notes/release_20_08.rst | 5 + drivers/bus/Makefile | 4 + drivers/bus/meson.build | 2 +- drivers/bus/mlx5_pci/Makefile | 41 ++ drivers/bus/mlx5_pci/meson.build | 19 + drivers/bus/mlx5_pci/mlx5_pci_bus.c | 522 ++++++++++++++++++ drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h | 84 +++ .../bus/mlx5_pci/rte_bus_mlx5_pci_version.map | 5 + drivers/common/mlx5/linux/mlx5_glue.h | 4 +- drivers/common/mlx5/mlx5_common.c | 39 +- drivers/common/mlx5/mlx5_common.h | 7 +- .../common/mlx5/rte_common_mlx5_version.map | 2 - drivers/net/mlx5/Makefile | 3 +- drivers/net/mlx5/linux/mlx5_os.c | 6 - drivers/net/mlx5/meson.build | 2 +- drivers/net/mlx5/mlx5.c | 26 +- drivers/net/mlx5/mlx5.h | 1 - drivers/vdpa/mlx5/Makefile | 3 +- drivers/vdpa/mlx5/meson.build | 2 +- drivers/vdpa/mlx5/mlx5_vdpa.c | 30 +- lib/librte_eal/include/rte_bitops.h | 8 + lib/librte_eal/include/rte_common.h | 1 + mk/rte.app.mk | 1 + 24 files changed, 737 insertions(+), 85 deletions(-) create mode 100644 drivers/bus/mlx5_pci/Makefile create mode 100644 drivers/bus/mlx5_pci/meson.build create mode 100644 drivers/bus/mlx5_pci/mlx5_pci_bus.c create mode 100644 drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h create mode 100644 drivers/bus/mlx5_pci/rte_bus_mlx5_pci_version.map