From patchwork Wed Jan 15 18:28:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcin Smoczynski X-Patchwork-Id: 64731 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8FEE5A0514; Wed, 15 Jan 2020 19:30:24 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 68BBE1C247; Wed, 15 Jan 2020 19:30:24 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 18B271C246 for ; Wed, 15 Jan 2020 19:30:22 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Jan 2020 10:30:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,323,1574150400"; d="scan'208";a="254502145" Received: from msmoczyx-mobl.ger.corp.intel.com ([10.104.125.3]) by fmsmga001.fm.intel.com with ESMTP; 15 Jan 2020 10:30:20 -0800 From: Marcin Smoczynski To: akhil.goyal@nxp.com, konstantin.ananyev@intel.com, roy.fan.zhang@intel.com, declan.doherty@intel.com, radu.nicolau@intel.com Cc: dev@dpdk.org, Marcin Smoczynski Date: Wed, 15 Jan 2020 19:28:26 +0100 Message-Id: <20200115182832.17012-1-marcinx.smoczynski@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 0/6] Introduce CPU crypto mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Originally both SW and HW crypto PMDs use rte_crypot_op based API to process the crypto workload asynchronously. This way provides uniformity to both PMD types, but also introduce unnecessary performance penalty to SW PMDs that have to "simulate" HW async behavior (crypto-ops enqueue/dequeue, HW addresses computations, storing/dereferencing user provided data (mbuf) for each crypto-op, etc). The aim is to introduce a new optional API for SW crypto-devices to perform crypto processing in a synchronous manner. Marcin Smoczynski (6): cryptodev: introduce cpu crypto support API crypto/aesni_gcm: cpu crypto support security: add cpu crypto action type ipsec: introduce support for cpu crypto mode examples/ipsec-secgw: cpu crypto support examples/ipsec-secgw: cpu crypto testing drivers/crypto/aesni_gcm/aesni_gcm_ops.h | 9 + drivers/crypto/aesni_gcm/aesni_gcm_pmd.c | 149 ++++++++++++++++- drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c | 3 + .../crypto/aesni_gcm/aesni_gcm_pmd_private.h | 18 +- examples/ipsec-secgw/ipsec.c | 12 +- examples/ipsec-secgw/ipsec_process.c | 134 +++++++++------ examples/ipsec-secgw/sa.c | 33 +++- examples/ipsec-secgw/test/common_defs.sh | 21 +++ examples/ipsec-secgw/test/linux_test4.sh | 11 +- examples/ipsec-secgw/test/linux_test6.sh | 11 +- .../test/trs_3descbc_sha1_common_defs.sh | 8 +- .../test/trs_aescbc_sha1_common_defs.sh | 8 +- .../test/trs_aesctr_sha1_common_defs.sh | 8 +- .../test/tun_3descbc_sha1_common_defs.sh | 8 +- .../test/tun_aescbc_sha1_common_defs.sh | 8 +- .../test/tun_aesctr_sha1_common_defs.sh | 8 +- lib/librte_cryptodev/rte_crypto_sym.h | 62 ++++++- lib/librte_cryptodev/rte_cryptodev.c | 30 ++++ lib/librte_cryptodev/rte_cryptodev.h | 20 +++ lib/librte_cryptodev/rte_cryptodev_pmd.h | 19 +++ .../rte_cryptodev_version.map | 1 + lib/librte_ipsec/esp_inb.c | 154 +++++++++++++++--- lib/librte_ipsec/esp_outb.c | 134 +++++++++++++-- lib/librte_ipsec/misc.h | 118 ++++++++++++++ lib/librte_ipsec/rte_ipsec.h | 18 +- lib/librte_ipsec/sa.c | 126 +++++++++++--- lib/librte_ipsec/sa.h | 17 ++ lib/librte_ipsec/ses.c | 3 +- lib/librte_security/rte_security.h | 6 +- 29 files changed, 990 insertions(+), 167 deletions(-)