From patchwork Wed Apr 3 17:34:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Eads, Gage" X-Patchwork-Id: 52221 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F2A831B513; Wed, 3 Apr 2019 19:35:32 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 33F691B4E5 for ; Wed, 3 Apr 2019 19:35:31 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Apr 2019 10:35:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,305,1549958400"; d="scan'208";a="334697325" Received: from txasoft-yocto.an.intel.com ([10.123.72.192]) by fmsmga005.fm.intel.com with ESMTP; 03 Apr 2019 10:35:29 -0700 From: Gage Eads To: dev@dpdk.org Cc: olivier.matz@6wind.com, arybchenko@solarflare.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, gavin.hu@arm.com, Honnappa.Nagarahalli@arm.com, nd@arm.com, chaozhu@linux.vnet.ibm.com, jerinj@marvell.com, hemant.agrawal@nxp.com, thomas@monjalon.net Date: Wed, 3 Apr 2019 12:34:37 -0500 Message-Id: <20190403173438.23691-1-gage.eads@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190304205133.2248-1-gage.eads@intel.com> References: <20190304205133.2248-1-gage.eads@intel.com> Subject: [dpdk-dev] [PATCH v4 0/1] Add 128-bit compare and set X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch addresses x86-64 only; other architectures can/will be supported in the future. The __atomic intrinsic was considered for the implementation, however libatomic was found[1] to use locks to implement the 128-bit CAS on at least one architecture and so is eschewed here. The interface is modeled after the __atomic_compare_exchange_16 (which itself is based on the C++11 memory model) to best support weak consistency architectures. This patch was originally part of a series that introduces a non-blocking stack mempool handler[2], and is required by a non-blocking ring patchset. This patch was spun off so that the the NB ring depends only on this patch and not on the entire non-blocking stack patchset. [1] http://mails.dpdk.org/archives/dev/2019-January/124002.html [2] http://mails.dpdk.org/archives/dev/2019-January/123653.html v4: - Move function declaration from generic/rte_atomic.h to x86-64 header file v3: - Rename function to ISA-neutral rte_atomic128_cmp_exchange() - Fix two pseudocode bugs in function documentation v2: - Rename function to rte_atomic128_cmpxchg() - Replace "=A" output constraint with "=a" and "=d" to prevent GCC from using the al register for the sete destination - Extend 'weak' definition to allow non-atomic 'exp' updates. - Add const keyword to 'src' and remove volatile keyword from 'dst' - Put __int128 in a union in rte_int128_t and move the structure definition inside the RTE_ARCH_x86_64 ifdef - Drop enum rte_atomic_memmodel_t in favor of compiler-defined __ATOMIC_* - Drop unnecessary comment relating to X86_64 - Tweak the pseudocode to reflect the 'exp' update on failure. Gage Eads (1): eal: add 128-bit compare exchange (x86-64 only) .../common/include/arch/x86/rte_atomic_64.h | 81 ++++++++++++++++++++++ 1 file changed, 81 insertions(+)