[dpdk-dev] eal/ppc: fix rte_smp_mb for a compilation error with else clause
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Commit Message
From: Gowrishankar Muthukrishnan <gowrishankar.m@linux.vnet.ibm.com>
This patch fixes the compilation problem with rte_smp_mb,
when there is else clause following it, as in test_barrier.c.
Fixes: 05c3fd7110 ("eal/ppc: atomic operations for IBM Power")
Cc: stable@dpdk.org
Signed-off-by: Gowrishankar Muthukrishnan <gowrishankar.m@linux.vnet.ibm.com>
---
lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
On Tue, 2018-02-27 at 20:43 +0530, Gowrishankar wrote:
> From: Gowrishankar Muthukrishnan <gowrishankar.m@linux.vnet.ibm.com>
>
> This patch fixes the compilation problem with rte_smp_mb,
> when there is else clause following it, as in test_barrier.c.
>
> Fixes: 05c3fd7110 ("eal/ppc: atomic operations for IBM Power")
> Cc: stable@dpdk.org
>
> Signed-off-by: Gowrishankar Muthukrishnan <gowrishankar.m@linux.vnet.
> ibm.com>
> ---
> lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
> b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
> index 39fce7b..1821774 100644
> --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
> +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
> @@ -55,7 +55,7 @@
> * Guarantees that the LOAD and STORE operations generated before
> the
> * barrier occur before the LOAD and STORE operations generated
> after.
> */
> -#define rte_mb() {asm volatile("sync" : : : "memory"); }
> +#define rte_mb() asm volatile("sync" : : : "memory")
>
> /**
> * Write memory barrier.
Acked-by: Luca Boccassi <bluca@debian.org>
Maintainers and reviewers, 18.02 build on ppc64 is currently broken and
I'd like to backport this patch to Debian ASAP and then backport to
16.11, so a quick review would be much much appreciated. Thank you!
> -----Original Message-----
> From: Gowrishankar [mailto:gowrishankar.m@linux.vnet.ibm.com]
> Sent: 2018年2月27日 23:14
> To: dev@dpdk.org
> Cc: Chao Zhu <chaozhu@linux.vnet.ibm.com>; stable@dpdk.org;
> thomas@monjalon.net; Gowrishankar Muthukrishnan
> <gowrishankar.m@linux.vnet.ibm.com>
> Subject: [PATCH] eal/ppc: fix rte_smp_mb for a compilation error with else
> clause
>
> From: Gowrishankar Muthukrishnan <gowrishankar.m@linux.vnet.ibm.com>
>
> This patch fixes the compilation problem with rte_smp_mb, when there is
else
> clause following it, as in test_barrier.c.
>
> Fixes: 05c3fd7110 ("eal/ppc: atomic operations for IBM Power")
> Cc: stable@dpdk.org
>
> Signed-off-by: Gowrishankar Muthukrishnan
> <gowrishankar.m@linux.vnet.ibm.com>
> ---
> lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
> b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
> index 39fce7b..1821774 100644
> --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
> +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
> @@ -55,7 +55,7 @@
> * Guarantees that the LOAD and STORE operations generated before the
> * barrier occur before the LOAD and STORE operations generated after.
> */
> -#define rte_mb() {asm volatile("sync" : : : "memory"); }
> +#define rte_mb() asm volatile("sync" : : : "memory")
>
> /**
> * Write memory barrier.
> --
> 1.9.1
Acked-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
> > This patch fixes the compilation problem with rte_smp_mb, when there is
> else
> > clause following it, as in test_barrier.c.
> >
> > Fixes: 05c3fd7110 ("eal/ppc: atomic operations for IBM Power")
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Gowrishankar Muthukrishnan
> > <gowrishankar.m@linux.vnet.ibm.com>
> > ---
> Acked-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
Applied, thanks
@@ -55,7 +55,7 @@
* Guarantees that the LOAD and STORE operations generated before the
* barrier occur before the LOAD and STORE operations generated after.
*/
-#define rte_mb() {asm volatile("sync" : : : "memory"); }
+#define rte_mb() asm volatile("sync" : : : "memory")
/**
* Write memory barrier.