doc: update mlx5 limitations on ESP header match
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Commit Message
The match on ESP header is supported over PF only.
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
doc/guides/nics/mlx5.rst | 2 ++
1 file changed, 2 insertions(+)
Comments
Hi,
> -----Original Message-----
> From: Slava Ovsiienko <viacheslavo@nvidia.com>
> Sent: Wednesday, March 22, 2023 5:07 PM
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@nvidia.com>; Raslan Darawsheh
> <rasland@nvidia.com>; Ori Kam <orika@nvidia.com>
> Subject: [PATCH] doc: update mlx5 limitations on ESP header match
>
> The match on ESP header is supported over PF only.
>
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
@@ -289,6 +289,8 @@ Limitations
- When using DV/Verbs flow engine (``dv_flow_en`` = 1/0 respectively),
match on SPI field in ESP header for group 0 is supported from ConnectX-7.
+- Matching on SPI field in ESP header is supported over the PF only.
+
- Flex item:
- Hardware support: **NVIDIA BlueField-2** and **NVIDIA BlueField-3**.