[v2,1/1] build: add Graviton2(arm64) meson configuration
Checks
Commit Message
Add meson build configuration for Graviton2 platform
with 64-bit Arm Neoverse N1 cores. This patch makes the
following changes to generic Neoverse N1 config:
1. increase lcore limit to 64
2. increase memory support to 1TB
3. remove +crc from -march as that is default when setting armv8.2
For more information about Graviton2 platform, refer to:
https://aws.amazon.com/ec2/graviton/
Signed-off-by: Vimal Chungath <vcchunga@amazon.com>
---
config/arm/arm64_graviton2_linux_gcc | 17 +++++++++++++++++
config/arm/meson.build | 12 +++++++++++-
2 files changed, 28 insertions(+), 1 deletion(-)
create mode 100644 config/arm/arm64_graviton2_linux_gcc
Comments
Hello,
IMO, Juraj's patch for meson build rework for Arm platforms will need some time. Keeping the RC2 deadline in mind, it makes sense to accept this patch and target Juraj's patch for 21.02.
Any opinions?
> -----Original Message-----
> From: Vimal Chungath <vcchunga@amazon.com>
> Sent: Tuesday, October 27, 2020 3:18 PM
> To: dev@dpdk.org
> Cc: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>; Dharmik
> Thakkar <Dharmik.Thakkar@arm.com>; alisaidi@amazon.com;
> bruce.richardson@intel.com; hemant.agrawal@nxp.com;
> jerinj@marvell.com; jerinjacobk@gmail.com; juraj.linkes@pantheon.tech;
> nd <nd@arm.com>; thomas@monjalon.net
> Subject: [PATCH v2 1/1] build: add Graviton2(arm64) meson configuration
>
> Add meson build configuration for Graviton2 platform with 64-bit Arm
> Neoverse N1 cores. This patch makes the following changes to generic
> Neoverse N1 config:
>
> 1. increase lcore limit to 64
> 2. increase memory support to 1TB
> 3. remove +crc from -march as that is default when setting armv8.2
>
> For more information about Graviton2 platform, refer to:
> https://aws.amazon.com/ec2/graviton/
>
> Signed-off-by: Vimal Chungath <vcchunga@amazon.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> ---
> config/arm/arm64_graviton2_linux_gcc | 17 +++++++++++++++++
> config/arm/meson.build | 12 +++++++++++-
> 2 files changed, 28 insertions(+), 1 deletion(-) create mode 100644
> config/arm/arm64_graviton2_linux_gcc
>
> diff --git a/config/arm/arm64_graviton2_linux_gcc
> b/config/arm/arm64_graviton2_linux_gcc
> new file mode 100644
> index 000000000..022e06303
> --- /dev/null
> +++ b/config/arm/arm64_graviton2_linux_gcc
> @@ -0,0 +1,17 @@
> +[binaries]
> +c = 'aarch64-linux-gnu-gcc'
> +cpp = 'aarch64-linux-gnu-cpp'
> +ar = 'aarch64-linux-gnu-gcc-ar'
> +strip = 'aarch64-linux-gnu-strip'
> +pkgconfig = 'aarch64-linux-gnu-pkg-config'
> +pcap-config = ''
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'aarch64'
> +cpu = 'armv8-a'
> +endian = 'little'
> +
> +[properties]
> +implementor_id = '0x41'
> +implementor_pn = '0xd0c'
> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> b49203fa8..0e7124843 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -86,6 +86,16 @@ flags_octeontx2_extra = [
> ['RTE_ARM_FEATURE_ATOMICS', true],
> ['RTE_EAL_IGB_UIO', false],
> ['RTE_USE_C11_MEM_MODEL', true]]
> +flags_n1generic_extra = [
> + ['RTE_MACHINE', '"neoverse-n1"'],
> + ['RTE_MAX_LCORE', 64],
> + ['RTE_CACHE_LINE_SIZE', 64],
> + ['RTE_ARM_FEATURE_ATOMICS', true],
> + ['RTE_USE_C11_MEM_MODEL', true],
> + ['RTE_MAX_MEM_MB', 1048576],
> + ['RTE_MAX_NUMA_NODES', 1],
> + ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> + ['RTE_LIBRTE_VHOST_NUMA', false]]
>
> machine_args_generic = [
> ['default', ['-march=armv8-a+crc', '-moutline-atomics']], @@ -97,7
> +107,7 @@ machine_args_generic = [
> ['0xd09', ['-mcpu=cortex-a73']],
> ['0xd0a', ['-mcpu=cortex-a75']],
> ['0xd0b', ['-mcpu=cortex-a76']],
> - ['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'],
> flags_n1sdp_extra]]
> + ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> +flags_n1generic_extra]]
>
> machine_args_cavium = [
> ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> --
> 2.16.6
> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Vimal Chungath
> Sent: Wednesday, October 28, 2020 4:18 AM
> To: dev@dpdk.org
> Cc: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>; Dharmik
> Thakkar <Dharmik.Thakkar@arm.com>; alisaidi@amazon.com;
> bruce.richardson@intel.com; hemant.agrawal@nxp.com;
> jerinj@marvell.com; jerinjacobk@gmail.com; juraj.linkes@pantheon.tech;
> nd <nd@arm.com>; thomas@monjalon.net
> Subject: [dpdk-dev] [PATCH v2 1/1] build: add Graviton2(arm64) meson
> configuration
>
> Add meson build configuration for Graviton2 platform with 64-bit Arm
> Neoverse N1 cores. This patch makes the following changes to generic
> Neoverse N1 config:
>
> 1. increase lcore limit to 64
> 2. increase memory support to 1TB
> 3. remove +crc from -march as that is default when setting armv8.2
>
> For more information about Graviton2 platform, refer to:
> https://aws.amazon.com/ec2/graviton/
>
> Signed-off-by: Vimal Chungath <vcchunga@amazon.com>
> ---
> config/arm/arm64_graviton2_linux_gcc | 17 +++++++++++++++++
> config/arm/meson.build | 12 +++++++++++-
> 2 files changed, 28 insertions(+), 1 deletion(-) create mode 100644
> config/arm/arm64_graviton2_linux_gcc
>
> diff --git a/config/arm/arm64_graviton2_linux_gcc
> b/config/arm/arm64_graviton2_linux_gcc
> new file mode 100644
> index 000000000..022e06303
> --- /dev/null
> +++ b/config/arm/arm64_graviton2_linux_gcc
> @@ -0,0 +1,17 @@
> +[binaries]
> +c = 'aarch64-linux-gnu-gcc'
> +cpp = 'aarch64-linux-gnu-cpp'
> +ar = 'aarch64-linux-gnu-gcc-ar'
> +strip = 'aarch64-linux-gnu-strip'
> +pkgconfig = 'aarch64-linux-gnu-pkg-config'
> +pcap-config = ''
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'aarch64'
> +cpu = 'armv8-a'
> +endian = 'little'
> +
> +[properties]
> +implementor_id = '0x41'
> +implementor_pn = '0xd0c'
> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> b49203fa8..0e7124843 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -86,6 +86,16 @@ flags_octeontx2_extra = [
> ['RTE_ARM_FEATURE_ATOMICS', true],
> ['RTE_EAL_IGB_UIO', false],
> ['RTE_USE_C11_MEM_MODEL', true]]
> +flags_n1generic_extra = [
> + ['RTE_MACHINE', '"neoverse-n1"'],
> + ['RTE_MAX_LCORE', 64],
> + ['RTE_CACHE_LINE_SIZE', 64],
> + ['RTE_ARM_FEATURE_ATOMICS', true],
> + ['RTE_USE_C11_MEM_MODEL', true],
> + ['RTE_MAX_MEM_MB', 1048576],
> + ['RTE_MAX_NUMA_NODES', 1],
> + ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> + ['RTE_LIBRTE_VHOST_NUMA', false]]
>
> machine_args_generic = [
> ['default', ['-march=armv8-a+crc', '-moutline-atomics']], @@ -97,7
> +107,7 @@ machine_args_generic = [
> ['0xd09', ['-mcpu=cortex-a73']],
> ['0xd0a', ['-mcpu=cortex-a75']],
> ['0xd0b', ['-mcpu=cortex-a76']],
> - ['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'],
> flags_n1sdp_extra]]
> + ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> +flags_n1generic_extra]]
After this change, 'flags_n1sdp_extra' will no longer be referenced. Then it can be removed.
>
> machine_args_cavium = [
> ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> --
> 2.16.6
On Wed, Oct 28, 2020 at 9:59 AM Honnappa Nagarahalli
<Honnappa.Nagarahalli@arm.com> wrote:
>
> Hello,
> IMO, Juraj's patch for meson build rework for Arm platforms will need some time. Keeping the RC2 deadline in mind, it makes sense to accept this patch and target Juraj's patch for 21.02.
>
> Any opinions?
I feel, Recent Juraj's changes looks in good shape, I think, once he
fixes your review comment and sends the next version. We can test it
and give the final reviewed by and merge it in RC2.
IMO, Those changes are critical to adding a new platform when MIDR is
the same value.
>
> > -----Original Message-----
> > From: Vimal Chungath <vcchunga@amazon.com>
> > Sent: Tuesday, October 27, 2020 3:18 PM
> > To: dev@dpdk.org
> > Cc: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>; Dharmik
> > Thakkar <Dharmik.Thakkar@arm.com>; alisaidi@amazon.com;
> > bruce.richardson@intel.com; hemant.agrawal@nxp.com;
> > jerinj@marvell.com; jerinjacobk@gmail.com; juraj.linkes@pantheon.tech;
> > nd <nd@arm.com>; thomas@monjalon.net
> > Subject: [PATCH v2 1/1] build: add Graviton2(arm64) meson configuration
> >
> > Add meson build configuration for Graviton2 platform with 64-bit Arm
> > Neoverse N1 cores. This patch makes the following changes to generic
> > Neoverse N1 config:
> >
> > 1. increase lcore limit to 64
> > 2. increase memory support to 1TB
> > 3. remove +crc from -march as that is default when setting armv8.2
> >
> > For more information about Graviton2 platform, refer to:
> > https://aws.amazon.com/ec2/graviton/
> >
> > Signed-off-by: Vimal Chungath <vcchunga@amazon.com>
> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
>
> > ---
> > config/arm/arm64_graviton2_linux_gcc | 17 +++++++++++++++++
> > config/arm/meson.build | 12 +++++++++++-
> > 2 files changed, 28 insertions(+), 1 deletion(-) create mode 100644
> > config/arm/arm64_graviton2_linux_gcc
> >
> > diff --git a/config/arm/arm64_graviton2_linux_gcc
> > b/config/arm/arm64_graviton2_linux_gcc
> > new file mode 100644
> > index 000000000..022e06303
> > --- /dev/null
> > +++ b/config/arm/arm64_graviton2_linux_gcc
> > @@ -0,0 +1,17 @@
> > +[binaries]
> > +c = 'aarch64-linux-gnu-gcc'
> > +cpp = 'aarch64-linux-gnu-cpp'
> > +ar = 'aarch64-linux-gnu-gcc-ar'
> > +strip = 'aarch64-linux-gnu-strip'
> > +pkgconfig = 'aarch64-linux-gnu-pkg-config'
> > +pcap-config = ''
> > +
> > +[host_machine]
> > +system = 'linux'
> > +cpu_family = 'aarch64'
> > +cpu = 'armv8-a'
> > +endian = 'little'
> > +
> > +[properties]
> > +implementor_id = '0x41'
> > +implementor_pn = '0xd0c'
> > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > b49203fa8..0e7124843 100644
> > --- a/config/arm/meson.build
> > +++ b/config/arm/meson.build
> > @@ -86,6 +86,16 @@ flags_octeontx2_extra = [
> > ['RTE_ARM_FEATURE_ATOMICS', true],
> > ['RTE_EAL_IGB_UIO', false],
> > ['RTE_USE_C11_MEM_MODEL', true]]
> > +flags_n1generic_extra = [
> > + ['RTE_MACHINE', '"neoverse-n1"'],
> > + ['RTE_MAX_LCORE', 64],
> > + ['RTE_CACHE_LINE_SIZE', 64],
> > + ['RTE_ARM_FEATURE_ATOMICS', true],
> > + ['RTE_USE_C11_MEM_MODEL', true],
> > + ['RTE_MAX_MEM_MB', 1048576],
> > + ['RTE_MAX_NUMA_NODES', 1],
> > + ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> > + ['RTE_LIBRTE_VHOST_NUMA', false]]
> >
> > machine_args_generic = [
> > ['default', ['-march=armv8-a+crc', '-moutline-atomics']], @@ -97,7
> > +107,7 @@ machine_args_generic = [
> > ['0xd09', ['-mcpu=cortex-a73']],
> > ['0xd0a', ['-mcpu=cortex-a75']],
> > ['0xd0b', ['-mcpu=cortex-a76']],
> > - ['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'],
> > flags_n1sdp_extra]]
> > + ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> > +flags_n1generic_extra]]
> >
> > machine_args_cavium = [
> > ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > --
> > 2.16.6
>
<snip>
> >
> > Hello,
> > IMO, Juraj's patch for meson build rework for Arm platforms will need
> some time. Keeping the RC2 deadline in mind, it makes sense to accept this
> patch and target Juraj's patch for 21.02.
> >
> > Any opinions?
>
> I feel, Recent Juraj's changes looks in good shape, I think, once he fixes your
> review comment and sends the next version. We can test it and give the final
> reviewed by and merge it in RC2.
> IMO, Those changes are critical to adding a new platform when MIDR is the
> same value.
The main aim was to have the ability to build for a specified SoC. It is available for cross-builds, but not for native builds.
>
>
> >
> > > -----Original Message-----
> > > From: Vimal Chungath <vcchunga@amazon.com>
> > > Sent: Tuesday, October 27, 2020 3:18 PM
> > > To: dev@dpdk.org
> > > Cc: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>; Dharmik
> > > Thakkar <Dharmik.Thakkar@arm.com>; alisaidi@amazon.com;
> > > bruce.richardson@intel.com; hemant.agrawal@nxp.com;
> > > jerinj@marvell.com; jerinjacobk@gmail.com;
> > > juraj.linkes@pantheon.tech; nd <nd@arm.com>; thomas@monjalon.net
> > > Subject: [PATCH v2 1/1] build: add Graviton2(arm64) meson
> > > configuration
> > >
> > > Add meson build configuration for Graviton2 platform with 64-bit Arm
> > > Neoverse N1 cores. This patch makes the following changes to generic
> > > Neoverse N1 config:
> > >
> > > 1. increase lcore limit to 64
> > > 2. increase memory support to 1TB
> > > 3. remove +crc from -march as that is default when setting armv8.2
> > >
> > > For more information about Graviton2 platform, refer to:
> > > https://aws.amazon.com/ec2/graviton/
> > >
> > > Signed-off-by: Vimal Chungath <vcchunga@amazon.com>
> > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> >
> > > ---
> > > config/arm/arm64_graviton2_linux_gcc | 17 +++++++++++++++++
> > > config/arm/meson.build | 12 +++++++++++-
> > > 2 files changed, 28 insertions(+), 1 deletion(-) create mode
> > > 100644 config/arm/arm64_graviton2_linux_gcc
> > >
> > > diff --git a/config/arm/arm64_graviton2_linux_gcc
> > > b/config/arm/arm64_graviton2_linux_gcc
> > > new file mode 100644
> > > index 000000000..022e06303
> > > --- /dev/null
> > > +++ b/config/arm/arm64_graviton2_linux_gcc
> > > @@ -0,0 +1,17 @@
> > > +[binaries]
> > > +c = 'aarch64-linux-gnu-gcc'
> > > +cpp = 'aarch64-linux-gnu-cpp'
> > > +ar = 'aarch64-linux-gnu-gcc-ar'
> > > +strip = 'aarch64-linux-gnu-strip'
> > > +pkgconfig = 'aarch64-linux-gnu-pkg-config'
> > > +pcap-config = ''
> > > +
> > > +[host_machine]
> > > +system = 'linux'
> > > +cpu_family = 'aarch64'
> > > +cpu = 'armv8-a'
> > > +endian = 'little'
> > > +
> > > +[properties]
> > > +implementor_id = '0x41'
> > > +implementor_pn = '0xd0c'
> > > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > > b49203fa8..0e7124843 100644
> > > --- a/config/arm/meson.build
> > > +++ b/config/arm/meson.build
> > > @@ -86,6 +86,16 @@ flags_octeontx2_extra = [
> > > ['RTE_ARM_FEATURE_ATOMICS', true],
> > > ['RTE_EAL_IGB_UIO', false],
> > > ['RTE_USE_C11_MEM_MODEL', true]]
> > > +flags_n1generic_extra = [
> > > + ['RTE_MACHINE', '"neoverse-n1"'],
> > > + ['RTE_MAX_LCORE', 64],
> > > + ['RTE_CACHE_LINE_SIZE', 64],
> > > + ['RTE_ARM_FEATURE_ATOMICS', true],
> > > + ['RTE_USE_C11_MEM_MODEL', true],
> > > + ['RTE_MAX_MEM_MB', 1048576],
> > > + ['RTE_MAX_NUMA_NODES', 1],
> > > + ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> > > + ['RTE_LIBRTE_VHOST_NUMA', false]]
> > >
> > > machine_args_generic = [
> > > ['default', ['-march=armv8-a+crc', '-moutline-atomics']], @@
> > > -97,7
> > > +107,7 @@ machine_args_generic = [
> > > ['0xd09', ['-mcpu=cortex-a73']],
> > > ['0xd0a', ['-mcpu=cortex-a75']],
> > > ['0xd0b', ['-mcpu=cortex-a76']],
> > > - ['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'],
> > > flags_n1sdp_extra]]
> > > + ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> > > +flags_n1generic_extra]]
> > >
> > > machine_args_cavium = [
> > > ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > > --
> > > 2.16.6
> >
new file mode 100644
@@ -0,0 +1,17 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pkgconfig = 'aarch64-linux-gnu-pkg-config'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x41'
+implementor_pn = '0xd0c'
@@ -86,6 +86,16 @@ flags_octeontx2_extra = [
['RTE_ARM_FEATURE_ATOMICS', true],
['RTE_EAL_IGB_UIO', false],
['RTE_USE_C11_MEM_MODEL', true]]
+flags_n1generic_extra = [
+ ['RTE_MACHINE', '"neoverse-n1"'],
+ ['RTE_MAX_LCORE', 64],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_MAX_MEM_MB', 1048576],
+ ['RTE_MAX_NUMA_NODES', 1],
+ ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
+ ['RTE_LIBRTE_VHOST_NUMA', false]]
machine_args_generic = [
['default', ['-march=armv8-a+crc', '-moutline-atomics']],
@@ -97,7 +107,7 @@ machine_args_generic = [
['0xd09', ['-mcpu=cortex-a73']],
['0xd0a', ['-mcpu=cortex-a75']],
['0xd0b', ['-mcpu=cortex-a76']],
- ['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'], flags_n1sdp_extra]]
+ ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_n1generic_extra]]
machine_args_cavium = [
['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],