Message ID | 20200923142253.18853-1-radu.nicolau@intel.com (mailing list archive) |
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Return-Path: <dev-bounces@dpdk.org> X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6F53AA04B1; Wed, 23 Sep 2020 16:23:42 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CBCDC1DA6F; Wed, 23 Sep 2020 16:23:41 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id F09F81DA33 for <dev@dpdk.org>; Wed, 23 Sep 2020 16:23:39 +0200 (CEST) IronPort-SDR: ktZdFTVkDez/VrwMmMrStRsxbXhZNek7QZxqLyLIFtybvnIYoZkAaTIKsI37Bo2/GGvfvkGrd5 veC3ay5WQYow== X-IronPort-AV: E=McAfee;i="6000,8403,9752"; a="245732135" X-IronPort-AV: E=Sophos;i="5.77,293,1596524400"; d="scan'208";a="245732135" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2020 07:23:39 -0700 IronPort-SDR: jpz2nmAAen9zlkui39ktNKcs9UxHT7/5RforVd8U0VKRU+WdLki73XvLX5vOtCiJn32VOZWdFn l0lBGvBljjdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,293,1596524400"; d="scan'208";a="511663484" Received: from silpixa00399477.ir.intel.com ([10.237.214.232]) by fmsmga005.fm.intel.com with ESMTP; 23 Sep 2020 07:23:36 -0700 From: Radu Nicolau <radu.nicolau@intel.com> To: dev@dpdk.org Cc: beilei.xing@intel.com, jia.guo@intel.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, jerinjacobk@gmail.com, david.marchand@redhat.com, fiona.trahe@intel.com, wei.zhao1@intel.com, ruifeng.wang@arm.com, qiming.yang@intel.com, qi.z.zhang@intel.com, Radu Nicolau <radu.nicolau@intel.com> Date: Wed, 23 Sep 2020 14:22:48 +0000 Message-Id: <20200923142253.18853-1-radu.nicolau@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <1591870283-7776-1-git-send-email-radu.nicolau@intel.com> References: <1591870283-7776-1-git-send-email-radu.nicolau@intel.com> Subject: [dpdk-dev] [PATCH v12 0/5] eal: add WC store functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> |
Series |
eal: add WC store functions
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Message
Radu Nicolau
Sept. 23, 2020, 2:22 p.m. UTC
Implement 2 new functions that will enable write combining stores depending on architecture. The functions are provided as a generic stub and a x86 specific implementation. The reason to implement these functions is to improve performance by reducing the overhead associated with regular mmio writes when updating the hardware queue tails and doorbells. With this patch set the I40E, ICE, IXGBE and QAT PMDs are updated to use the write combining store functions with other PMDs to follow. Radu Nicolau (5): eal: add WC store functions net/i40e: use WC store to update queue tail registers common/qat: use WC store to update queue tail registers net/ixgbe: use WC store to update queue tail registers net/ice: use WC store to update queue tail registers doc/guides/rel_notes/release_20_11.rst | 22 +++++++++ .../qat/qat_adf/adf_transport_access_macros.h | 6 ++- drivers/net/i40e/base/i40e_osdep.h | 5 ++ drivers/net/i40e/i40e_rxtx.c | 8 ++-- drivers/net/i40e/i40e_rxtx_vec_avx2.c | 4 +- drivers/net/i40e/i40e_rxtx_vec_sse.c | 4 +- drivers/net/ice/base/ice_osdep.h | 1 + drivers/net/ice/ice_rxtx.c | 6 +-- drivers/net/ice/ice_rxtx_vec_avx2.c | 4 +- drivers/net/ice/ice_rxtx_vec_sse.c | 4 +- drivers/net/ixgbe/base/ixgbe_osdep.h | 6 +++ drivers/net/ixgbe/ixgbe_rxtx.c | 15 +++--- drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c | 4 +- lib/librte_eal/arm/include/rte_io_64.h | 12 +++++ lib/librte_eal/include/generic/rte_io.h | 48 +++++++++++++++++++ lib/librte_eal/x86/include/rte_io.h | 42 ++++++++++++++++ 16 files changed, 165 insertions(+), 26 deletions(-)
Comments
On Wed, Sep 23, 2020 at 4:23 PM Radu Nicolau <radu.nicolau@intel.com> wrote: > > Implement 2 new functions that will enable write combining > stores depending on architecture. The functions are provided > as a generic stub and a x86 specific implementation. > > The reason to implement these functions is to improve performance > by reducing the overhead associated with regular mmio writes when > updating the hardware queue tails and doorbells. For the record, on which CPU/platform was this tested and how much of an improvement did you get with this? I did not see review/ack tokens from other arch maintainers, but since it has been on the ml for a while, I guess I can proceed as is. > > With this patch set the I40E, ICE, IXGBE and QAT PMDs are updated to > use the write combining store functions with other PMDs to follow. This series will go through the main repo: copying Ferruh and Akhil for info.
On 10/8/2020 8:28 AM, David Marchand wrote: > On Wed, Sep 23, 2020 at 4:23 PM Radu Nicolau <radu.nicolau@intel.com> wrote: >> Implement 2 new functions that will enable write combining >> stores depending on architecture. The functions are provided >> as a generic stub and a x86 specific implementation. >> >> The reason to implement these functions is to improve performance >> by reducing the overhead associated with regular mmio writes when >> updating the hardware queue tails and doorbells. > For the record, on which CPU/platform was this tested and how much of > an improvement did you get with this? The improvement varies a lot with the particular usecase and the PMD, so it's difficult to state a number, but there were cases with performance improvements going well into the double digits, with very small bursts applications seeing the most benefits. Tests were done on a Snow Ridge platform. > > I did not see review/ack tokens from other arch maintainers, but since > it has been on the ml for a while, I guess I can proceed as is. > > >> With this patch set the I40E, ICE, IXGBE and QAT PMDs are updated to >> use the write combining store functions with other PMDs to follow. > This series will go through the main repo: copying Ferruh and Akhil for info. > >
On 10/8/2020 8:28 AM, David Marchand wrote: > On Wed, Sep 23, 2020 at 4:23 PM Radu Nicolau <radu.nicolau@intel.com> wrote: >> >> Implement 2 new functions that will enable write combining >> stores depending on architecture. The functions are provided >> as a generic stub and a x86 specific implementation. >> >> The reason to implement these functions is to improve performance >> by reducing the overhead associated with regular mmio writes when >> updating the hardware queue tails and doorbells. > > For the record, on which CPU/platform was this tested and how much of > an improvement did you get with this? > > I did not see review/ack tokens from other arch maintainers, but since > it has been on the ml for a while, I guess I can proceed as is. > > >> >> With this patch set the I40E, ICE, IXGBE and QAT PMDs are updated to >> use the write combining store functions with other PMDs to follow. > > This series will go through the main repo: copying Ferruh and Akhil for info. > Sounds good to me, +1 to not separate the driver implementation from actual change.
On Wed, Sep 23, 2020 at 4:23 PM Radu Nicolau <radu.nicolau@intel.com> wrote: > > Implement 2 new functions that will enable write combining > stores depending on architecture. The functions are provided > as a generic stub and a x86 specific implementation. > > The reason to implement these functions is to improve performance > by reducing the overhead associated with regular mmio writes when > updating the hardware queue tails and doorbells. > > With this patch set the I40E, ICE, IXGBE and QAT PMDs are updated to > use the write combining store functions with other PMDs to follow. > > > Radu Nicolau (5): > eal: add WC store functions > net/i40e: use WC store to update queue tail registers > common/qat: use WC store to update queue tail registers > net/ixgbe: use WC store to update queue tail registers > net/ice: use WC store to update queue tail registers Series applied.