On 6/12/2020 4:23 AM, Guinan Sun wrote:
> Add a method to clear VFMBMEM memory.
Can you please give some context, what is "VFMBMEM memory", why need to clear
it, etc...?
> Add a method to toggle VF's TX queues as workaround
> for silicon errata.
'toggle' here means enable and disable the Tx queues right?
Will this 'ixgbe_toggle_txdctl()' function used by the driver, if so better to
have that change in the same patch to get the full context.
Are there two changes related to eachother, 'txdctl' & 'VFMBMEM ', if not can
you please seperate them?
>
> Signed-off-by: Piotr Pietruszewski <piotr.pietruszewski@intel.com>
> Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
<...>
> +/**
> + * ixgbe_clear_mbx - Clear Mailbox Memory
> + * @hw: pointer to the HW structure
> + * @vf_number: id of mailbox to write
> + *
> + * Set VFMBMEM of given VF to 0x0.
> + **/
> +s32 ixgbe_clear_mbx(struct ixgbe_hw *hw, u16 vf_number)
> +{
> + struct ixgbe_mbx_info *mbx = &hw->mbx;
> + s32 ret_val = IXGBE_SUCCESS;
> +
> + DEBUGFUNC("ixgbe_clear_mbx");
> +
> + if (mbx->ops.clear)
> + ret_val = mbx->ops.clear(hw, vf_number);
> +
> + return ret_val;
> +}
> +
> /**
> * ixgbe_poll_for_msg - Wait for message notification
> * @hw: pointer to the HW structure
> @@ -486,6 +506,7 @@ void ixgbe_init_mbx_params_vf(struct ixgbe_hw *hw)
> mbx->ops.check_for_msg = ixgbe_check_for_msg_vf;
> mbx->ops.check_for_ack = ixgbe_check_for_ack_vf;
> mbx->ops.check_for_rst = ixgbe_check_for_rst_vf;
> + mbx->ops.clear = NULL;
If it is not used why 'ixgbe_clear_mbx()' added?
Hi Ferruh
> -----Original Message-----
> From: Yigit, Ferruh
> Sent: Monday, June 22, 2020 7:59 PM
> To: Sun, GuinanX <guinanx.sun@intel.com>; dev@dpdk.org
> Cc: Pietruszewski, Piotr <piotr.pietruszewski@intel.com>
> Subject: Re: [dpdk-dev] [PATCH 01/21] net/ixgbe/base: clear VFMBMEM and
> toggle VF's Tx queues
>
> On 6/12/2020 4:23 AM, Guinan Sun wrote:
> > Add a method to clear VFMBMEM memory.
>
> Can you please give some context, what is "VFMBMEM memory", why need to
> clear it, etc...?
>
> > Add a method to toggle VF's TX queues as workaround for silicon
> > errata.
>
>
> 'toggle' here means enable and disable the Tx queues right?
> Will this 'ixgbe_toggle_txdctl()' function used by the driver, if so better to have
> that change in the same patch to get the full context.
>
> Are there two changes related to eachother, 'txdctl' & 'VFMBMEM ', if not can
> you please seperate them?
>
Sorry, our commit message caused you confusion.
Later V2 patch will modify the commit information and explain'txdctl' &'VFMBMEM'.
> >
> > Signed-off-by: Piotr Pietruszewski <piotr.pietruszewski@intel.com>
> > Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
>
> <...>
>
> > +/**
> > + * ixgbe_clear_mbx - Clear Mailbox Memory
> > + * @hw: pointer to the HW structure
> > + * @vf_number: id of mailbox to write
> > + *
> > + * Set VFMBMEM of given VF to 0x0.
> > + **/
> > +s32 ixgbe_clear_mbx(struct ixgbe_hw *hw, u16 vf_number) {
> > + struct ixgbe_mbx_info *mbx = &hw->mbx;
> > + s32 ret_val = IXGBE_SUCCESS;
> > +
> > + DEBUGFUNC("ixgbe_clear_mbx");
> > +
> > + if (mbx->ops.clear)
> > + ret_val = mbx->ops.clear(hw, vf_number);
> > +
> > + return ret_val;
> > +}
> > +
> > /**
> > * ixgbe_poll_for_msg - Wait for message notification
> > * @hw: pointer to the HW structure
> > @@ -486,6 +506,7 @@ void ixgbe_init_mbx_params_vf(struct ixgbe_hw *hw)
> > mbx->ops.check_for_msg = ixgbe_check_for_msg_vf;
> > mbx->ops.check_for_ack = ixgbe_check_for_ack_vf;
> > mbx->ops.check_for_rst = ixgbe_check_for_rst_vf;
> > + mbx->ops.clear = NULL;
>
> If it is not used why 'ixgbe_clear_mbx()' added?
@@ -1101,6 +1101,19 @@ s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
IXGBE_NOT_IMPLEMENTED);
}
+/**
+ * ixgbe_toggle_txdctl - Toggle VF's queues
+ * @hw: pointer to hardware structure
+ * @vind: VMDq pool index
+ *
+ * Enable and disable each queue in VF.
+ */
+s32 ixgbe_toggle_txdctl(struct ixgbe_hw *hw, u32 vind)
+{
+ return ixgbe_call_func(hw, hw->mac.ops.toggle_txdctl, (hw,
+ vind), IXGBE_NOT_IMPLEMENTED);
+}
+
/**
* ixgbe_fc_enable - Enable flow control
* @hw: pointer to hardware structure
@@ -101,6 +101,7 @@ s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,
s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
bool vlan_on, u32 *vfta_delta, u32 vfta,
bool vlvf_bypass);
+s32 ixgbe_toggle_txdctl(struct ixgbe_hw *hw, u32 vind);
s32 ixgbe_fc_enable(struct ixgbe_hw *hw);
s32 ixgbe_setup_fc(struct ixgbe_hw *hw);
s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
@@ -103,6 +103,7 @@ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
mac->ops.init_uta_tables = NULL;
mac->ops.enable_rx = ixgbe_enable_rx_generic;
mac->ops.disable_rx = ixgbe_disable_rx_generic;
+ mac->ops.toggle_txdctl = ixgbe_toggle_txdctl_generic;
/* Flow Control */
mac->ops.fc_enable = ixgbe_fc_enable_generic;
@@ -4103,6 +4104,61 @@ s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
return IXGBE_SUCCESS;
}
+/**
+ * ixgbe_toggle_txdctl_generic - Toggle VF's queues
+ * @hw: pointer to hardware structure
+ * @vf_number: VF index
+ *
+ * Enable and disable each queue in VF.
+ */
+s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vf_number)
+{
+ u8 queue_count, i;
+ u32 offset, reg;
+
+ if (vf_number > 63)
+ return IXGBE_ERR_PARAM;
+
+ /*
+ * Determine number of queues by checking
+ * number of virtual functions
+ */
+ reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
+ switch (reg & IXGBE_GCR_EXT_VT_MODE_MASK) {
+ case IXGBE_GCR_EXT_VT_MODE_64:
+ queue_count = 2;
+ break;
+ case IXGBE_GCR_EXT_VT_MODE_32:
+ queue_count = 4;
+ break;
+ case IXGBE_GCR_EXT_VT_MODE_16:
+ queue_count = 8;
+ break;
+ default:
+ return IXGBE_ERR_CONFIG;
+ }
+
+ /* Toggle queues */
+ for (i = 0; i < queue_count; ++i) {
+ /* Calculate offset of current queue */
+ offset = queue_count * vf_number + i;
+
+ /* Enable queue */
+ reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));
+ reg |= IXGBE_TXDCTL_ENABLE;
+ IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);
+ IXGBE_WRITE_FLUSH(hw);
+
+ /* Disable queue */
+ reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));
+ reg &= ~IXGBE_TXDCTL_ENABLE;
+ IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);
+ IXGBE_WRITE_FLUSH(hw);
+ }
+
+ return IXGBE_SUCCESS;
+}
+
/**
* ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
* @hw: pointer to hardware structure
@@ -111,6 +111,7 @@ s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
bool vlvf_bypass);
s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass);
+s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vind);
s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
ixgbe_link_speed *speed,
@@ -117,6 +117,26 @@ s32 ixgbe_check_for_rst(struct ixgbe_hw *hw, u16 mbx_id)
return ret_val;
}
+/**
+ * ixgbe_clear_mbx - Clear Mailbox Memory
+ * @hw: pointer to the HW structure
+ * @vf_number: id of mailbox to write
+ *
+ * Set VFMBMEM of given VF to 0x0.
+ **/
+s32 ixgbe_clear_mbx(struct ixgbe_hw *hw, u16 vf_number)
+{
+ struct ixgbe_mbx_info *mbx = &hw->mbx;
+ s32 ret_val = IXGBE_SUCCESS;
+
+ DEBUGFUNC("ixgbe_clear_mbx");
+
+ if (mbx->ops.clear)
+ ret_val = mbx->ops.clear(hw, vf_number);
+
+ return ret_val;
+}
+
/**
* ixgbe_poll_for_msg - Wait for message notification
* @hw: pointer to the HW structure
@@ -486,6 +506,7 @@ void ixgbe_init_mbx_params_vf(struct ixgbe_hw *hw)
mbx->ops.check_for_msg = ixgbe_check_for_msg_vf;
mbx->ops.check_for_ack = ixgbe_check_for_ack_vf;
mbx->ops.check_for_rst = ixgbe_check_for_rst_vf;
+ mbx->ops.clear = NULL;
mbx->stats.msgs_tx = 0;
mbx->stats.msgs_rx = 0;
@@ -702,6 +723,27 @@ STATIC s32 ixgbe_read_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size,
return ret_val;
}
+/**
+ * ixgbe_clear_mbx_pf - Clear Mailbox Memory
+ * @hw: pointer to the HW structure
+ * @vf_number: the VF index
+ *
+ * Set VFMBMEM of given VF to 0x0.
+ **/
+STATIC s32 ixgbe_clear_mbx_pf(struct ixgbe_hw *hw, u16 vf_number)
+{
+ u16 mbx_size = hw->mbx.size;
+ u16 i;
+
+ if (vf_number > 63)
+ return IXGBE_ERR_PARAM;
+
+ for (i = 0; i < mbx_size; ++i)
+ IXGBE_WRITE_REG_ARRAY(hw, IXGBE_PFMBMEM(vf_number), i, 0x0);
+
+ return IXGBE_SUCCESS;
+}
+
/**
* ixgbe_init_mbx_params_pf - set initial values for pf mailbox
* @hw: pointer to the HW structure
@@ -731,6 +773,7 @@ void ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw)
mbx->ops.check_for_msg = ixgbe_check_for_msg_pf;
mbx->ops.check_for_ack = ixgbe_check_for_ack_pf;
mbx->ops.check_for_rst = ixgbe_check_for_rst_pf;
+ mbx->ops.clear = ixgbe_clear_mbx_pf;
mbx->stats.msgs_tx = 0;
mbx->stats.msgs_rx = 0;
@@ -129,6 +129,7 @@ s32 ixgbe_write_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);
s32 ixgbe_check_for_msg(struct ixgbe_hw *, u16);
s32 ixgbe_check_for_ack(struct ixgbe_hw *, u16);
s32 ixgbe_check_for_rst(struct ixgbe_hw *, u16);
+s32 ixgbe_clear_mbx(struct ixgbe_hw *hw, u16 vf_number);
void ixgbe_init_mbx_ops_generic(struct ixgbe_hw *hw);
void ixgbe_init_mbx_params_vf(struct ixgbe_hw *);
void ixgbe_init_mbx_params_pf(struct ixgbe_hw *);
@@ -3997,6 +3997,7 @@ struct ixgbe_mac_operations {
s32 (*init_uta_tables)(struct ixgbe_hw *);
void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
+ s32 (*toggle_txdctl)(struct ixgbe_hw *hw, u32 vf_index);
s32 (*update_xcast_mode)(struct ixgbe_hw *, int);
s32 (*set_rlpml)(struct ixgbe_hw *, u16);
@@ -4155,6 +4156,7 @@ struct ixgbe_mbx_operations {
s32 (*check_for_msg)(struct ixgbe_hw *, u16);
s32 (*check_for_ack)(struct ixgbe_hw *, u16);
s32 (*check_for_rst)(struct ixgbe_hw *, u16);
+ s32 (*clear)(struct ixgbe_hw *hw, u16 vf_number);
};
struct ixgbe_mbx_stats {