[3/3] net/i40e/base: add constants for PTP pins

Message ID 20200325032356.20198-4-jiaqix.min@intel.com (mailing list archive)
State Superseded, archived
Delegated to: xiaolong ye
Headers
Series update i40e base code |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

Min, JiaqiX March 25, 2020, 3:23 a.m. UTC
  Introduce constants for handling PTP pins used for external
clock source.

Signed-off-by: Piotr Kwapulinski <piotr.kwapulinski@intel.com>
Signed-off-by: Jiaqi Min <jiaqix.min@intel.com>
---
 drivers/net/i40e/base/i40e_register.h | 4 ++++
 1 file changed, 4 insertions(+)
  

Comments

Kwapulinski, Piotr March 25, 2020, 10:03 a.m. UTC | #1
ACK

-----Original Message-----
From: Min, JiaqiX <jiaqix.min@intel.com> 
Sent: Wednesday, March 25, 2020 4:24 AM
To: dev@dpdk.org
Cc: Min, JiaqiX <jiaqix.min@intel.com>; Kwapulinski, Piotr <piotr.kwapulinski@intel.com>
Subject: [PATCH 3/3] net/i40e/base: add constants for PTP pins

Introduce constants for handling PTP pins used for external clock source.

Signed-off-by: Piotr Kwapulinski <piotr.kwapulinski@intel.com>
Signed-off-by: Jiaqi Min <jiaqix.min@intel.com>
---
 drivers/net/i40e/base/i40e_register.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/i40e_register.h
index 436f48efa..dffcc633c 100644
--- a/drivers/net/i40e/base/i40e_register.h
+++ b/drivers/net/i40e/base/i40e_register.h
@@ -2910,6 +2910,10 @@
 #define I40E_PRTTSYN_AUX_0_PULSEW_MASK   I40E_MASK(0xF, I40E_PRTTSYN_AUX_0_PULSEW_SHIFT)
 #define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16  #define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK  I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT)
+#define I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT 17 #define 
+I40E_PRTTSYN_AUX_0_PTPFLAG_MASK \
+		I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT) #define 
+I40E_PRTTSYN_AUX_0_PTP_OUT_SYNC_CLK_IO 0xF
 #define I40E_PRTTSYN_AUX_1(_i)               (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
 #define I40E_PRTTSYN_AUX_1_MAX_INDEX         1
 #define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT      0
--
2.17.1

--------------------------------------------------------------------

Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek
przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by
others is strictly prohibited.
  

Patch

diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/i40e_register.h
index 436f48efa..dffcc633c 100644
--- a/drivers/net/i40e/base/i40e_register.h
+++ b/drivers/net/i40e/base/i40e_register.h
@@ -2910,6 +2910,10 @@ 
 #define I40E_PRTTSYN_AUX_0_PULSEW_MASK   I40E_MASK(0xF, I40E_PRTTSYN_AUX_0_PULSEW_SHIFT)
 #define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16
 #define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK  I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT)
+#define I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT 17
+#define I40E_PRTTSYN_AUX_0_PTPFLAG_MASK \
+		I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT)
+#define I40E_PRTTSYN_AUX_0_PTP_OUT_SYNC_CLK_IO 0xF
 #define I40E_PRTTSYN_AUX_1(_i)               (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
 #define I40E_PRTTSYN_AUX_1_MAX_INDEX         1
 #define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT      0