crypto/nitrox: fix coverity defects
Checks
Commit Message
Address the defects reported by coverity: Unintended sign extension
and Out-of-bounds access.
Coverity issue: 349899, 349905, 349911, 349921, 349923, 349926
Fixes: 32e4930d5a3b ("crypto/nitrox: add hardware queue management")
Fixes: 9fdef0cc2385 ("crypto/nitrox: create symmetric cryptodev")
Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
---
drivers/crypto/nitrox/nitrox_csr.h | 18 +++++++++---------
drivers/crypto/nitrox/nitrox_sym.c | 3 ++-
2 files changed, 11 insertions(+), 10 deletions(-)
Comments
>
> Address the defects reported by coverity: Unintended sign extension
> and Out-of-bounds access.
>
> Coverity issue: 349899, 349905, 349911, 349921, 349923, 349926
>
> Fixes: 32e4930d5a3b ("crypto/nitrox: add hardware queue management")
> Fixes: 9fdef0cc2385 ("crypto/nitrox: create symmetric cryptodev")
>
> Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
> ---
Thomas,
Can you take this directly on master.
Thanks,
Akhil
20/02/2020 12:07, Akhil Goyal:
> >
> > Address the defects reported by coverity: Unintended sign extension
> > and Out-of-bounds access.
> >
> > Coverity issue: 349899, 349905, 349911, 349921, 349923, 349926
> >
> > Fixes: 32e4930d5a3b ("crypto/nitrox: add hardware queue management")
> > Fixes: 9fdef0cc2385 ("crypto/nitrox: create symmetric cryptodev")
> >
> > Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
> > ---
> Thomas,
>
> Can you take this directly on master.
No sorry, I can't because there is no review and test.
And I think we should not have general patches for Coverity defects.
Instead we must do one patch per issue. Here two:
- sign of constants
- out-of-bound access
In each patch, we must have a description of the consequence of the issue.
Thanks
@@ -12,15 +12,15 @@
#define NITROX_CSR_ADDR(bar_addr, offset) (bar_addr + (offset))
/* NPS packet registers */
-#define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060 + ((_i) * 0x40000))
-#define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068 + ((_i) * 0x40000))
-#define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070 + ((_i) * 0x40000))
-#define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080 + ((_i) * 0x40000))
-#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078 + ((_i) * 0x40000))
-#define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088 + ((_i) * 0x40000))
-#define NPS_PKT_SLC_CTLX(_i) (0x10000 + ((_i) * 0x40000))
-#define NPS_PKT_SLC_CNTSX(_i) (0x10008 + ((_i) * 0x40000))
-#define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010 + ((_i) * 0x40000))
+#define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088UL + ((_i) * 0x40000UL))
+#define NPS_PKT_SLC_CTLX(_i) (0x10000UL + ((_i) * 0x40000UL))
+#define NPS_PKT_SLC_CNTSX(_i) (0x10008UL + ((_i) * 0x40000UL))
+#define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010UL + ((_i) * 0x40000UL))
/* AQM Virtual Function Registers */
#define AQMQ_QSZX(_i) (0x20008 + ((_i)*0x40000))
@@ -683,7 +683,8 @@ nitrox_sym_pmd_create(struct nitrox_device *ndev)
struct rte_cryptodev *cdev;
rte_pci_device_name(&ndev->pdev->addr, name, sizeof(name));
- snprintf(name + strlen(name), RTE_CRYPTODEV_NAME_MAX_LEN, "_n5sym");
+ snprintf(name + strlen(name), RTE_CRYPTODEV_NAME_MAX_LEN - strlen(name),
+ "_n5sym");
ndev->rte_sym_dev.driver = &nitrox_rte_sym_drv;
ndev->rte_sym_dev.numa_node = ndev->pdev->device.numa_node;
ndev->rte_sym_dev.devargs = NULL;