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GET /api/patches/99347/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 99347,
    "url": "http://patches.dpdk.org/api/patches/99347/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210921110038.115560-2-hkalra@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210921110038.115560-2-hkalra@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210921110038.115560-2-hkalra@marvell.com",
    "date": "2021-09-21T11:00:38",
    "name": "[2/2] common/cnxk: cq overflow issue",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "d720ad202dfed506dfbb20ff7a81838e72a11948",
    "submitter": {
        "id": 1182,
        "url": "http://patches.dpdk.org/api/people/1182/?format=api",
        "name": "Harman Kalra",
        "email": "hkalra@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210921110038.115560-2-hkalra@marvell.com/mbox/",
    "series": [
        {
            "id": 19053,
            "url": "http://patches.dpdk.org/api/series/19053/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19053",
            "date": "2021-09-21T11:00:37",
            "name": "[1/2] common/cnxk: clear rvum interrupts",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/19053/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/99347/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/99347/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 487CDA0C4C;\n\tTue, 21 Sep 2021 13:01:03 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 35AAF410FA;\n\tTue, 21 Sep 2021 13:01:03 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id ADD08410F7\n for <dev@dpdk.org>; Tue, 21 Sep 2021 13:01:01 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18L99JBx005235\n for <dev@dpdk.org>; Tue, 21 Sep 2021 04:01:00 -0700",
            "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 3b7cgt88vk-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 21 Sep 2021 04:01:00 -0700",
            "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 21 Sep 2021 04:00:59 -0700",
            "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 21 Sep 2021 04:00:59 -0700",
            "from localhost.localdomain (unknown [10.29.52.211])\n by maili.marvell.com (Postfix) with ESMTP id 5F3CA3F706B;\n Tue, 21 Sep 2021 04:00:57 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=XBos2qS3rok7CCb3iznJ++OkTrZnATjQeGsTTkzSdo4=;\n b=c4RzwGhuExX31rGTtwMsHsYrDbzW4tac4Ch2mdPtjH0mBNXcmLmwXrJDeQnlAdrCZueQ\n jiiTJqbYP9D5Qp+xhmhC/55OkIRt4EgMHjjrWQCG/kgFilJLzrG94RJDpxse27dIP2QV\n iCPKK44l4mFCOAwlVWPSdK/zcnf6ARd69bm0WHXQHrR0xWSuYU09xM4HaW2cnUqW3k+c\n ZPvYEkkFZgpqn6EmZ127PcISKe/4cPqD7O9zD6I6p3A4zP0zRY6mIazdtH3qRIQKWTqY\n KIZS74/ThU9AI8wYZ1z3zxXLzxg9e7Z0EK5LXcuTU9keOAPVkDgvCU1WIGd0cVZCQy82 GA==",
        "From": "Harman Kalra <hkalra@marvell.com>",
        "To": "<dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>",
        "CC": "Harman Kalra <hkalra@marvell.com>",
        "Date": "Tue, 21 Sep 2021 16:30:38 +0530",
        "Message-ID": "<20210921110038.115560-2-hkalra@marvell.com>",
        "X-Mailer": "git-send-email 2.18.0",
        "In-Reply-To": "<20210921110038.115560-1-hkalra@marvell.com>",
        "References": "<20210921110038.115560-1-hkalra@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Proofpoint-ORIG-GUID": "fmcGzj_u7022ngmbKmauWCYJPsYOIBMu",
        "X-Proofpoint-GUID": "fmcGzj_u7022ngmbKmauWCYJPsYOIBMu",
        "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-09-21_01,2021-09-20_01,2020-04-07_01",
        "Subject": "[dpdk-dev] [PATCH 2/2] common/cnxk: cq overflow issue",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "An issue exists on some HW revisions whereby if a CQ overflows\nNIX may have undefined behavior, e.g. free incorrect buffers.\nImplementing a workaround for this known HW issue.\n\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n drivers/common/cnxk/roc_nix_priv.h  |  3 ++-\n drivers/common/cnxk/roc_nix_queue.c | 18 +++++++++++++++---\n 2 files changed, 17 insertions(+), 4 deletions(-)",
    "diff": "diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 9dc0c88a6f..1bd1b6a36b 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -17,7 +17,8 @@\n \n /* Apply BP/DROP when CQ is 95% full */\n #define NIX_CQ_THRESH_LEVEL\t(5 * 256 / 100)\n-#define NIX_RQ_AURA_THRESH(x)\t(((x) * 95) / 100)\n+#define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)\n+#define NIX_RQ_AURA_THRESH(x)\t(((x)*95) / 100)\n \n /* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */\n #define CQ_CQE_THRESH_DEFAULT\t0x1ULL\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex 76e439e7a9..d7c4844d69 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -2,6 +2,8 @@\n  * Copyright(C) 2021 Marvell.\n  */\n \n+#include <math.h>\n+\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n \n@@ -435,7 +437,6 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)\n \tcq->status = (int64_t *)(nix->base + NIX_LF_CQ_OP_STATUS);\n \tcq->wdata = (uint64_t)cq->qid << 32;\n \tcq->roc_nix = roc_nix;\n-\tcq->drop_thresh = NIX_CQ_THRESH_LEVEL;\n \n \t/* CQE of W16 */\n \tdesc_sz = cq->nb_desc * NIX_CQ_ENTRY_SZ;\n@@ -476,8 +477,19 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)\n \t/* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */\n \tcq_ctx->cint_idx = cq->qid;\n \n-\tcq_ctx->drop = cq->drop_thresh;\n-\tcq_ctx->drop_ena = 1;\n+\tif (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) {\n+\t\tconst float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;\n+\t\tuint16_t min_rx_drop;\n+\n+\t\tmin_rx_drop = ceil(rx_cq_skid / (float)cq->nb_desc);\n+\t\tcq_ctx->drop = min_rx_drop;\n+\t\tcq_ctx->drop_ena = 1;\n+\t\tcq->drop_thresh = min_rx_drop;\n+\t} else {\n+\t\tcq->drop_thresh = NIX_CQ_THRESH_LEVEL;\n+\t\tcq_ctx->drop = cq->drop_thresh;\n+\t\tcq_ctx->drop_ena = 1;\n+\t}\n \n \t/* TX pause frames enable flow ctrl on RX side */\n \tif (nix->tx_pause) {\n",
    "prefixes": [
        "2/2"
    ]
}