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GET /api/patches/99181/?format=api
{ "id": 99181, "url": "http://patches.dpdk.org/api/patches/99181/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210917140252.2999006-14-kevin.laatz@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210917140252.2999006-14-kevin.laatz@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210917140252.2999006-14-kevin.laatz@intel.com", "date": "2021-09-17T14:02:49", "name": "[v4,13/16] dma/idxd: add burst capacity API", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4e305b143fb592c162ea6ce30e851d661fca3540", "submitter": { "id": 921, "url": "http://patches.dpdk.org/api/people/921/?format=api", "name": "Kevin Laatz", "email": "kevin.laatz@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210917140252.2999006-14-kevin.laatz@intel.com/mbox/", "series": [ { "id": 19018, "url": "http://patches.dpdk.org/api/series/19018/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19018", "date": "2021-09-17T14:02:36", "name": "add dmadev driver for idxd devices", "version": 4, "mbox": "http://patches.dpdk.org/series/19018/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/99181/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/99181/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 81798A0C46;\n\tFri, 17 Sep 2021 16:04:52 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 61F214118B;\n\tFri, 17 Sep 2021 16:03:42 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id 6D83D41179\n for <dev@dpdk.org>; Fri, 17 Sep 2021 16:03:37 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 17 Sep 2021 07:03:37 -0700", "from silpixa00401122.ir.intel.com ([10.55.128.10])\n by fmsmga006.fm.intel.com with ESMTP; 17 Sep 2021 07:03:35 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10109\"; a=\"219614951\"", "E=Sophos;i=\"5.85,301,1624345200\"; d=\"scan'208\";a=\"219614951\"", "E=Sophos;i=\"5.85,301,1624345200\"; d=\"scan'208\";a=\"699496308\"" ], "X-ExtLoop1": "1", "From": "Kevin Laatz <kevin.laatz@intel.com>", "To": "dev@dpdk.org", "Cc": "bruce.richardson@intel.com, fengchengwen@huawei.com, jerinj@marvell.com,\n conor.walsh@intel.com, Kevin Laatz <kevin.laatz@intel.com>", "Date": "Fri, 17 Sep 2021 14:02:49 +0000", "Message-Id": "<20210917140252.2999006-14-kevin.laatz@intel.com>", "X-Mailer": "git-send-email 2.30.2", "In-Reply-To": "<20210917140252.2999006-1-kevin.laatz@intel.com>", "References": "<20210827172048.558704-1-kevin.laatz@intel.com>\n <20210917140252.2999006-1-kevin.laatz@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v4 13/16] dma/idxd: add burst capacity API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for the burst capacity API. This API will provide the calling\napplication with the remaining capacity of the current burst (limited by\nmax HW batch size).\n\nSigned-off-by: Kevin Laatz <kevin.laatz@intel.com>\nReviewed-by: Conor Walsh <conor.walsh@intel.com>\n---\n drivers/dma/idxd/idxd_bus.c | 1 +\n drivers/dma/idxd/idxd_common.c | 20 ++++++++++++++++++++\n drivers/dma/idxd/idxd_internal.h | 1 +\n drivers/dma/idxd/idxd_pci.c | 2 ++\n 4 files changed, 24 insertions(+)", "diff": "diff --git a/drivers/dma/idxd/idxd_bus.c b/drivers/dma/idxd/idxd_bus.c\nindex e6caa048a9..54129e5083 100644\n--- a/drivers/dma/idxd/idxd_bus.c\n+++ b/drivers/dma/idxd/idxd_bus.c\n@@ -102,6 +102,7 @@ static const struct rte_dma_dev_ops idxd_bus_ops = {\n \t\t.stats_get = idxd_stats_get,\n \t\t.stats_reset = idxd_stats_reset,\n \t\t.vchan_status = idxd_vchan_status,\n+\t\t.burst_capacity = idxd_burst_capacity,\n };\n \n static void *\ndiff --git a/drivers/dma/idxd/idxd_common.c b/drivers/dma/idxd/idxd_common.c\nindex 87d84c081e..b31611c8a4 100644\n--- a/drivers/dma/idxd/idxd_common.c\n+++ b/drivers/dma/idxd/idxd_common.c\n@@ -469,6 +469,26 @@ idxd_info_get(const struct rte_dma_dev *dev, struct rte_dma_info *info, uint32_t\n \treturn 0;\n }\n \n+uint16_t\n+idxd_burst_capacity(const struct rte_dma_dev *dev, uint16_t vchan __rte_unused)\n+{\n+\tstruct idxd_dmadev *idxd = dev->dev_private;\n+\tuint16_t write_idx = idxd->batch_start + idxd->batch_size;\n+\tuint16_t used_space;\n+\n+\t/* Check for space in the batch ring */\n+\tif ((idxd->batch_idx_read == 0 && idxd->batch_idx_write == idxd->max_batches) ||\n+\t\t\tidxd->batch_idx_write + 1 == idxd->batch_idx_read)\n+\t\treturn 0;\n+\n+\t/* For descriptors, check for wrap-around on write but not read */\n+\tif (idxd->ids_returned > write_idx)\n+\t\twrite_idx += idxd->desc_ring_mask + 1;\n+\tused_space = write_idx - idxd->ids_returned;\n+\n+\treturn RTE_MIN((idxd->desc_ring_mask - used_space), idxd->max_batch_size);\n+}\n+\n int\n idxd_configure(struct rte_dma_dev *dev __rte_unused, const struct rte_dma_conf *dev_conf,\n \t\tuint32_t conf_sz)\ndiff --git a/drivers/dma/idxd/idxd_internal.h b/drivers/dma/idxd/idxd_internal.h\nindex a291ad26d9..3ef2f729a8 100644\n--- a/drivers/dma/idxd/idxd_internal.h\n+++ b/drivers/dma/idxd/idxd_internal.h\n@@ -103,5 +103,6 @@ int idxd_stats_get(const struct rte_dma_dev *dev, uint16_t vchan,\n int idxd_stats_reset(struct rte_dma_dev *dev, uint16_t vchan);\n int idxd_vchan_status(const struct rte_dma_dev *dev, uint16_t vchan,\n \t\tenum rte_dma_vchan_status *status);\n+uint16_t idxd_burst_capacity(const struct rte_dma_dev *dev, uint16_t vchan);\n \n #endif /* _IDXD_INTERNAL_H_ */\ndiff --git a/drivers/dma/idxd/idxd_pci.c b/drivers/dma/idxd/idxd_pci.c\nindex 2464d4a06c..03ddd63f38 100644\n--- a/drivers/dma/idxd/idxd_pci.c\n+++ b/drivers/dma/idxd/idxd_pci.c\n@@ -119,6 +119,7 @@ static const struct rte_dma_dev_ops idxd_pci_ops = {\n \t.dev_start = idxd_pci_dev_start,\n \t.dev_stop = idxd_pci_dev_stop,\n \t.vchan_status = idxd_vchan_status,\n+\t.burst_capacity = idxd_burst_capacity,\n };\n \n /* each portal uses 4 x 4k pages */\n@@ -232,6 +233,7 @@ init_pci_device(struct rte_pci_device *dev, struct idxd_dmadev *idxd,\n \n \tidxd->u.pci = pci;\n \tidxd->max_batches = wq_size;\n+\tidxd->max_batch_size = 1 << lg2_max_batch;\n \n \t/* enable the device itself */\n \terr_code = idxd_pci_dev_command(idxd, idxd_enable_dev);\n", "prefixes": [ "v4", "13/16" ] }