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GET /api/patches/98832/?format=api
{ "id": 98832, "url": "http://patches.dpdk.org/api/patches/98832/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210914053833.7760-9-talshn@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210914053833.7760-9-talshn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210914053833.7760-9-talshn@nvidia.com", "date": "2021-09-14T05:38:31", "name": "[RFC,08/10] crypto/mlx5: use OS agnostic functions for Verbs operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a06a55e5bd057b2dec5342a29d8ab07e6d147072", "submitter": { "id": 1893, "url": "http://patches.dpdk.org/api/people/1893/?format=api", "name": "Tal Shnaiderman", "email": "talshn@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210914053833.7760-9-talshn@nvidia.com/mbox/", "series": [ { "id": 18890, "url": "http://patches.dpdk.org/api/series/18890/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18890", "date": "2021-09-14T05:38:23", "name": "Support MLX5 crypto driver on Windows", "version": 1, "mbox": "http://patches.dpdk.org/series/18890/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/98832/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/98832/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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SFS:(4636009)(136003)(39860400002)(396003)(346002)(376002)(46966006)(36840700001)(47076005)(5660300002)(2616005)(4326008)(86362001)(8676002)(70586007)(2906002)(186003)(1076003)(82310400003)(16526019)(26005)(36756003)(356005)(8936002)(83380400001)(70206006)(82740400003)(316002)(54906003)(55016002)(7696005)(36860700001)(426003)(107886003)(6916009)(6286002)(336012)(6666004)(7636003)(478600001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "14 Sep 2021 05:40:13.5309 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n abaf2a6e-676e-4c14-842a-08d977421fe7", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.32];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT019.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB4921", "Subject": "[dpdk-dev] [RFC PATCH 08/10] crypto/mlx5: use OS agnostic functions\n for Verbs operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "use the functions mlx5_os_open_device_context, mlx5_os_get_ctx_device_name\nmlx5_os_reg_mr mlx5_os_dereg_mr instead of the ib verbs functions\nand variables to support device operations on all OSs.\n\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 41 +++++++++++++++++----------------------\n drivers/crypto/mlx5/mlx5_crypto.h | 2 +-\n 2 files changed, 19 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 35319d0115..3f5a6745dc 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -796,9 +796,6 @@ mlx5_crypto_hw_global_release(struct mlx5_crypto_priv *priv)\n static int\n mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv)\n {\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-\tstruct mlx5dv_obj obj;\n-\tstruct mlx5dv_pd pd_info;\n \tint ret;\n \n \tpriv->pd = mlx5_os_alloc_pd(priv->ctx);\n@@ -814,11 +811,6 @@ mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv)\n \t\treturn -errno;\n \t}\n \treturn 0;\n-#else\n-\t(void)priv;\n-\tDRV_LOG(ERR, \"Cannot get pdn - no DV support.\");\n-\treturn -ENOTSUP;\n-#endif /* HAVE_IBV_FLOW_DV_SUPPORT */\n }\n \n static int\n@@ -964,8 +956,8 @@ mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n \t\t/* Iterate all the existing mlx5 devices. */\n \t\tTAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next)\n \t\t\tmlx5_free_mr_by_addr(&priv->mr_scache,\n-\t\t\t\t\t priv->ctx->device->name,\n-\t\t\t\t\t addr, len);\n+\t\t\t\t\t mlx5_os_get_ctx_device_name(\n+\t\t\t\t\t priv->ctx), addr, len);\n \t\tpthread_mutex_unlock(&priv_list_lock);\n \t\tbreak;\n \tcase RTE_MEM_EVENT_ALLOC:\n@@ -977,9 +969,9 @@ mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n static int\n mlx5_crypto_dev_probe(struct rte_device *dev)\n {\n-\tstruct ibv_device *ibv;\n \tstruct rte_cryptodev *crypto_dev;\n-\tstruct ibv_context *ctx;\n+\tvoid *ctx;\n+\tconst char *device_name;\n \tstruct mlx5_devx_obj *login;\n \tstruct mlx5_crypto_priv *priv;\n \tstruct mlx5_crypto_devarg_params devarg_prms = { 0 };\n@@ -999,15 +991,19 @@ mlx5_crypto_dev_probe(struct rte_device *dev)\n \t\trte_errno = ENOTSUP;\n \t\treturn -rte_errno;\n \t}\n-\tibv = mlx5_os_get_ibv_dev(dev);\n-\tif (ibv == NULL)\n-\t\treturn -rte_errno;\n-\tctx = mlx5_glue->dv_open_device(ibv);\n+\tctx = mlx5_os_open_device_context(dev);\n \tif (ctx == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to open IB device \\\"%s\\\".\", ibv->name);\n+\t\tDRV_LOG(ERR, \"Failed to open IB device.\");\n \t\trte_errno = ENODEV;\n \t\treturn -rte_errno;\n \t}\n+\tdevice_name = mlx5_os_get_ctx_device_name(ctx);\n+\tif (!device_name) {\n+\t\tDRV_LOG(ERR, \"Failed getting device name\");\n+\t\tclaim_zero(mlx5_glue->close_device(ctx));\n+\t\trte_errno = ENODEV;\n+\t\treturn -ENODEV;\n+\t}\n \tif (mlx5_devx_cmd_query_hca_attr(ctx, &attr) != 0 ||\n \t attr.crypto == 0 || attr.aes_xts == 0) {\n \t\tDRV_LOG(ERR, \"Not enough capabilities to support crypto \"\n@@ -1029,15 +1025,14 @@ mlx5_crypto_dev_probe(struct rte_device *dev)\n \t\tclaim_zero(mlx5_glue->close_device(ctx));\n \t\treturn -rte_errno;\n \t}\n-\tcrypto_dev = rte_cryptodev_pmd_create(ibv->name, dev,\n-\t\t\t\t\t&init_params);\n+\tcrypto_dev = rte_cryptodev_pmd_create(device_name, dev, &init_params);\n \tif (crypto_dev == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to create device \\\"%s\\\".\", ibv->name);\n+\t\tDRV_LOG(ERR, \"Failed to create device \\\"%s\\\".\", device_name);\n \t\tclaim_zero(mlx5_glue->close_device(ctx));\n \t\treturn -ENODEV;\n \t}\n \tDRV_LOG(INFO,\n-\t\t\"Crypto device %s was created successfully.\", ibv->name);\n+\t\t\"Crypto device %s was created successfully.\", device_name);\n \tcrypto_dev->dev_ops = &mlx5_crypto_ops;\n \tcrypto_dev->dequeue_burst = mlx5_crypto_dequeue_burst;\n \tcrypto_dev->enqueue_burst = mlx5_crypto_enqueue_burst;\n@@ -1061,8 +1056,8 @@ mlx5_crypto_dev_probe(struct rte_device *dev)\n \t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n \t}\n-\tpriv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;\n-\tpriv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;\n+\tpriv->mr_scache.reg_mr_cb = mlx5_os_reg_mr;\n+\tpriv->mr_scache.dereg_mr_cb = mlx5_os_dereg_mr;\n \tpriv->keytag = rte_cpu_to_be_64(devarg_prms.keytag);\n \tpriv->max_segs_num = devarg_prms.max_segs_num;\n \tpriv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) +\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 91e3f438b8..57461a8a33 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -19,7 +19,7 @@\n \n struct mlx5_crypto_priv {\n \tTAILQ_ENTRY(mlx5_crypto_priv) next;\n-\tstruct ibv_context *ctx; /* Device context. */\n+\tvoid *ctx; /* Device context. */\n \tstruct rte_cryptodev *crypto_dev;\n \tvoid *uar; /* User Access Region. */\n \tvolatile uint64_t *uar_addr;\n", "prefixes": [ "RFC", "08/10" ] }