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GET /api/patches/98830/?format=api
{ "id": 98830, "url": "http://patches.dpdk.org/api/patches/98830/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210914053833.7760-7-talshn@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210914053833.7760-7-talshn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210914053833.7760-7-talshn@nvidia.com", "date": "2021-09-14T05:38:29", "name": "[RFC,06/10] crypto/mlx5: use OS agnostic functions for UMEM operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a19c1b17f9dc8648811d661a82c43d474e3dbf6f", "submitter": { "id": 1893, "url": "http://patches.dpdk.org/api/people/1893/?format=api", "name": "Tal Shnaiderman", "email": "talshn@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210914053833.7760-7-talshn@nvidia.com/mbox/", "series": [ { "id": 18890, "url": "http://patches.dpdk.org/api/series/18890/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18890", "date": "2021-09-14T05:38:23", "name": "Support MLX5 crypto driver on Windows", "version": 1, "mbox": "http://patches.dpdk.org/series/18890/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/98830/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/98830/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 344CCA0C47;\n\tTue, 14 Sep 2021 07:40:40 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1031741121;\n\tTue, 14 Sep 2021 07:40:14 +0200 (CEST)", "from NAM04-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam08on2043.outbound.protection.outlook.com [40.107.101.43])\n by mails.dpdk.org (Postfix) with ESMTP id D85AF41130\n for <dev@dpdk.org>; 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mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.36) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=pRnlv0VKhi9gjOrWEq9QOyJNt8YxmrOK7u4BnLJqysw=;\n b=EIKykGPv4SNKVIBQtjUdWAcfeZXoQHIPqVZdT98OooayqTb8wbNlqoMwW1pZUekENy/mSfE4wHxoK4dahaBO7ssFlvvosWrjjO7gE3XyG5pmT3ukqZf60rkO8JNwe8Qxc75NxS7/MIypWNtVqvyEClaAzzIs+JiUYZY3KLGZqVZSAFCuxY6I1rYGJg4UGOtipgfug7S+DiYHD9+45dP9LK2gaSVhl+c7GMLO0SXG+uGmIzs+tQtk32/P632GSvGokYXBrjmog4rl6JNx1+OcyICUiJ38aGcsiA7rGhuQY3AjRvKzxwpx+rRjJOQ+hd0mFW6kyYw/gZ1te1dc6qO8tw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.36)\n smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed)\n header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.36 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.36; helo=mail.nvidia.com;", "From": "Tal Shnaiderman <talshn@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <matan@nvidia.com>, <rasland@nvidia.com>,\n <asafp@nvidia.com>, <gakhil@marvell.com>, <declan.doherty@intel.com>,\n <viacheslavo@nvidia.com>, <eilong@nvidia.com>", "Date": "Tue, 14 Sep 2021 08:38:29 +0300", "Message-ID": "<20210914053833.7760-7-talshn@nvidia.com>", "X-Mailer": "git-send-email 2.16.1.windows.4", "In-Reply-To": "<20210914053833.7760-1-talshn@nvidia.com>", "References": "<20210914053833.7760-1-talshn@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n DRHQMAIL107.nvidia.com (10.27.9.16)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "a890622a-35d6-4ed5-e848-08d977421da2", "X-MS-TrafficTypeDiagnostic": "BN6PR1201MB0148:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BN6PR1201MB01482F1787C6259A55E726A4A4DA9@BN6PR1201MB0148.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:635;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n /m1iuPh9HpaIyVeRdC8EqtvCGtWU2gnVqqJY7WDhx7A5cAjfqrw6CSUOi+oAaByYe6dOTwA7iv4PT2uzDW9GsWN/WCHniNJdCb1rkSHbaA/h1MTDOTyAkqOQD5PuIQgn9DaoJXY+h7SKnmZrqOlWuKoLWvb2rAk49X2o0i/+Ic0RzEG5QcIQt383dwmWTkagUtKHZ4hMuH7ia+2PgQgF+x5wLpsQaP3YK7i7uEWk7cJ57K9Sk2EmOYLHLDzksLdZi39cugz+gjNG0apRZlP3CbrAZaRPVuuYR42BAeERkBRshqm1movCz6W6uB2x1LzgKjuIx3wxCadqWhUJTMN9ZAlNqQ+IoFJxtrjbcloEG3jGhNLh2LsmuiZNrUmK9C7KDix08Ema+6G6w2b6BZu4PvHItQg1iqtW4fZJybBXMWE51Ov+0Cq2HNICLFXGS/iMRvilgiOY4ivScWWEyDluhdRNFXwmGYKqXEyN0gGF5OVq6znveHi5Z1kmXulMFA84yTatfQxP7KCrpNUpKtlhxXa1T92WjSy31kVoUEJZ2dF9UJl0Y8sK35rGFRHNW8Ye7JsKdD7N65Bmzc0o8XAzxdwp+4UVw2g0GMNA8IHqg4Btjjx8p84o4Jt6ouCBOi/lVv9P4dJwE23N+wSA/WUEm/I6BqzCRcGP3ofPNZeT6Cq5Vl91mR3DTTpl/hrKhwcP7qar+300f87cmL/RafoQig==", "X-Forefront-Antispam-Report": "CIP:216.228.112.36; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid05.nvidia.com; CAT:NONE;\n SFS:(4636009)(376002)(346002)(39860400002)(136003)(396003)(46966006)(36840700001)(6666004)(70206006)(70586007)(5660300002)(47076005)(26005)(16526019)(36860700001)(4326008)(186003)(8676002)(55016002)(356005)(86362001)(107886003)(82310400003)(478600001)(8936002)(7636003)(6916009)(2616005)(426003)(336012)(82740400003)(6286002)(83380400001)(36756003)(1076003)(36906005)(7696005)(54906003)(316002)(2906002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "14 Sep 2021 05:40:09.7208 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a890622a-35d6-4ed5-e848-08d977421da2", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.36];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT051.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN6PR1201MB0148", "Subject": "[dpdk-dev] [RFC PATCH 06/10] crypto/mlx5: use OS agnostic functions\n for UMEM operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "use the functions mlx5_os_umem_reg, mlx5_os_umem_dereg\nmlx5_os_get_umem_id instead of the glue functions to support\nUMEM operations on all OSs.\n\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 14 +++++++-------\n drivers/crypto/mlx5/mlx5_crypto.h | 2 +-\n 2 files changed, 8 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 3dac69f860..ccae113770 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -261,7 +261,7 @@ mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)\n \tif (qp->qp_obj != NULL)\n \t\tclaim_zero(mlx5_devx_cmd_destroy(qp->qp_obj));\n \tif (qp->umem_obj != NULL)\n-\t\tclaim_zero(mlx5_glue->devx_umem_dereg(qp->umem_obj));\n+\t\tclaim_zero(mlx5_os_umem_dereg(qp->umem_obj));\n \tif (qp->umem_buf != NULL)\n \t\trte_free(qp->umem_buf);\n \tmlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);\n@@ -682,10 +682,10 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\trte_errno = ENOMEM;\n \t\tgoto error;\n \t}\n-\tqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,\n-\t\t\t\t\t (void *)(uintptr_t)qp->umem_buf,\n-\t\t\t\t\t umem_size,\n-\t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n+\tqp->umem_obj = mlx5_os_umem_reg(priv->ctx,\n+\t\t\t\t\t(void *)(uintptr_t)qp->umem_buf,\n+\t\t\t\t\tumem_size,\n+\t\t\t\t\tIBV_ACCESS_LOCAL_WRITE);\n \tif (qp->umem_obj == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to register QP umem.\");\n \t\tgoto error;\n@@ -705,9 +705,9 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \tattr.rq_size = 0;\n \tattr.sq_size = RTE_BIT32(log_nb_desc);\n \tattr.dbr_umem_valid = 1;\n-\tattr.wq_umem_id = qp->umem_obj->umem_id;\n+\tattr.wq_umem_id = mlx5_os_get_umem_id(qp->umem_obj);\n \tattr.wq_umem_offset = 0;\n-\tattr.dbr_umem_id = qp->umem_obj->umem_id;\n+\tattr.dbr_umem_id = mlx5_os_get_umem_id(qp->umem_obj);\n \tattr.dbr_address = RTE_BIT64(log_nb_desc) * priv->wqe_set_size;\n \tqp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr);\n \tif (qp->qp_obj == NULL) {\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex d49b0001f0..d5cc509e42 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -45,7 +45,7 @@ struct mlx5_crypto_qp {\n \tstruct mlx5_devx_cq cq_obj;\n \tstruct mlx5_devx_obj *qp_obj;\n \tstruct rte_cryptodev_stats stats;\n-\tstruct mlx5dv_devx_umem *umem_obj;\n+\tvoid *umem_obj;\n \tvoid *umem_buf;\n \tvolatile uint32_t *db_rec;\n \tstruct rte_crypto_op **ops;\n", "prefixes": [ "RFC", "06/10" ] }