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{
    "id": 98735,
    "url": "http://patches.dpdk.org/api/patches/98735/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210911153041.28510-14-venkatkumar.duvvuru@broadcom.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210911153041.28510-14-venkatkumar.duvvuru@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210911153041.28510-14-venkatkumar.duvvuru@broadcom.com",
    "date": "2021-09-11T15:30:41",
    "name": "[v3,13/13] net/bnxt: add enhancements to TF ULP",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "2caa380d71978ff44391779850996f7ffeb3690d",
    "submitter": {
        "id": 1635,
        "url": "http://patches.dpdk.org/api/people/1635/?format=api",
        "name": "Venkat Duvvuru",
        "email": "venkatkumar.duvvuru@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "http://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210911153041.28510-14-venkatkumar.duvvuru@broadcom.com/mbox/",
    "series": [
        {
            "id": 18856,
            "url": "http://patches.dpdk.org/api/series/18856/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18856",
            "date": "2021-09-11T15:30:28",
            "name": "enhancements to host based flow table management",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/18856/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/98735/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/98735/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B8584A0C4B;\n\tMon, 13 Sep 2021 10:06:52 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2BF9F410EF;\n\tMon, 13 Sep 2021 10:06:24 +0200 (CEST)",
            "from relay.smtp-ext.broadcom.com (lpdvacalvio01.broadcom.com\n [192.19.166.228])\n by mails.dpdk.org (Postfix) with ESMTP id 52B2740E32\n for <dev@dpdk.org>; Sat, 11 Sep 2021 17:31:08 +0200 (CEST)",
            "from S60.dhcp.broadcom.net (unknown [10.123.66.170])\n (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n (No client certificate requested)\n by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 0354E7A48;\n Sat, 11 Sep 2021 08:31:05 -0700 (PDT)"
        ],
        "DKIM-Filter": "OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 0354E7A48",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n s=dkimrelay; t=1631374267;\n bh=U6uhFWL+GtDKaE5P1jCi7X50CkPJ5T7L4dGYLccqKV4=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=hn5sU1dtGzET3Lpi+i8XlOVddSsXq7D+fYhC4N/589Iz2DpvlGF7VFXbSU9hLxG6+\n Jj664MQwzKkK7z6cH6uvhsjbYE1hh7T5+Pk2kRaM7cZmOlpzUfOm2aVa+U7Khvt44o\n Tau2gCHgvIoVe6wvq2xokgdzlfxn1yW6JWpPBEaY=",
        "From": "Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "Kishore Padmanabha <kishore.padmanabha@broadcom.com>,\n Mike Baucom <michael.baucom@broadcom.com>,\n Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "Date": "Sat, 11 Sep 2021 21:00:41 +0530",
        "Message-Id": "<20210911153041.28510-14-venkatkumar.duvvuru@broadcom.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20210911153041.28510-1-venkatkumar.duvvuru@broadcom.com>",
        "References": "<20210908050643.9989-1-venkatkumar.duvvuru@broadcom.com>\n <20210911153041.28510-1-venkatkumar.duvvuru@broadcom.com>",
        "X-Mailman-Approved-At": "Mon, 13 Sep 2021 10:06:19 +0200",
        "Subject": "[dpdk-dev] [PATCH v3 13/13] net/bnxt: add enhancements to TF ULP",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\n\n1. Added support to specify l4 port masks in the template. Also enabled\n   source mac in the wild card key for ingress flows.\n\n2. Added support to enable offload for ipv6 traffic within the vxlan\n   tunnel connection.\n\n3. The flow counters is reduced from 7168 to 6912 for Whitney.\n   The stats operation is updated to reflect counts for packets\n   at egress from CFA instead of ingress to CFA\n\n4. The miss path for the l2 context table is updated with correct\n   parif and default action handler to handle the miss path for\n   egress flows.\n\n5. This support enables allocation of encapsulation, modification and\n   action records dynamically based on a given flow actions.\n\n6. Reduce the l2context resource requests during open_session. Move the\n   SMAC from the L2Context to the EM/WM\n\n7. Remap the parif in the bd action in order to eliminate incorrect\n   replication of broadcast packets. The layer 4 source port mask\n   was incorrectly updated in the outer layer 4 source port mask\n   instead of inner layer 4. Add the l3 proto to egress rules, switch\n   to using computed fields for l4 ports, add internal smac to f1/f2\n   flows, add l3 proto to ingress ipv6 flows\n\nSigned-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\nSigned-off-by: Mike Baucom <michael.baucom@broadcom.com>\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\nReviewed-by: Randy Schacher <stuart.schacher@broadcom.com>\n---\n drivers/net/bnxt/tf_core/tf_tbl_sram.c        |    7 -\n .../generic_templates/ulp_template_db_class.c | 8102 ++++++++++++-----\n .../generic_templates/ulp_template_db_enum.h  |  675 +-\n .../generic_templates/ulp_template_db_field.h |  195 +-\n .../generic_templates/ulp_template_db_tbl.c   | 2136 ++++-\n .../ulp_template_db_thor_act.c                |  996 +-\n .../ulp_template_db_thor_class.c              | 7495 ++++++++-------\n .../ulp_template_db_wh_plus_class.c           |   14 +-\n drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c         |    4 +-\n drivers/net/bnxt/tf_ulp/ulp_mapper.c          |  135 +-\n drivers/net/bnxt/tf_ulp/ulp_rte_parser.c      |  175 +-\n drivers/net/bnxt/tf_ulp/ulp_template_struct.h |   10 +\n drivers/net/bnxt/tf_ulp/ulp_utils.c           |    3 +-\n 13 files changed, 13538 insertions(+), 6409 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c\nindex 167078a8c6..636811bc2d 100644\n--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c\n+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c\n@@ -134,11 +134,6 @@ static int tf_tbl_sram_get_info(struct tf_tbl_sram_get_info_parms *parms)\n \tif (slices)\n \t\tparms->slice_size = tf_tbl_sram_slices_2_size[slices];\n \n-\tTFP_DRV_LOG(DEBUG,\n-\t\t    \"(%s) bank(%s) slice_size(%s)\\n\",\n-\t\t    tf_tbl_type_2_str(parms->tbl_type),\n-\t\t    tf_sram_bank_2_str(parms->bank_id),\n-\t\t    tf_sram_slice_2_str(parms->slice_size));\n \treturn rc;\n }\n \n@@ -373,7 +368,6 @@ tf_tbl_sram_free(struct tf *tfp __rte_unused,\n \t\treturn rc;\n \t}\n \n-\n #if (DBG_SRAM == 1)\n \t{\n \t\tstruct tf_sram_mgr_dump_parms dparms;\n@@ -411,7 +405,6 @@ tf_tbl_sram_set(struct tf *tfp,\n \tvoid *sram_handle = NULL;\n \tuint16_t base = 0, shift = 0;\n \n-\n \tTF_CHECK_PARMS3(tfp, parms, parms->data);\n \n \t/* Retrieve the session information */\ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c\nindex f74687acfa..ad3866243d 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Thu May 20 11:56:39 2021 */\n+/* date: Fri Aug  6 11:15:47 2021 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -362,508 +362,652 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {\n \t[BNXT_ULP_CLASS_HID_315d] = 344,\n \t[BNXT_ULP_CLASS_HID_3612] = 345,\n \t[BNXT_ULP_CLASS_HID_66da] = 346,\n-\t[BNXT_ULP_CLASS_HID_6165] = 347,\n-\t[BNXT_ULP_CLASS_HID_2aa1] = 348,\n-\t[BNXT_ULP_CLASS_HID_09cd] = 349,\n-\t[BNXT_ULP_CLASS_HID_3845] = 350,\n-\t[BNXT_ULP_CLASS_HID_11e9] = 351,\n-\t[BNXT_ULP_CLASS_HID_4361] = 352,\n-\t[BNXT_ULP_CLASS_HID_218d] = 353,\n-\t[BNXT_ULP_CLASS_HID_5105] = 354,\n-\t[BNXT_ULP_CLASS_HID_0c89] = 355,\n-\t[BNXT_ULP_CLASS_HID_3e81] = 356,\n-\t[BNXT_ULP_CLASS_HID_1dad] = 357,\n-\t[BNXT_ULP_CLASS_HID_4ca5] = 358,\n-\t[BNXT_ULP_CLASS_HID_25c9] = 359,\n-\t[BNXT_ULP_CLASS_HID_57c1] = 360,\n-\t[BNXT_ULP_CLASS_HID_33ed] = 361,\n-\t[BNXT_ULP_CLASS_HID_65e5] = 362,\n-\t[BNXT_ULP_CLASS_HID_6dd9] = 363,\n-\t[BNXT_ULP_CLASS_HID_261d] = 364,\n-\t[BNXT_ULP_CLASS_HID_0571] = 365,\n-\t[BNXT_ULP_CLASS_HID_34f9] = 366,\n-\t[BNXT_ULP_CLASS_HID_1d55] = 367,\n-\t[BNXT_ULP_CLASS_HID_4fdd] = 368,\n-\t[BNXT_ULP_CLASS_HID_2d31] = 369,\n-\t[BNXT_ULP_CLASS_HID_5db9] = 370,\n-\t[BNXT_ULP_CLASS_HID_0035] = 371,\n-\t[BNXT_ULP_CLASS_HID_323d] = 372,\n-\t[BNXT_ULP_CLASS_HID_1111] = 373,\n-\t[BNXT_ULP_CLASS_HID_4019] = 374,\n-\t[BNXT_ULP_CLASS_HID_2975] = 375,\n-\t[BNXT_ULP_CLASS_HID_5b7d] = 376,\n-\t[BNXT_ULP_CLASS_HID_3f51] = 377,\n-\t[BNXT_ULP_CLASS_HID_6959] = 378,\n-\t[BNXT_ULP_CLASS_HID_0e85] = 379,\n-\t[BNXT_ULP_CLASS_HID_380d] = 380,\n-\t[BNXT_ULP_CLASS_HID_1f21] = 381,\n-\t[BNXT_ULP_CLASS_HID_4ea9] = 382,\n-\t[BNXT_ULP_CLASS_HID_1705] = 383,\n-\t[BNXT_ULP_CLASS_HID_418d] = 384,\n-\t[BNXT_ULP_CLASS_HID_2721] = 385,\n-\t[BNXT_ULP_CLASS_HID_57a9] = 386,\n-\t[BNXT_ULP_CLASS_HID_1a25] = 387,\n-\t[BNXT_ULP_CLASS_HID_342d] = 388,\n-\t[BNXT_ULP_CLASS_HID_2b01] = 389,\n-\t[BNXT_ULP_CLASS_HID_5a09] = 390,\n-\t[BNXT_ULP_CLASS_HID_2325] = 391,\n-\t[BNXT_ULP_CLASS_HID_5d2d] = 392,\n-\t[BNXT_ULP_CLASS_HID_3101] = 393,\n-\t[BNXT_ULP_CLASS_HID_6309] = 394,\n-\t[BNXT_ULP_CLASS_HID_0bad] = 395,\n-\t[BNXT_ULP_CLASS_HID_2535] = 396,\n-\t[BNXT_ULP_CLASS_HID_1869] = 397,\n-\t[BNXT_ULP_CLASS_HID_4bf1] = 398,\n-\t[BNXT_ULP_CLASS_HID_136d] = 399,\n-\t[BNXT_ULP_CLASS_HID_43f5] = 400,\n-\t[BNXT_ULP_CLASS_HID_2129] = 401,\n-\t[BNXT_ULP_CLASS_HID_53b1] = 402,\n-\t[BNXT_ULP_CLASS_HID_072d] = 403,\n-\t[BNXT_ULP_CLASS_HID_3135] = 404,\n-\t[BNXT_ULP_CLASS_HID_1429] = 405,\n-\t[BNXT_ULP_CLASS_HID_4731] = 406,\n-\t[BNXT_ULP_CLASS_HID_2f6d] = 407,\n-\t[BNXT_ULP_CLASS_HID_5f75] = 408,\n-\t[BNXT_ULP_CLASS_HID_3d69] = 409,\n-\t[BNXT_ULP_CLASS_HID_6f71] = 410,\n-\t[BNXT_ULP_CLASS_HID_0dbd] = 411,\n-\t[BNXT_ULP_CLASS_HID_3f25] = 412,\n-\t[BNXT_ULP_CLASS_HID_1239] = 413,\n-\t[BNXT_ULP_CLASS_HID_4da1] = 414,\n-\t[BNXT_ULP_CLASS_HID_153d] = 415,\n-\t[BNXT_ULP_CLASS_HID_45a5] = 416,\n-\t[BNXT_ULP_CLASS_HID_3bb9] = 417,\n-\t[BNXT_ULP_CLASS_HID_55a1] = 418,\n-\t[BNXT_ULP_CLASS_HID_193d] = 419,\n-\t[BNXT_ULP_CLASS_HID_4b25] = 420,\n-\t[BNXT_ULP_CLASS_HID_2e39] = 421,\n-\t[BNXT_ULP_CLASS_HID_5921] = 422,\n-\t[BNXT_ULP_CLASS_HID_213d] = 423,\n-\t[BNXT_ULP_CLASS_HID_5125] = 424,\n-\t[BNXT_ULP_CLASS_HID_3739] = 425,\n-\t[BNXT_ULP_CLASS_HID_093d] = 426,\n-\t[BNXT_ULP_CLASS_HID_684d] = 427,\n-\t[BNXT_ULP_CLASS_HID_2389] = 428,\n-\t[BNXT_ULP_CLASS_HID_00e5] = 429,\n-\t[BNXT_ULP_CLASS_HID_316d] = 430,\n-\t[BNXT_ULP_CLASS_HID_18c1] = 431,\n-\t[BNXT_ULP_CLASS_HID_4a49] = 432,\n-\t[BNXT_ULP_CLASS_HID_28a5] = 433,\n-\t[BNXT_ULP_CLASS_HID_582d] = 434,\n-\t[BNXT_ULP_CLASS_HID_05a1] = 435,\n-\t[BNXT_ULP_CLASS_HID_37a9] = 436,\n-\t[BNXT_ULP_CLASS_HID_1485] = 437,\n-\t[BNXT_ULP_CLASS_HID_458d] = 438,\n-\t[BNXT_ULP_CLASS_HID_2ce1] = 439,\n-\t[BNXT_ULP_CLASS_HID_5ee9] = 440,\n-\t[BNXT_ULP_CLASS_HID_3ac5] = 441,\n-\t[BNXT_ULP_CLASS_HID_6ccd] = 442,\n-\t[BNXT_ULP_CLASS_HID_0b11] = 443,\n-\t[BNXT_ULP_CLASS_HID_3d99] = 444,\n-\t[BNXT_ULP_CLASS_HID_1ab5] = 445,\n-\t[BNXT_ULP_CLASS_HID_4b3d] = 446,\n-\t[BNXT_ULP_CLASS_HID_1291] = 447,\n-\t[BNXT_ULP_CLASS_HID_4419] = 448,\n-\t[BNXT_ULP_CLASS_HID_22b5] = 449,\n-\t[BNXT_ULP_CLASS_HID_523d] = 450,\n-\t[BNXT_ULP_CLASS_HID_1fb1] = 451,\n-\t[BNXT_ULP_CLASS_HID_31b9] = 452,\n-\t[BNXT_ULP_CLASS_HID_2e95] = 453,\n-\t[BNXT_ULP_CLASS_HID_5f9d] = 454,\n-\t[BNXT_ULP_CLASS_HID_26b1] = 455,\n-\t[BNXT_ULP_CLASS_HID_58b9] = 456,\n-\t[BNXT_ULP_CLASS_HID_3495] = 457,\n-\t[BNXT_ULP_CLASS_HID_669d] = 458,\n-\t[BNXT_ULP_CLASS_HID_0e39] = 459,\n-\t[BNXT_ULP_CLASS_HID_20a1] = 460,\n-\t[BNXT_ULP_CLASS_HID_1dfd] = 461,\n-\t[BNXT_ULP_CLASS_HID_4e65] = 462,\n-\t[BNXT_ULP_CLASS_HID_16f9] = 463,\n-\t[BNXT_ULP_CLASS_HID_4661] = 464,\n-\t[BNXT_ULP_CLASS_HID_24bd] = 465,\n-\t[BNXT_ULP_CLASS_HID_5625] = 466,\n-\t[BNXT_ULP_CLASS_HID_02b9] = 467,\n-\t[BNXT_ULP_CLASS_HID_34a1] = 468,\n-\t[BNXT_ULP_CLASS_HID_11bd] = 469,\n-\t[BNXT_ULP_CLASS_HID_42a5] = 470,\n-\t[BNXT_ULP_CLASS_HID_2af9] = 471,\n-\t[BNXT_ULP_CLASS_HID_5ae1] = 472,\n-\t[BNXT_ULP_CLASS_HID_38fd] = 473,\n-\t[BNXT_ULP_CLASS_HID_6ae5] = 474,\n-\t[BNXT_ULP_CLASS_HID_0829] = 475,\n-\t[BNXT_ULP_CLASS_HID_3ab1] = 476,\n-\t[BNXT_ULP_CLASS_HID_17ad] = 477,\n-\t[BNXT_ULP_CLASS_HID_4835] = 478,\n-\t[BNXT_ULP_CLASS_HID_10a9] = 479,\n-\t[BNXT_ULP_CLASS_HID_4031] = 480,\n-\t[BNXT_ULP_CLASS_HID_3e2d] = 481,\n-\t[BNXT_ULP_CLASS_HID_5035] = 482,\n-\t[BNXT_ULP_CLASS_HID_1ca9] = 483,\n-\t[BNXT_ULP_CLASS_HID_4eb1] = 484,\n-\t[BNXT_ULP_CLASS_HID_2bad] = 485,\n-\t[BNXT_ULP_CLASS_HID_5cb5] = 486,\n-\t[BNXT_ULP_CLASS_HID_24a9] = 487,\n-\t[BNXT_ULP_CLASS_HID_54b1] = 488,\n-\t[BNXT_ULP_CLASS_HID_32ad] = 489,\n-\t[BNXT_ULP_CLASS_HID_0ca9] = 490,\n-\t[BNXT_ULP_CLASS_HID_7f35] = 491,\n-\t[BNXT_ULP_CLASS_HID_34f1] = 492,\n-\t[BNXT_ULP_CLASS_HID_179d] = 493,\n-\t[BNXT_ULP_CLASS_HID_2615] = 494,\n-\t[BNXT_ULP_CLASS_HID_0fb9] = 495,\n-\t[BNXT_ULP_CLASS_HID_5d31] = 496,\n-\t[BNXT_ULP_CLASS_HID_3fdd] = 497,\n-\t[BNXT_ULP_CLASS_HID_4f55] = 498,\n-\t[BNXT_ULP_CLASS_HID_12d9] = 499,\n-\t[BNXT_ULP_CLASS_HID_20d1] = 500,\n-\t[BNXT_ULP_CLASS_HID_03fd] = 501,\n-\t[BNXT_ULP_CLASS_HID_52f5] = 502,\n-\t[BNXT_ULP_CLASS_HID_3b99] = 503,\n-\t[BNXT_ULP_CLASS_HID_4991] = 504,\n-\t[BNXT_ULP_CLASS_HID_2dbd] = 505,\n-\t[BNXT_ULP_CLASS_HID_7bb5] = 506,\n-\t[BNXT_ULP_CLASS_HID_34c6] = 507,\n-\t[BNXT_ULP_CLASS_HID_0c22] = 508,\n-\t[BNXT_ULP_CLASS_HID_1cbe] = 509,\n-\t[BNXT_ULP_CLASS_HID_179a] = 510,\n-\t[BNXT_ULP_CLASS_HID_59be] = 511,\n-\t[BNXT_ULP_CLASS_HID_515a] = 512,\n-\t[BNXT_ULP_CLASS_HID_1c72] = 513,\n-\t[BNXT_ULP_CLASS_HID_171e] = 514,\n-\t[BNXT_ULP_CLASS_HID_19c8] = 515,\n-\t[BNXT_ULP_CLASS_HID_112c] = 516,\n-\t[BNXT_ULP_CLASS_HID_4d68] = 517,\n-\t[BNXT_ULP_CLASS_HID_444c] = 518,\n-\t[BNXT_ULP_CLASS_HID_0e8c] = 519,\n-\t[BNXT_ULP_CLASS_HID_09e0] = 520,\n-\t[BNXT_ULP_CLASS_HID_1af0] = 521,\n-\t[BNXT_ULP_CLASS_HID_15d4] = 522,\n-\t[BNXT_ULP_CLASS_HID_1dd0] = 523,\n-\t[BNXT_ULP_CLASS_HID_14f4] = 524,\n-\t[BNXT_ULP_CLASS_HID_70b0] = 525,\n-\t[BNXT_ULP_CLASS_HID_4854] = 526,\n-\t[BNXT_ULP_CLASS_HID_3dd4] = 527,\n-\t[BNXT_ULP_CLASS_HID_34f8] = 528,\n-\t[BNXT_ULP_CLASS_HID_09e8] = 529,\n-\t[BNXT_ULP_CLASS_HID_008c] = 530,\n-\t[BNXT_ULP_CLASS_HID_34e6] = 531,\n-\t[BNXT_ULP_CLASS_HID_0c02] = 532,\n-\t[BNXT_ULP_CLASS_HID_1c9e] = 533,\n-\t[BNXT_ULP_CLASS_HID_17ba] = 534,\n-\t[BNXT_ULP_CLASS_HID_429e] = 535,\n-\t[BNXT_ULP_CLASS_HID_5dba] = 536,\n-\t[BNXT_ULP_CLASS_HID_2a16] = 537,\n-\t[BNXT_ULP_CLASS_HID_2532] = 538,\n-\t[BNXT_ULP_CLASS_HID_2da2] = 539,\n-\t[BNXT_ULP_CLASS_HID_24fe] = 540,\n-\t[BNXT_ULP_CLASS_HID_355a] = 541,\n-\t[BNXT_ULP_CLASS_HID_0c76] = 542,\n-\t[BNXT_ULP_CLASS_HID_13e6] = 543,\n-\t[BNXT_ULP_CLASS_HID_7276] = 544,\n-\t[BNXT_ULP_CLASS_HID_42d2] = 545,\n-\t[BNXT_ULP_CLASS_HID_5dee] = 546,\n-\t[BNXT_ULP_CLASS_HID_59de] = 547,\n-\t[BNXT_ULP_CLASS_HID_513a] = 548,\n-\t[BNXT_ULP_CLASS_HID_1c12] = 549,\n-\t[BNXT_ULP_CLASS_HID_177e] = 550,\n-\t[BNXT_ULP_CLASS_HID_0e92] = 551,\n-\t[BNXT_ULP_CLASS_HID_09fe] = 552,\n-\t[BNXT_ULP_CLASS_HID_5c1a] = 553,\n-\t[BNXT_ULP_CLASS_HID_5746] = 554,\n-\t[BNXT_ULP_CLASS_HID_79da] = 555,\n-\t[BNXT_ULP_CLASS_HID_7106] = 556,\n-\t[BNXT_ULP_CLASS_HID_3c1e] = 557,\n-\t[BNXT_ULP_CLASS_HID_377a] = 558,\n-\t[BNXT_ULP_CLASS_HID_2e9e] = 559,\n-\t[BNXT_ULP_CLASS_HID_29fa] = 560,\n-\t[BNXT_ULP_CLASS_HID_14d2] = 561,\n-\t[BNXT_ULP_CLASS_HID_7742] = 562,\n-\t[BNXT_ULP_CLASS_HID_3706] = 563,\n-\t[BNXT_ULP_CLASS_HID_0fe2] = 564,\n-\t[BNXT_ULP_CLASS_HID_1f7e] = 565,\n-\t[BNXT_ULP_CLASS_HID_145a] = 566,\n-\t[BNXT_ULP_CLASS_HID_417e] = 567,\n-\t[BNXT_ULP_CLASS_HID_5e5a] = 568,\n-\t[BNXT_ULP_CLASS_HID_29f6] = 569,\n-\t[BNXT_ULP_CLASS_HID_26d2] = 570,\n-\t[BNXT_ULP_CLASS_HID_2e42] = 571,\n-\t[BNXT_ULP_CLASS_HID_271e] = 572,\n-\t[BNXT_ULP_CLASS_HID_36ba] = 573,\n-\t[BNXT_ULP_CLASS_HID_0f96] = 574,\n-\t[BNXT_ULP_CLASS_HID_1006] = 575,\n-\t[BNXT_ULP_CLASS_HID_7196] = 576,\n-\t[BNXT_ULP_CLASS_HID_4132] = 577,\n-\t[BNXT_ULP_CLASS_HID_5e0e] = 578,\n-\t[BNXT_ULP_CLASS_HID_59fe] = 579,\n-\t[BNXT_ULP_CLASS_HID_511a] = 580,\n-\t[BNXT_ULP_CLASS_HID_1c32] = 581,\n-\t[BNXT_ULP_CLASS_HID_175e] = 582,\n-\t[BNXT_ULP_CLASS_HID_0eb2] = 583,\n-\t[BNXT_ULP_CLASS_HID_09de] = 584,\n-\t[BNXT_ULP_CLASS_HID_5c3a] = 585,\n-\t[BNXT_ULP_CLASS_HID_5766] = 586,\n-\t[BNXT_ULP_CLASS_HID_79fa] = 587,\n-\t[BNXT_ULP_CLASS_HID_7126] = 588,\n-\t[BNXT_ULP_CLASS_HID_3c3e] = 589,\n-\t[BNXT_ULP_CLASS_HID_375a] = 590,\n-\t[BNXT_ULP_CLASS_HID_2ebe] = 591,\n-\t[BNXT_ULP_CLASS_HID_29da] = 592,\n-\t[BNXT_ULP_CLASS_HID_14f2] = 593,\n-\t[BNXT_ULP_CLASS_HID_7762] = 594,\n-\t[BNXT_ULP_CLASS_HID_19e8] = 595,\n-\t[BNXT_ULP_CLASS_HID_110c] = 596,\n-\t[BNXT_ULP_CLASS_HID_4d48] = 597,\n-\t[BNXT_ULP_CLASS_HID_446c] = 598,\n-\t[BNXT_ULP_CLASS_HID_0eac] = 599,\n-\t[BNXT_ULP_CLASS_HID_09c0] = 600,\n-\t[BNXT_ULP_CLASS_HID_1ad0] = 601,\n-\t[BNXT_ULP_CLASS_HID_15f4] = 602,\n-\t[BNXT_ULP_CLASS_HID_39ec] = 603,\n-\t[BNXT_ULP_CLASS_HID_3100] = 604,\n-\t[BNXT_ULP_CLASS_HID_0210] = 605,\n-\t[BNXT_ULP_CLASS_HID_1d34] = 606,\n-\t[BNXT_ULP_CLASS_HID_2ea0] = 607,\n-\t[BNXT_ULP_CLASS_HID_29c4] = 608,\n-\t[BNXT_ULP_CLASS_HID_3ad4] = 609,\n-\t[BNXT_ULP_CLASS_HID_35e8] = 610,\n-\t[BNXT_ULP_CLASS_HID_5d80] = 611,\n-\t[BNXT_ULP_CLASS_HID_54a4] = 612,\n-\t[BNXT_ULP_CLASS_HID_29b4] = 613,\n-\t[BNXT_ULP_CLASS_HID_20c8] = 614,\n-\t[BNXT_ULP_CLASS_HID_7244] = 615,\n-\t[BNXT_ULP_CLASS_HID_4d98] = 616,\n-\t[BNXT_ULP_CLASS_HID_5e68] = 617,\n-\t[BNXT_ULP_CLASS_HID_598c] = 618,\n-\t[BNXT_ULP_CLASS_HID_1248] = 619,\n-\t[BNXT_ULP_CLASS_HID_74d8] = 620,\n-\t[BNXT_ULP_CLASS_HID_49a8] = 621,\n-\t[BNXT_ULP_CLASS_HID_40cc] = 622,\n-\t[BNXT_ULP_CLASS_HID_0b0c] = 623,\n-\t[BNXT_ULP_CLASS_HID_0220] = 624,\n-\t[BNXT_ULP_CLASS_HID_1730] = 625,\n-\t[BNXT_ULP_CLASS_HID_7980] = 626,\n-\t[BNXT_ULP_CLASS_HID_1db0] = 627,\n-\t[BNXT_ULP_CLASS_HID_1494] = 628,\n-\t[BNXT_ULP_CLASS_HID_70d0] = 629,\n-\t[BNXT_ULP_CLASS_HID_4834] = 630,\n-\t[BNXT_ULP_CLASS_HID_3db4] = 631,\n-\t[BNXT_ULP_CLASS_HID_3498] = 632,\n-\t[BNXT_ULP_CLASS_HID_0988] = 633,\n-\t[BNXT_ULP_CLASS_HID_00ec] = 634,\n-\t[BNXT_ULP_CLASS_HID_3f44] = 635,\n-\t[BNXT_ULP_CLASS_HID_36a8] = 636,\n-\t[BNXT_ULP_CLASS_HID_0b58] = 637,\n-\t[BNXT_ULP_CLASS_HID_02bc] = 638,\n-\t[BNXT_ULP_CLASS_HID_5f48] = 639,\n-\t[BNXT_ULP_CLASS_HID_56ac] = 640,\n-\t[BNXT_ULP_CLASS_HID_2b5c] = 641,\n-\t[BNXT_ULP_CLASS_HID_2280] = 642,\n-\t[BNXT_ULP_CLASS_HID_4000] = 643,\n-\t[BNXT_ULP_CLASS_HID_5b64] = 644,\n-\t[BNXT_ULP_CLASS_HID_2c14] = 645,\n-\t[BNXT_ULP_CLASS_HID_2778] = 646,\n-\t[BNXT_ULP_CLASS_HID_18f8] = 647,\n-\t[BNXT_ULP_CLASS_HID_13dc] = 648,\n-\t[BNXT_ULP_CLASS_HID_4c18] = 649,\n-\t[BNXT_ULP_CLASS_HID_477c] = 650,\n-\t[BNXT_ULP_CLASS_HID_1a88] = 651,\n-\t[BNXT_ULP_CLASS_HID_15ec] = 652,\n-\t[BNXT_ULP_CLASS_HID_4e28] = 653,\n-\t[BNXT_ULP_CLASS_HID_490c] = 654,\n-\t[BNXT_ULP_CLASS_HID_3a8c] = 655,\n-\t[BNXT_ULP_CLASS_HID_35f0] = 656,\n-\t[BNXT_ULP_CLASS_HID_06e0] = 657,\n-\t[BNXT_ULP_CLASS_HID_01c4] = 658,\n-\t[BNXT_ULP_CLASS_HID_1a08] = 659,\n-\t[BNXT_ULP_CLASS_HID_12ec] = 660,\n-\t[BNXT_ULP_CLASS_HID_4ea8] = 661,\n-\t[BNXT_ULP_CLASS_HID_478c] = 662,\n-\t[BNXT_ULP_CLASS_HID_0d4c] = 663,\n-\t[BNXT_ULP_CLASS_HID_0a20] = 664,\n-\t[BNXT_ULP_CLASS_HID_1930] = 665,\n-\t[BNXT_ULP_CLASS_HID_1614] = 666,\n-\t[BNXT_ULP_CLASS_HID_3a0c] = 667,\n-\t[BNXT_ULP_CLASS_HID_32e0] = 668,\n-\t[BNXT_ULP_CLASS_HID_01f0] = 669,\n-\t[BNXT_ULP_CLASS_HID_1ed4] = 670,\n-\t[BNXT_ULP_CLASS_HID_2d40] = 671,\n-\t[BNXT_ULP_CLASS_HID_2a24] = 672,\n-\t[BNXT_ULP_CLASS_HID_3934] = 673,\n-\t[BNXT_ULP_CLASS_HID_3608] = 674,\n-\t[BNXT_ULP_CLASS_HID_5e60] = 675,\n-\t[BNXT_ULP_CLASS_HID_5744] = 676,\n-\t[BNXT_ULP_CLASS_HID_2a54] = 677,\n-\t[BNXT_ULP_CLASS_HID_2328] = 678,\n-\t[BNXT_ULP_CLASS_HID_71a4] = 679,\n-\t[BNXT_ULP_CLASS_HID_4e78] = 680,\n-\t[BNXT_ULP_CLASS_HID_5d88] = 681,\n-\t[BNXT_ULP_CLASS_HID_5a6c] = 682,\n-\t[BNXT_ULP_CLASS_HID_11a8] = 683,\n-\t[BNXT_ULP_CLASS_HID_7738] = 684,\n-\t[BNXT_ULP_CLASS_HID_4a48] = 685,\n-\t[BNXT_ULP_CLASS_HID_432c] = 686,\n-\t[BNXT_ULP_CLASS_HID_08ec] = 687,\n-\t[BNXT_ULP_CLASS_HID_01c0] = 688,\n-\t[BNXT_ULP_CLASS_HID_14d0] = 689,\n-\t[BNXT_ULP_CLASS_HID_7a60] = 690,\n-\t[BNXT_ULP_CLASS_HID_1d90] = 691,\n-\t[BNXT_ULP_CLASS_HID_14b4] = 692,\n-\t[BNXT_ULP_CLASS_HID_70f0] = 693,\n-\t[BNXT_ULP_CLASS_HID_4814] = 694,\n-\t[BNXT_ULP_CLASS_HID_3d94] = 695,\n-\t[BNXT_ULP_CLASS_HID_34b8] = 696,\n-\t[BNXT_ULP_CLASS_HID_09a8] = 697,\n-\t[BNXT_ULP_CLASS_HID_00cc] = 698,\n-\t[BNXT_ULP_CLASS_HID_3f64] = 699,\n-\t[BNXT_ULP_CLASS_HID_3688] = 700,\n-\t[BNXT_ULP_CLASS_HID_0b78] = 701,\n-\t[BNXT_ULP_CLASS_HID_029c] = 702,\n-\t[BNXT_ULP_CLASS_HID_5f68] = 703,\n-\t[BNXT_ULP_CLASS_HID_568c] = 704,\n-\t[BNXT_ULP_CLASS_HID_2b7c] = 705,\n-\t[BNXT_ULP_CLASS_HID_22a0] = 706,\n-\t[BNXT_ULP_CLASS_HID_4020] = 707,\n-\t[BNXT_ULP_CLASS_HID_5b44] = 708,\n-\t[BNXT_ULP_CLASS_HID_2c34] = 709,\n-\t[BNXT_ULP_CLASS_HID_2758] = 710,\n-\t[BNXT_ULP_CLASS_HID_18d8] = 711,\n-\t[BNXT_ULP_CLASS_HID_13fc] = 712,\n-\t[BNXT_ULP_CLASS_HID_4c38] = 713,\n-\t[BNXT_ULP_CLASS_HID_475c] = 714,\n-\t[BNXT_ULP_CLASS_HID_1aa8] = 715,\n-\t[BNXT_ULP_CLASS_HID_15cc] = 716,\n-\t[BNXT_ULP_CLASS_HID_4e08] = 717,\n-\t[BNXT_ULP_CLASS_HID_492c] = 718,\n-\t[BNXT_ULP_CLASS_HID_3aac] = 719,\n-\t[BNXT_ULP_CLASS_HID_35d0] = 720,\n-\t[BNXT_ULP_CLASS_HID_06c0] = 721,\n-\t[BNXT_ULP_CLASS_HID_01e4] = 722,\n-\t[BNXT_ULP_CLASS_HID_4d32] = 723,\n-\t[BNXT_ULP_CLASS_HID_54aa] = 724,\n-\t[BNXT_ULP_CLASS_HID_0686] = 725,\n-\t[BNXT_ULP_CLASS_HID_540e] = 726,\n-\t[BNXT_ULP_CLASS_HID_2e3c] = 727,\n-\t[BNXT_ULP_CLASS_HID_3a20] = 728,\n-\t[BNXT_ULP_CLASS_HID_46f0] = 729,\n-\t[BNXT_ULP_CLASS_HID_52e4] = 730,\n-\t[BNXT_ULP_CLASS_HID_55e4] = 731,\n-\t[BNXT_ULP_CLASS_HID_21f8] = 732,\n-\t[BNXT_ULP_CLASS_HID_75e8] = 733,\n-\t[BNXT_ULP_CLASS_HID_41fc] = 734,\n-\t[BNXT_ULP_CLASS_HID_4d12] = 735,\n-\t[BNXT_ULP_CLASS_HID_548a] = 736,\n-\t[BNXT_ULP_CLASS_HID_3356] = 737,\n-\t[BNXT_ULP_CLASS_HID_1ace] = 738,\n-\t[BNXT_ULP_CLASS_HID_1a9a] = 739,\n-\t[BNXT_ULP_CLASS_HID_4d46] = 740,\n-\t[BNXT_ULP_CLASS_HID_2812] = 741,\n-\t[BNXT_ULP_CLASS_HID_338a] = 742,\n-\t[BNXT_ULP_CLASS_HID_06e6] = 743,\n-\t[BNXT_ULP_CLASS_HID_546e] = 744,\n-\t[BNXT_ULP_CLASS_HID_46ee] = 745,\n-\t[BNXT_ULP_CLASS_HID_0d22] = 746,\n-\t[BNXT_ULP_CLASS_HID_26e2] = 747,\n-\t[BNXT_ULP_CLASS_HID_746a] = 748,\n-\t[BNXT_ULP_CLASS_HID_1fa6] = 749,\n-\t[BNXT_ULP_CLASS_HID_2d2e] = 750,\n-\t[BNXT_ULP_CLASS_HID_4ef2] = 751,\n-\t[BNXT_ULP_CLASS_HID_576a] = 752,\n-\t[BNXT_ULP_CLASS_HID_30b6] = 753,\n-\t[BNXT_ULP_CLASS_HID_192e] = 754,\n-\t[BNXT_ULP_CLASS_HID_197a] = 755,\n-\t[BNXT_ULP_CLASS_HID_4ea6] = 756,\n-\t[BNXT_ULP_CLASS_HID_2bf2] = 757,\n-\t[BNXT_ULP_CLASS_HID_306a] = 758,\n-\t[BNXT_ULP_CLASS_HID_06c6] = 759,\n-\t[BNXT_ULP_CLASS_HID_544e] = 760,\n-\t[BNXT_ULP_CLASS_HID_46ce] = 761,\n-\t[BNXT_ULP_CLASS_HID_0d02] = 762,\n-\t[BNXT_ULP_CLASS_HID_26c2] = 763,\n-\t[BNXT_ULP_CLASS_HID_744a] = 764,\n-\t[BNXT_ULP_CLASS_HID_1f86] = 765,\n-\t[BNXT_ULP_CLASS_HID_2d0e] = 766,\n-\t[BNXT_ULP_CLASS_HID_2e1c] = 767,\n-\t[BNXT_ULP_CLASS_HID_3a00] = 768,\n-\t[BNXT_ULP_CLASS_HID_46d0] = 769,\n-\t[BNXT_ULP_CLASS_HID_52c4] = 770,\n-\t[BNXT_ULP_CLASS_HID_4e10] = 771,\n-\t[BNXT_ULP_CLASS_HID_5a04] = 772,\n-\t[BNXT_ULP_CLASS_HID_1f98] = 773,\n-\t[BNXT_ULP_CLASS_HID_72f8] = 774,\n-\t[BNXT_ULP_CLASS_HID_0a78] = 775,\n-\t[BNXT_ULP_CLASS_HID_166c] = 776,\n-\t[BNXT_ULP_CLASS_HID_233c] = 777,\n-\t[BNXT_ULP_CLASS_HID_0f20] = 778,\n-\t[BNXT_ULP_CLASS_HID_2a7c] = 779,\n-\t[BNXT_ULP_CLASS_HID_3660] = 780,\n-\t[BNXT_ULP_CLASS_HID_4330] = 781,\n-\t[BNXT_ULP_CLASS_HID_2f24] = 782,\n-\t[BNXT_ULP_CLASS_HID_5584] = 783,\n-\t[BNXT_ULP_CLASS_HID_2198] = 784,\n-\t[BNXT_ULP_CLASS_HID_7588] = 785,\n-\t[BNXT_ULP_CLASS_HID_419c] = 786,\n-\t[BNXT_ULP_CLASS_HID_7758] = 787,\n-\t[BNXT_ULP_CLASS_HID_43ac] = 788,\n-\t[BNXT_ULP_CLASS_HID_0c10] = 789,\n-\t[BNXT_ULP_CLASS_HID_1864] = 790,\n-\t[BNXT_ULP_CLASS_HID_30c8] = 791,\n-\t[BNXT_ULP_CLASS_HID_1cdc] = 792,\n-\t[BNXT_ULP_CLASS_HID_50cc] = 793,\n-\t[BNXT_ULP_CLASS_HID_3d20] = 794,\n-\t[BNXT_ULP_CLASS_HID_529c] = 795,\n-\t[BNXT_ULP_CLASS_HID_3ef0] = 796,\n-\t[BNXT_ULP_CLASS_HID_72e0] = 797,\n-\t[BNXT_ULP_CLASS_HID_5ef4] = 798,\n-\t[BNXT_ULP_CLASS_HID_2dfc] = 799,\n-\t[BNXT_ULP_CLASS_HID_39e0] = 800,\n-\t[BNXT_ULP_CLASS_HID_4530] = 801,\n-\t[BNXT_ULP_CLASS_HID_5124] = 802,\n-\t[BNXT_ULP_CLASS_HID_4df0] = 803,\n-\t[BNXT_ULP_CLASS_HID_59e4] = 804,\n-\t[BNXT_ULP_CLASS_HID_1c78] = 805,\n-\t[BNXT_ULP_CLASS_HID_7118] = 806,\n-\t[BNXT_ULP_CLASS_HID_0998] = 807,\n-\t[BNXT_ULP_CLASS_HID_158c] = 808,\n-\t[BNXT_ULP_CLASS_HID_20dc] = 809,\n-\t[BNXT_ULP_CLASS_HID_0cc0] = 810,\n-\t[BNXT_ULP_CLASS_HID_299c] = 811,\n-\t[BNXT_ULP_CLASS_HID_3580] = 812,\n-\t[BNXT_ULP_CLASS_HID_40d0] = 813,\n-\t[BNXT_ULP_CLASS_HID_2cc4] = 814,\n-\t[BNXT_ULP_CLASS_HID_55a4] = 815,\n-\t[BNXT_ULP_CLASS_HID_21b8] = 816,\n-\t[BNXT_ULP_CLASS_HID_75a8] = 817,\n-\t[BNXT_ULP_CLASS_HID_41bc] = 818,\n-\t[BNXT_ULP_CLASS_HID_7778] = 819,\n-\t[BNXT_ULP_CLASS_HID_438c] = 820,\n-\t[BNXT_ULP_CLASS_HID_0c30] = 821,\n-\t[BNXT_ULP_CLASS_HID_1844] = 822,\n-\t[BNXT_ULP_CLASS_HID_30e8] = 823,\n-\t[BNXT_ULP_CLASS_HID_1cfc] = 824,\n-\t[BNXT_ULP_CLASS_HID_50ec] = 825,\n-\t[BNXT_ULP_CLASS_HID_3d00] = 826,\n-\t[BNXT_ULP_CLASS_HID_52bc] = 827,\n-\t[BNXT_ULP_CLASS_HID_3ed0] = 828,\n-\t[BNXT_ULP_CLASS_HID_72c0] = 829,\n-\t[BNXT_ULP_CLASS_HID_5ed4] = 830,\n-\t[BNXT_ULP_CLASS_HID_3866] = 831,\n-\t[BNXT_ULP_CLASS_HID_381e] = 832,\n-\t[BNXT_ULP_CLASS_HID_3860] = 833,\n-\t[BNXT_ULP_CLASS_HID_0454] = 834,\n-\t[BNXT_ULP_CLASS_HID_3818] = 835,\n-\t[BNXT_ULP_CLASS_HID_042c] = 836,\n-\t[BNXT_ULP_CLASS_HID_3846] = 837,\n-\t[BNXT_ULP_CLASS_HID_387e] = 838,\n-\t[BNXT_ULP_CLASS_HID_3ba6] = 839,\n-\t[BNXT_ULP_CLASS_HID_385e] = 840,\n-\t[BNXT_ULP_CLASS_HID_3840] = 841,\n-\t[BNXT_ULP_CLASS_HID_0474] = 842,\n-\t[BNXT_ULP_CLASS_HID_3878] = 843,\n-\t[BNXT_ULP_CLASS_HID_044c] = 844,\n-\t[BNXT_ULP_CLASS_HID_3ba0] = 845,\n-\t[BNXT_ULP_CLASS_HID_0794] = 846,\n-\t[BNXT_ULP_CLASS_HID_3858] = 847,\n-\t[BNXT_ULP_CLASS_HID_046c] = 848\n+\t[BNXT_ULP_CLASS_HID_e082] = 347,\n+\t[BNXT_ULP_CLASS_HID_ab46] = 348,\n+\t[BNXT_ULP_CLASS_HID_c82a] = 349,\n+\t[BNXT_ULP_CLASS_HID_f9a2] = 350,\n+\t[BNXT_ULP_CLASS_HID_d8ce] = 351,\n+\t[BNXT_ULP_CLASS_HID_a2d2] = 352,\n+\t[BNXT_ULP_CLASS_HID_c076] = 353,\n+\t[BNXT_ULP_CLASS_HID_f1ee] = 354,\n+\t[BNXT_ULP_CLASS_HID_a96e] = 355,\n+\t[BNXT_ULP_CLASS_HID_dae6] = 356,\n+\t[BNXT_ULP_CLASS_HID_c7aa] = 357,\n+\t[BNXT_ULP_CLASS_HID_c26e] = 358,\n+\t[BNXT_ULP_CLASS_HID_a0fa] = 359,\n+\t[BNXT_ULP_CLASS_HID_d272] = 360,\n+\t[BNXT_ULP_CLASS_HID_fff6] = 361,\n+\t[BNXT_ULP_CLASS_HID_e16e] = 362,\n+\t[BNXT_ULP_CLASS_HID_e165] = 363,\n+\t[BNXT_ULP_CLASS_HID_aaa1] = 364,\n+\t[BNXT_ULP_CLASS_HID_c9cd] = 365,\n+\t[BNXT_ULP_CLASS_HID_f845] = 366,\n+\t[BNXT_ULP_CLASS_HID_90f9] = 367,\n+\t[BNXT_ULP_CLASS_HID_c371] = 368,\n+\t[BNXT_ULP_CLASS_HID_e19d] = 369,\n+\t[BNXT_ULP_CLASS_HID_d015] = 370,\n+\t[BNXT_ULP_CLASS_HID_8c09] = 371,\n+\t[BNXT_ULP_CLASS_HID_be89] = 372,\n+\t[BNXT_ULP_CLASS_HID_ddad] = 373,\n+\t[BNXT_ULP_CLASS_HID_cc2d] = 374,\n+\t[BNXT_ULP_CLASS_HID_a4d9] = 375,\n+\t[BNXT_ULP_CLASS_HID_d759] = 376,\n+\t[BNXT_ULP_CLASS_HID_f27d] = 377,\n+\t[BNXT_ULP_CLASS_HID_e4fd] = 378,\n+\t[BNXT_ULP_CLASS_HID_ecf6] = 379,\n+\t[BNXT_ULP_CLASS_HID_a732] = 380,\n+\t[BNXT_ULP_CLASS_HID_c45e] = 381,\n+\t[BNXT_ULP_CLASS_HID_f5d6] = 382,\n+\t[BNXT_ULP_CLASS_HID_d4ba] = 383,\n+\t[BNXT_ULP_CLASS_HID_aea6] = 384,\n+\t[BNXT_ULP_CLASS_HID_cc02] = 385,\n+\t[BNXT_ULP_CLASS_HID_fd9a] = 386,\n+\t[BNXT_ULP_CLASS_HID_a51a] = 387,\n+\t[BNXT_ULP_CLASS_HID_d692] = 388,\n+\t[BNXT_ULP_CLASS_HID_cbde] = 389,\n+\t[BNXT_ULP_CLASS_HID_ce1a] = 390,\n+\t[BNXT_ULP_CLASS_HID_ac8e] = 391,\n+\t[BNXT_ULP_CLASS_HID_de06] = 392,\n+\t[BNXT_ULP_CLASS_HID_f382] = 393,\n+\t[BNXT_ULP_CLASS_HID_ed1a] = 394,\n+\t[BNXT_ULP_CLASS_HID_9d6a] = 395,\n+\t[BNXT_ULP_CLASS_HID_cee2] = 396,\n+\t[BNXT_ULP_CLASS_HID_ec0e] = 397,\n+\t[BNXT_ULP_CLASS_HID_dd86] = 398,\n+\t[BNXT_ULP_CLASS_HID_852e] = 399,\n+\t[BNXT_ULP_CLASS_HID_b6a6] = 400,\n+\t[BNXT_ULP_CLASS_HID_eb82] = 401,\n+\t[BNXT_ULP_CLASS_HID_c50a] = 402,\n+\t[BNXT_ULP_CLASS_HID_ccca] = 403,\n+\t[BNXT_ULP_CLASS_HID_8706] = 404,\n+\t[BNXT_ULP_CLASS_HID_d38e] = 405,\n+\t[BNXT_ULP_CLASS_HID_d5ca] = 406,\n+\t[BNXT_ULP_CLASS_HID_b48e] = 407,\n+\t[BNXT_ULP_CLASS_HID_8e8a] = 408,\n+\t[BNXT_ULP_CLASS_HID_db02] = 409,\n+\t[BNXT_ULP_CLASS_HID_dd8e] = 410,\n+\t[BNXT_ULP_CLASS_HID_819a] = 411,\n+\t[BNXT_ULP_CLASS_HID_b31a] = 412,\n+\t[BNXT_ULP_CLASS_HID_d03e] = 413,\n+\t[BNXT_ULP_CLASS_HID_c1be] = 414,\n+\t[BNXT_ULP_CLASS_HID_890e] = 415,\n+\t[BNXT_ULP_CLASS_HID_ba8e] = 416,\n+\t[BNXT_ULP_CLASS_HID_dfaa] = 417,\n+\t[BNXT_ULP_CLASS_HID_c93a] = 418,\n+\t[BNXT_ULP_CLASS_HID_b11a] = 419,\n+\t[BNXT_ULP_CLASS_HID_8b4e] = 420,\n+\t[BNXT_ULP_CLASS_HID_c79e] = 421,\n+\t[BNXT_ULP_CLASS_HID_d9da] = 422,\n+\t[BNXT_ULP_CLASS_HID_b88e] = 423,\n+\t[BNXT_ULP_CLASS_HID_ea0e] = 424,\n+\t[BNXT_ULP_CLASS_HID_cf0a] = 425,\n+\t[BNXT_ULP_CLASS_HID_c18e] = 426,\n+\t[BNXT_ULP_CLASS_HID_a94a] = 427,\n+\t[BNXT_ULP_CLASS_HID_daca] = 428,\n+\t[BNXT_ULP_CLASS_HID_ffee] = 429,\n+\t[BNXT_ULP_CLASS_HID_e96e] = 430,\n+\t[BNXT_ULP_CLASS_HID_910e] = 431,\n+\t[BNXT_ULP_CLASS_HID_c28e] = 432,\n+\t[BNXT_ULP_CLASS_HID_e7aa] = 433,\n+\t[BNXT_ULP_CLASS_HID_d12a] = 434,\n+\t[BNXT_ULP_CLASS_HID_d8ca] = 435,\n+\t[BNXT_ULP_CLASS_HID_930e] = 436,\n+\t[BNXT_ULP_CLASS_HID_ef4e] = 437,\n+\t[BNXT_ULP_CLASS_HID_e18a] = 438,\n+\t[BNXT_ULP_CLASS_HID_c08e] = 439,\n+\t[BNXT_ULP_CLASS_HID_9a8a] = 440,\n+\t[BNXT_ULP_CLASS_HID_d70a] = 441,\n+\t[BNXT_ULP_CLASS_HID_e90e] = 442,\n+\t[BNXT_ULP_CLASS_HID_edd9] = 443,\n+\t[BNXT_ULP_CLASS_HID_a61d] = 444,\n+\t[BNXT_ULP_CLASS_HID_c571] = 445,\n+\t[BNXT_ULP_CLASS_HID_f4f9] = 446,\n+\t[BNXT_ULP_CLASS_HID_9c45] = 447,\n+\t[BNXT_ULP_CLASS_HID_cfcd] = 448,\n+\t[BNXT_ULP_CLASS_HID_ed21] = 449,\n+\t[BNXT_ULP_CLASS_HID_dca9] = 450,\n+\t[BNXT_ULP_CLASS_HID_80b5] = 451,\n+\t[BNXT_ULP_CLASS_HID_b235] = 452,\n+\t[BNXT_ULP_CLASS_HID_d111] = 453,\n+\t[BNXT_ULP_CLASS_HID_c091] = 454,\n+\t[BNXT_ULP_CLASS_HID_a865] = 455,\n+\t[BNXT_ULP_CLASS_HID_dbe5] = 456,\n+\t[BNXT_ULP_CLASS_HID_fec1] = 457,\n+\t[BNXT_ULP_CLASS_HID_e841] = 458,\n+\t[BNXT_ULP_CLASS_HID_8e85] = 459,\n+\t[BNXT_ULP_CLASS_HID_b80d] = 460,\n+\t[BNXT_ULP_CLASS_HID_df65] = 461,\n+\t[BNXT_ULP_CLASS_HID_ceed] = 462,\n+\t[BNXT_ULP_CLASS_HID_9645] = 463,\n+\t[BNXT_ULP_CLASS_HID_c1cd] = 464,\n+\t[BNXT_ULP_CLASS_HID_e725] = 465,\n+\t[BNXT_ULP_CLASS_HID_d6ad] = 466,\n+\t[BNXT_ULP_CLASS_HID_9aa5] = 467,\n+\t[BNXT_ULP_CLASS_HID_b425] = 468,\n+\t[BNXT_ULP_CLASS_HID_eb05] = 469,\n+\t[BNXT_ULP_CLASS_HID_da85] = 470,\n+\t[BNXT_ULP_CLASS_HID_a265] = 471,\n+\t[BNXT_ULP_CLASS_HID_dde5] = 472,\n+\t[BNXT_ULP_CLASS_HID_f0c5] = 473,\n+\t[BNXT_ULP_CLASS_HID_e245] = 474,\n+\t[BNXT_ULP_CLASS_HID_8b8f] = 475,\n+\t[BNXT_ULP_CLASS_HID_a517] = 476,\n+\t[BNXT_ULP_CLASS_HID_d86b] = 477,\n+\t[BNXT_ULP_CLASS_HID_cbf3] = 478,\n+\t[BNXT_ULP_CLASS_HID_934f] = 479,\n+\t[BNXT_ULP_CLASS_HID_c2c7] = 480,\n+\t[BNXT_ULP_CLASS_HID_e02b] = 481,\n+\t[BNXT_ULP_CLASS_HID_d3a3] = 482,\n+\t[BNXT_ULP_CLASS_HID_87a7] = 483,\n+\t[BNXT_ULP_CLASS_HID_b137] = 484,\n+\t[BNXT_ULP_CLASS_HID_d403] = 485,\n+\t[BNXT_ULP_CLASS_HID_c793] = 486,\n+\t[BNXT_ULP_CLASS_HID_af67] = 487,\n+\t[BNXT_ULP_CLASS_HID_dee7] = 488,\n+\t[BNXT_ULP_CLASS_HID_fdc3] = 489,\n+\t[BNXT_ULP_CLASS_HID_ef43] = 490,\n+\t[BNXT_ULP_CLASS_HID_8dbf] = 491,\n+\t[BNXT_ULP_CLASS_HID_bf07] = 492,\n+\t[BNXT_ULP_CLASS_HID_d21f] = 493,\n+\t[BNXT_ULP_CLASS_HID_cde7] = 494,\n+\t[BNXT_ULP_CLASS_HID_956f] = 495,\n+\t[BNXT_ULP_CLASS_HID_c4c7] = 496,\n+\t[BNXT_ULP_CLASS_HID_fbcf] = 497,\n+\t[BNXT_ULP_CLASS_HID_d5a7] = 498,\n+\t[BNXT_ULP_CLASS_HID_9957] = 499,\n+\t[BNXT_ULP_CLASS_HID_cb27] = 500,\n+\t[BNXT_ULP_CLASS_HID_ee37] = 501,\n+\t[BNXT_ULP_CLASS_HID_d987] = 502,\n+\t[BNXT_ULP_CLASS_HID_a107] = 503,\n+\t[BNXT_ULP_CLASS_HID_d0e7] = 504,\n+\t[BNXT_ULP_CLASS_HID_f7e7] = 505,\n+\t[BNXT_ULP_CLASS_HID_c827] = 506,\n+\t[BNXT_ULP_CLASS_HID_f76a] = 507,\n+\t[BNXT_ULP_CLASS_HID_bcae] = 508,\n+\t[BNXT_ULP_CLASS_HID_dfc2] = 509,\n+\t[BNXT_ULP_CLASS_HID_ee4a] = 510,\n+\t[BNXT_ULP_CLASS_HID_cf26] = 511,\n+\t[BNXT_ULP_CLASS_HID_b53a] = 512,\n+\t[BNXT_ULP_CLASS_HID_d79e] = 513,\n+\t[BNXT_ULP_CLASS_HID_e606] = 514,\n+\t[BNXT_ULP_CLASS_HID_be86] = 515,\n+\t[BNXT_ULP_CLASS_HID_cd0e] = 516,\n+\t[BNXT_ULP_CLASS_HID_d042] = 517,\n+\t[BNXT_ULP_CLASS_HID_d586] = 518,\n+\t[BNXT_ULP_CLASS_HID_b712] = 519,\n+\t[BNXT_ULP_CLASS_HID_c59a] = 520,\n+\t[BNXT_ULP_CLASS_HID_e81e] = 521,\n+\t[BNXT_ULP_CLASS_HID_f686] = 522,\n+\t[BNXT_ULP_CLASS_HID_86f6] = 523,\n+\t[BNXT_ULP_CLASS_HID_d57e] = 524,\n+\t[BNXT_ULP_CLASS_HID_f792] = 525,\n+\t[BNXT_ULP_CLASS_HID_c61a] = 526,\n+\t[BNXT_ULP_CLASS_HID_9eb2] = 527,\n+\t[BNXT_ULP_CLASS_HID_ad3a] = 528,\n+\t[BNXT_ULP_CLASS_HID_f01e] = 529,\n+\t[BNXT_ULP_CLASS_HID_de96] = 530,\n+\t[BNXT_ULP_CLASS_HID_d756] = 531,\n+\t[BNXT_ULP_CLASS_HID_9c9a] = 532,\n+\t[BNXT_ULP_CLASS_HID_c812] = 533,\n+\t[BNXT_ULP_CLASS_HID_ce56] = 534,\n+\t[BNXT_ULP_CLASS_HID_af12] = 535,\n+\t[BNXT_ULP_CLASS_HID_9516] = 536,\n+\t[BNXT_ULP_CLASS_HID_c09e] = 537,\n+\t[BNXT_ULP_CLASS_HID_c612] = 538,\n+\t[BNXT_ULP_CLASS_HID_9a06] = 539,\n+\t[BNXT_ULP_CLASS_HID_a886] = 540,\n+\t[BNXT_ULP_CLASS_HID_cba2] = 541,\n+\t[BNXT_ULP_CLASS_HID_da22] = 542,\n+\t[BNXT_ULP_CLASS_HID_9292] = 543,\n+\t[BNXT_ULP_CLASS_HID_a112] = 544,\n+\t[BNXT_ULP_CLASS_HID_c436] = 545,\n+\t[BNXT_ULP_CLASS_HID_d2a6] = 546,\n+\t[BNXT_ULP_CLASS_HID_aa86] = 547,\n+\t[BNXT_ULP_CLASS_HID_90d2] = 548,\n+\t[BNXT_ULP_CLASS_HID_dc02] = 549,\n+\t[BNXT_ULP_CLASS_HID_c246] = 550,\n+\t[BNXT_ULP_CLASS_HID_a312] = 551,\n+\t[BNXT_ULP_CLASS_HID_f192] = 552,\n+\t[BNXT_ULP_CLASS_HID_d496] = 553,\n+\t[BNXT_ULP_CLASS_HID_da12] = 554,\n+\t[BNXT_ULP_CLASS_HID_b2d6] = 555,\n+\t[BNXT_ULP_CLASS_HID_c156] = 556,\n+\t[BNXT_ULP_CLASS_HID_e472] = 557,\n+\t[BNXT_ULP_CLASS_HID_f2f2] = 558,\n+\t[BNXT_ULP_CLASS_HID_8a92] = 559,\n+\t[BNXT_ULP_CLASS_HID_d912] = 560,\n+\t[BNXT_ULP_CLASS_HID_fc36] = 561,\n+\t[BNXT_ULP_CLASS_HID_cab6] = 562,\n+\t[BNXT_ULP_CLASS_HID_c356] = 563,\n+\t[BNXT_ULP_CLASS_HID_8892] = 564,\n+\t[BNXT_ULP_CLASS_HID_f4d2] = 565,\n+\t[BNXT_ULP_CLASS_HID_fa16] = 566,\n+\t[BNXT_ULP_CLASS_HID_db12] = 567,\n+\t[BNXT_ULP_CLASS_HID_8116] = 568,\n+\t[BNXT_ULP_CLASS_HID_cc96] = 569,\n+\t[BNXT_ULP_CLASS_HID_f292] = 570,\n+\t[BNXT_ULP_CLASS_HID_e84d] = 571,\n+\t[BNXT_ULP_CLASS_HID_a389] = 572,\n+\t[BNXT_ULP_CLASS_HID_c0e5] = 573,\n+\t[BNXT_ULP_CLASS_HID_f16d] = 574,\n+\t[BNXT_ULP_CLASS_HID_99d1] = 575,\n+\t[BNXT_ULP_CLASS_HID_ca59] = 576,\n+\t[BNXT_ULP_CLASS_HID_e8b5] = 577,\n+\t[BNXT_ULP_CLASS_HID_d93d] = 578,\n+\t[BNXT_ULP_CLASS_HID_8521] = 579,\n+\t[BNXT_ULP_CLASS_HID_b7a1] = 580,\n+\t[BNXT_ULP_CLASS_HID_d485] = 581,\n+\t[BNXT_ULP_CLASS_HID_c505] = 582,\n+\t[BNXT_ULP_CLASS_HID_adf1] = 583,\n+\t[BNXT_ULP_CLASS_HID_de71] = 584,\n+\t[BNXT_ULP_CLASS_HID_fb55] = 585,\n+\t[BNXT_ULP_CLASS_HID_edd5] = 586,\n+\t[BNXT_ULP_CLASS_HID_8b11] = 587,\n+\t[BNXT_ULP_CLASS_HID_bd99] = 588,\n+\t[BNXT_ULP_CLASS_HID_daf1] = 589,\n+\t[BNXT_ULP_CLASS_HID_cb79] = 590,\n+\t[BNXT_ULP_CLASS_HID_93d1] = 591,\n+\t[BNXT_ULP_CLASS_HID_c459] = 592,\n+\t[BNXT_ULP_CLASS_HID_e2b1] = 593,\n+\t[BNXT_ULP_CLASS_HID_d339] = 594,\n+\t[BNXT_ULP_CLASS_HID_9f31] = 595,\n+\t[BNXT_ULP_CLASS_HID_b1b1] = 596,\n+\t[BNXT_ULP_CLASS_HID_ee91] = 597,\n+\t[BNXT_ULP_CLASS_HID_df11] = 598,\n+\t[BNXT_ULP_CLASS_HID_a7f1] = 599,\n+\t[BNXT_ULP_CLASS_HID_d871] = 600,\n+\t[BNXT_ULP_CLASS_HID_f551] = 601,\n+\t[BNXT_ULP_CLASS_HID_e7d1] = 602,\n+\t[BNXT_ULP_CLASS_HID_8e1b] = 603,\n+\t[BNXT_ULP_CLASS_HID_a083] = 604,\n+\t[BNXT_ULP_CLASS_HID_ddff] = 605,\n+\t[BNXT_ULP_CLASS_HID_ce67] = 606,\n+\t[BNXT_ULP_CLASS_HID_96db] = 607,\n+\t[BNXT_ULP_CLASS_HID_c753] = 608,\n+\t[BNXT_ULP_CLASS_HID_e5bf] = 609,\n+\t[BNXT_ULP_CLASS_HID_d637] = 610,\n+\t[BNXT_ULP_CLASS_HID_8233] = 611,\n+\t[BNXT_ULP_CLASS_HID_b4a3] = 612,\n+\t[BNXT_ULP_CLASS_HID_d197] = 613,\n+\t[BNXT_ULP_CLASS_HID_c207] = 614,\n+\t[BNXT_ULP_CLASS_HID_aaf3] = 615,\n+\t[BNXT_ULP_CLASS_HID_db73] = 616,\n+\t[BNXT_ULP_CLASS_HID_f857] = 617,\n+\t[BNXT_ULP_CLASS_HID_ead7] = 618,\n+\t[BNXT_ULP_CLASS_HID_882b] = 619,\n+\t[BNXT_ULP_CLASS_HID_ba93] = 620,\n+\t[BNXT_ULP_CLASS_HID_d78b] = 621,\n+\t[BNXT_ULP_CLASS_HID_c873] = 622,\n+\t[BNXT_ULP_CLASS_HID_90fb] = 623,\n+\t[BNXT_ULP_CLASS_HID_c153] = 624,\n+\t[BNXT_ULP_CLASS_HID_fe5b] = 625,\n+\t[BNXT_ULP_CLASS_HID_d033] = 626,\n+\t[BNXT_ULP_CLASS_HID_9cc3] = 627,\n+\t[BNXT_ULP_CLASS_HID_ceb3] = 628,\n+\t[BNXT_ULP_CLASS_HID_eba3] = 629,\n+\t[BNXT_ULP_CLASS_HID_dc13] = 630,\n+\t[BNXT_ULP_CLASS_HID_a493] = 631,\n+\t[BNXT_ULP_CLASS_HID_d573] = 632,\n+\t[BNXT_ULP_CLASS_HID_f273] = 633,\n+\t[BNXT_ULP_CLASS_HID_cdb3] = 634,\n+\t[BNXT_ULP_CLASS_HID_ff35] = 635,\n+\t[BNXT_ULP_CLASS_HID_b4f1] = 636,\n+\t[BNXT_ULP_CLASS_HID_d79d] = 637,\n+\t[BNXT_ULP_CLASS_HID_e615] = 638,\n+\t[BNXT_ULP_CLASS_HID_8ea9] = 639,\n+\t[BNXT_ULP_CLASS_HID_dd21] = 640,\n+\t[BNXT_ULP_CLASS_HID_ffcd] = 641,\n+\t[BNXT_ULP_CLASS_HID_ce45] = 642,\n+\t[BNXT_ULP_CLASS_HID_9259] = 643,\n+\t[BNXT_ULP_CLASS_HID_a0d9] = 644,\n+\t[BNXT_ULP_CLASS_HID_c3fd] = 645,\n+\t[BNXT_ULP_CLASS_HID_d27d] = 646,\n+\t[BNXT_ULP_CLASS_HID_ba89] = 647,\n+\t[BNXT_ULP_CLASS_HID_c909] = 648,\n+\t[BNXT_ULP_CLASS_HID_ec2d] = 649,\n+\t[BNXT_ULP_CLASS_HID_faad] = 650,\n+\t[BNXT_ULP_CLASS_HID_34c6] = 651,\n+\t[BNXT_ULP_CLASS_HID_0c22] = 652,\n+\t[BNXT_ULP_CLASS_HID_1cbe] = 653,\n+\t[BNXT_ULP_CLASS_HID_179a] = 654,\n+\t[BNXT_ULP_CLASS_HID_59be] = 655,\n+\t[BNXT_ULP_CLASS_HID_515a] = 656,\n+\t[BNXT_ULP_CLASS_HID_1c72] = 657,\n+\t[BNXT_ULP_CLASS_HID_171e] = 658,\n+\t[BNXT_ULP_CLASS_HID_19c8] = 659,\n+\t[BNXT_ULP_CLASS_HID_112c] = 660,\n+\t[BNXT_ULP_CLASS_HID_4d68] = 661,\n+\t[BNXT_ULP_CLASS_HID_444c] = 662,\n+\t[BNXT_ULP_CLASS_HID_0e8c] = 663,\n+\t[BNXT_ULP_CLASS_HID_09e0] = 664,\n+\t[BNXT_ULP_CLASS_HID_1af0] = 665,\n+\t[BNXT_ULP_CLASS_HID_15d4] = 666,\n+\t[BNXT_ULP_CLASS_HID_1dd0] = 667,\n+\t[BNXT_ULP_CLASS_HID_14f4] = 668,\n+\t[BNXT_ULP_CLASS_HID_70b0] = 669,\n+\t[BNXT_ULP_CLASS_HID_4854] = 670,\n+\t[BNXT_ULP_CLASS_HID_3dd4] = 671,\n+\t[BNXT_ULP_CLASS_HID_34f8] = 672,\n+\t[BNXT_ULP_CLASS_HID_09e8] = 673,\n+\t[BNXT_ULP_CLASS_HID_008c] = 674,\n+\t[BNXT_ULP_CLASS_HID_34e6] = 675,\n+\t[BNXT_ULP_CLASS_HID_0c02] = 676,\n+\t[BNXT_ULP_CLASS_HID_1c9e] = 677,\n+\t[BNXT_ULP_CLASS_HID_17ba] = 678,\n+\t[BNXT_ULP_CLASS_HID_429e] = 679,\n+\t[BNXT_ULP_CLASS_HID_5dba] = 680,\n+\t[BNXT_ULP_CLASS_HID_2a16] = 681,\n+\t[BNXT_ULP_CLASS_HID_2532] = 682,\n+\t[BNXT_ULP_CLASS_HID_2da2] = 683,\n+\t[BNXT_ULP_CLASS_HID_24fe] = 684,\n+\t[BNXT_ULP_CLASS_HID_355a] = 685,\n+\t[BNXT_ULP_CLASS_HID_0c76] = 686,\n+\t[BNXT_ULP_CLASS_HID_13e6] = 687,\n+\t[BNXT_ULP_CLASS_HID_7276] = 688,\n+\t[BNXT_ULP_CLASS_HID_42d2] = 689,\n+\t[BNXT_ULP_CLASS_HID_5dee] = 690,\n+\t[BNXT_ULP_CLASS_HID_59de] = 691,\n+\t[BNXT_ULP_CLASS_HID_513a] = 692,\n+\t[BNXT_ULP_CLASS_HID_1c12] = 693,\n+\t[BNXT_ULP_CLASS_HID_177e] = 694,\n+\t[BNXT_ULP_CLASS_HID_0e92] = 695,\n+\t[BNXT_ULP_CLASS_HID_09fe] = 696,\n+\t[BNXT_ULP_CLASS_HID_5c1a] = 697,\n+\t[BNXT_ULP_CLASS_HID_5746] = 698,\n+\t[BNXT_ULP_CLASS_HID_79da] = 699,\n+\t[BNXT_ULP_CLASS_HID_7106] = 700,\n+\t[BNXT_ULP_CLASS_HID_3c1e] = 701,\n+\t[BNXT_ULP_CLASS_HID_377a] = 702,\n+\t[BNXT_ULP_CLASS_HID_2e9e] = 703,\n+\t[BNXT_ULP_CLASS_HID_29fa] = 704,\n+\t[BNXT_ULP_CLASS_HID_14d2] = 705,\n+\t[BNXT_ULP_CLASS_HID_7742] = 706,\n+\t[BNXT_ULP_CLASS_HID_3706] = 707,\n+\t[BNXT_ULP_CLASS_HID_0fe2] = 708,\n+\t[BNXT_ULP_CLASS_HID_1f7e] = 709,\n+\t[BNXT_ULP_CLASS_HID_145a] = 710,\n+\t[BNXT_ULP_CLASS_HID_417e] = 711,\n+\t[BNXT_ULP_CLASS_HID_5e5a] = 712,\n+\t[BNXT_ULP_CLASS_HID_29f6] = 713,\n+\t[BNXT_ULP_CLASS_HID_26d2] = 714,\n+\t[BNXT_ULP_CLASS_HID_2e42] = 715,\n+\t[BNXT_ULP_CLASS_HID_271e] = 716,\n+\t[BNXT_ULP_CLASS_HID_36ba] = 717,\n+\t[BNXT_ULP_CLASS_HID_0f96] = 718,\n+\t[BNXT_ULP_CLASS_HID_1006] = 719,\n+\t[BNXT_ULP_CLASS_HID_7196] = 720,\n+\t[BNXT_ULP_CLASS_HID_4132] = 721,\n+\t[BNXT_ULP_CLASS_HID_5e0e] = 722,\n+\t[BNXT_ULP_CLASS_HID_59fe] = 723,\n+\t[BNXT_ULP_CLASS_HID_511a] = 724,\n+\t[BNXT_ULP_CLASS_HID_1c32] = 725,\n+\t[BNXT_ULP_CLASS_HID_175e] = 726,\n+\t[BNXT_ULP_CLASS_HID_0eb2] = 727,\n+\t[BNXT_ULP_CLASS_HID_09de] = 728,\n+\t[BNXT_ULP_CLASS_HID_5c3a] = 729,\n+\t[BNXT_ULP_CLASS_HID_5766] = 730,\n+\t[BNXT_ULP_CLASS_HID_79fa] = 731,\n+\t[BNXT_ULP_CLASS_HID_7126] = 732,\n+\t[BNXT_ULP_CLASS_HID_3c3e] = 733,\n+\t[BNXT_ULP_CLASS_HID_375a] = 734,\n+\t[BNXT_ULP_CLASS_HID_2ebe] = 735,\n+\t[BNXT_ULP_CLASS_HID_29da] = 736,\n+\t[BNXT_ULP_CLASS_HID_14f2] = 737,\n+\t[BNXT_ULP_CLASS_HID_7762] = 738,\n+\t[BNXT_ULP_CLASS_HID_19e8] = 739,\n+\t[BNXT_ULP_CLASS_HID_110c] = 740,\n+\t[BNXT_ULP_CLASS_HID_4d48] = 741,\n+\t[BNXT_ULP_CLASS_HID_446c] = 742,\n+\t[BNXT_ULP_CLASS_HID_0eac] = 743,\n+\t[BNXT_ULP_CLASS_HID_09c0] = 744,\n+\t[BNXT_ULP_CLASS_HID_1ad0] = 745,\n+\t[BNXT_ULP_CLASS_HID_15f4] = 746,\n+\t[BNXT_ULP_CLASS_HID_39ec] = 747,\n+\t[BNXT_ULP_CLASS_HID_3100] = 748,\n+\t[BNXT_ULP_CLASS_HID_0210] = 749,\n+\t[BNXT_ULP_CLASS_HID_1d34] = 750,\n+\t[BNXT_ULP_CLASS_HID_2ea0] = 751,\n+\t[BNXT_ULP_CLASS_HID_29c4] = 752,\n+\t[BNXT_ULP_CLASS_HID_3ad4] = 753,\n+\t[BNXT_ULP_CLASS_HID_35e8] = 754,\n+\t[BNXT_ULP_CLASS_HID_5d80] = 755,\n+\t[BNXT_ULP_CLASS_HID_54a4] = 756,\n+\t[BNXT_ULP_CLASS_HID_29b4] = 757,\n+\t[BNXT_ULP_CLASS_HID_20c8] = 758,\n+\t[BNXT_ULP_CLASS_HID_7244] = 759,\n+\t[BNXT_ULP_CLASS_HID_4d98] = 760,\n+\t[BNXT_ULP_CLASS_HID_5e68] = 761,\n+\t[BNXT_ULP_CLASS_HID_598c] = 762,\n+\t[BNXT_ULP_CLASS_HID_1248] = 763,\n+\t[BNXT_ULP_CLASS_HID_74d8] = 764,\n+\t[BNXT_ULP_CLASS_HID_49a8] = 765,\n+\t[BNXT_ULP_CLASS_HID_40cc] = 766,\n+\t[BNXT_ULP_CLASS_HID_0b0c] = 767,\n+\t[BNXT_ULP_CLASS_HID_0220] = 768,\n+\t[BNXT_ULP_CLASS_HID_1730] = 769,\n+\t[BNXT_ULP_CLASS_HID_7980] = 770,\n+\t[BNXT_ULP_CLASS_HID_1db0] = 771,\n+\t[BNXT_ULP_CLASS_HID_1494] = 772,\n+\t[BNXT_ULP_CLASS_HID_70d0] = 773,\n+\t[BNXT_ULP_CLASS_HID_4834] = 774,\n+\t[BNXT_ULP_CLASS_HID_3db4] = 775,\n+\t[BNXT_ULP_CLASS_HID_3498] = 776,\n+\t[BNXT_ULP_CLASS_HID_0988] = 777,\n+\t[BNXT_ULP_CLASS_HID_00ec] = 778,\n+\t[BNXT_ULP_CLASS_HID_3f44] = 779,\n+\t[BNXT_ULP_CLASS_HID_36a8] = 780,\n+\t[BNXT_ULP_CLASS_HID_0b58] = 781,\n+\t[BNXT_ULP_CLASS_HID_02bc] = 782,\n+\t[BNXT_ULP_CLASS_HID_5f48] = 783,\n+\t[BNXT_ULP_CLASS_HID_56ac] = 784,\n+\t[BNXT_ULP_CLASS_HID_2b5c] = 785,\n+\t[BNXT_ULP_CLASS_HID_2280] = 786,\n+\t[BNXT_ULP_CLASS_HID_4000] = 787,\n+\t[BNXT_ULP_CLASS_HID_5b64] = 788,\n+\t[BNXT_ULP_CLASS_HID_2c14] = 789,\n+\t[BNXT_ULP_CLASS_HID_2778] = 790,\n+\t[BNXT_ULP_CLASS_HID_18f8] = 791,\n+\t[BNXT_ULP_CLASS_HID_13dc] = 792,\n+\t[BNXT_ULP_CLASS_HID_4c18] = 793,\n+\t[BNXT_ULP_CLASS_HID_477c] = 794,\n+\t[BNXT_ULP_CLASS_HID_1a88] = 795,\n+\t[BNXT_ULP_CLASS_HID_15ec] = 796,\n+\t[BNXT_ULP_CLASS_HID_4e28] = 797,\n+\t[BNXT_ULP_CLASS_HID_490c] = 798,\n+\t[BNXT_ULP_CLASS_HID_3a8c] = 799,\n+\t[BNXT_ULP_CLASS_HID_35f0] = 800,\n+\t[BNXT_ULP_CLASS_HID_06e0] = 801,\n+\t[BNXT_ULP_CLASS_HID_01c4] = 802,\n+\t[BNXT_ULP_CLASS_HID_1a08] = 803,\n+\t[BNXT_ULP_CLASS_HID_12ec] = 804,\n+\t[BNXT_ULP_CLASS_HID_4ea8] = 805,\n+\t[BNXT_ULP_CLASS_HID_478c] = 806,\n+\t[BNXT_ULP_CLASS_HID_0d4c] = 807,\n+\t[BNXT_ULP_CLASS_HID_0a20] = 808,\n+\t[BNXT_ULP_CLASS_HID_1930] = 809,\n+\t[BNXT_ULP_CLASS_HID_1614] = 810,\n+\t[BNXT_ULP_CLASS_HID_3a0c] = 811,\n+\t[BNXT_ULP_CLASS_HID_32e0] = 812,\n+\t[BNXT_ULP_CLASS_HID_01f0] = 813,\n+\t[BNXT_ULP_CLASS_HID_1ed4] = 814,\n+\t[BNXT_ULP_CLASS_HID_2d40] = 815,\n+\t[BNXT_ULP_CLASS_HID_2a24] = 816,\n+\t[BNXT_ULP_CLASS_HID_3934] = 817,\n+\t[BNXT_ULP_CLASS_HID_3608] = 818,\n+\t[BNXT_ULP_CLASS_HID_5e60] = 819,\n+\t[BNXT_ULP_CLASS_HID_5744] = 820,\n+\t[BNXT_ULP_CLASS_HID_2a54] = 821,\n+\t[BNXT_ULP_CLASS_HID_2328] = 822,\n+\t[BNXT_ULP_CLASS_HID_71a4] = 823,\n+\t[BNXT_ULP_CLASS_HID_4e78] = 824,\n+\t[BNXT_ULP_CLASS_HID_5d88] = 825,\n+\t[BNXT_ULP_CLASS_HID_5a6c] = 826,\n+\t[BNXT_ULP_CLASS_HID_11a8] = 827,\n+\t[BNXT_ULP_CLASS_HID_7738] = 828,\n+\t[BNXT_ULP_CLASS_HID_4a48] = 829,\n+\t[BNXT_ULP_CLASS_HID_432c] = 830,\n+\t[BNXT_ULP_CLASS_HID_08ec] = 831,\n+\t[BNXT_ULP_CLASS_HID_01c0] = 832,\n+\t[BNXT_ULP_CLASS_HID_14d0] = 833,\n+\t[BNXT_ULP_CLASS_HID_7a60] = 834,\n+\t[BNXT_ULP_CLASS_HID_1d90] = 835,\n+\t[BNXT_ULP_CLASS_HID_14b4] = 836,\n+\t[BNXT_ULP_CLASS_HID_70f0] = 837,\n+\t[BNXT_ULP_CLASS_HID_4814] = 838,\n+\t[BNXT_ULP_CLASS_HID_3d94] = 839,\n+\t[BNXT_ULP_CLASS_HID_34b8] = 840,\n+\t[BNXT_ULP_CLASS_HID_09a8] = 841,\n+\t[BNXT_ULP_CLASS_HID_00cc] = 842,\n+\t[BNXT_ULP_CLASS_HID_3f64] = 843,\n+\t[BNXT_ULP_CLASS_HID_3688] = 844,\n+\t[BNXT_ULP_CLASS_HID_0b78] = 845,\n+\t[BNXT_ULP_CLASS_HID_029c] = 846,\n+\t[BNXT_ULP_CLASS_HID_5f68] = 847,\n+\t[BNXT_ULP_CLASS_HID_568c] = 848,\n+\t[BNXT_ULP_CLASS_HID_2b7c] = 849,\n+\t[BNXT_ULP_CLASS_HID_22a0] = 850,\n+\t[BNXT_ULP_CLASS_HID_4020] = 851,\n+\t[BNXT_ULP_CLASS_HID_5b44] = 852,\n+\t[BNXT_ULP_CLASS_HID_2c34] = 853,\n+\t[BNXT_ULP_CLASS_HID_2758] = 854,\n+\t[BNXT_ULP_CLASS_HID_18d8] = 855,\n+\t[BNXT_ULP_CLASS_HID_13fc] = 856,\n+\t[BNXT_ULP_CLASS_HID_4c38] = 857,\n+\t[BNXT_ULP_CLASS_HID_475c] = 858,\n+\t[BNXT_ULP_CLASS_HID_1aa8] = 859,\n+\t[BNXT_ULP_CLASS_HID_15cc] = 860,\n+\t[BNXT_ULP_CLASS_HID_4e08] = 861,\n+\t[BNXT_ULP_CLASS_HID_492c] = 862,\n+\t[BNXT_ULP_CLASS_HID_3aac] = 863,\n+\t[BNXT_ULP_CLASS_HID_35d0] = 864,\n+\t[BNXT_ULP_CLASS_HID_06c0] = 865,\n+\t[BNXT_ULP_CLASS_HID_01e4] = 866,\n+\t[BNXT_ULP_CLASS_HID_4d32] = 867,\n+\t[BNXT_ULP_CLASS_HID_54aa] = 868,\n+\t[BNXT_ULP_CLASS_HID_0686] = 869,\n+\t[BNXT_ULP_CLASS_HID_540e] = 870,\n+\t[BNXT_ULP_CLASS_HID_2e3c] = 871,\n+\t[BNXT_ULP_CLASS_HID_3a20] = 872,\n+\t[BNXT_ULP_CLASS_HID_46f0] = 873,\n+\t[BNXT_ULP_CLASS_HID_52e4] = 874,\n+\t[BNXT_ULP_CLASS_HID_55e4] = 875,\n+\t[BNXT_ULP_CLASS_HID_21f8] = 876,\n+\t[BNXT_ULP_CLASS_HID_75e8] = 877,\n+\t[BNXT_ULP_CLASS_HID_41fc] = 878,\n+\t[BNXT_ULP_CLASS_HID_4d12] = 879,\n+\t[BNXT_ULP_CLASS_HID_548a] = 880,\n+\t[BNXT_ULP_CLASS_HID_3356] = 881,\n+\t[BNXT_ULP_CLASS_HID_1ace] = 882,\n+\t[BNXT_ULP_CLASS_HID_1a9a] = 883,\n+\t[BNXT_ULP_CLASS_HID_4d46] = 884,\n+\t[BNXT_ULP_CLASS_HID_2812] = 885,\n+\t[BNXT_ULP_CLASS_HID_338a] = 886,\n+\t[BNXT_ULP_CLASS_HID_06e6] = 887,\n+\t[BNXT_ULP_CLASS_HID_546e] = 888,\n+\t[BNXT_ULP_CLASS_HID_46ee] = 889,\n+\t[BNXT_ULP_CLASS_HID_0d22] = 890,\n+\t[BNXT_ULP_CLASS_HID_26e2] = 891,\n+\t[BNXT_ULP_CLASS_HID_746a] = 892,\n+\t[BNXT_ULP_CLASS_HID_1fa6] = 893,\n+\t[BNXT_ULP_CLASS_HID_2d2e] = 894,\n+\t[BNXT_ULP_CLASS_HID_4ef2] = 895,\n+\t[BNXT_ULP_CLASS_HID_576a] = 896,\n+\t[BNXT_ULP_CLASS_HID_30b6] = 897,\n+\t[BNXT_ULP_CLASS_HID_192e] = 898,\n+\t[BNXT_ULP_CLASS_HID_197a] = 899,\n+\t[BNXT_ULP_CLASS_HID_4ea6] = 900,\n+\t[BNXT_ULP_CLASS_HID_2bf2] = 901,\n+\t[BNXT_ULP_CLASS_HID_306a] = 902,\n+\t[BNXT_ULP_CLASS_HID_06c6] = 903,\n+\t[BNXT_ULP_CLASS_HID_544e] = 904,\n+\t[BNXT_ULP_CLASS_HID_46ce] = 905,\n+\t[BNXT_ULP_CLASS_HID_0d02] = 906,\n+\t[BNXT_ULP_CLASS_HID_26c2] = 907,\n+\t[BNXT_ULP_CLASS_HID_744a] = 908,\n+\t[BNXT_ULP_CLASS_HID_1f86] = 909,\n+\t[BNXT_ULP_CLASS_HID_2d0e] = 910,\n+\t[BNXT_ULP_CLASS_HID_2e1c] = 911,\n+\t[BNXT_ULP_CLASS_HID_3a00] = 912,\n+\t[BNXT_ULP_CLASS_HID_46d0] = 913,\n+\t[BNXT_ULP_CLASS_HID_52c4] = 914,\n+\t[BNXT_ULP_CLASS_HID_4e10] = 915,\n+\t[BNXT_ULP_CLASS_HID_5a04] = 916,\n+\t[BNXT_ULP_CLASS_HID_1f98] = 917,\n+\t[BNXT_ULP_CLASS_HID_72f8] = 918,\n+\t[BNXT_ULP_CLASS_HID_0a78] = 919,\n+\t[BNXT_ULP_CLASS_HID_166c] = 920,\n+\t[BNXT_ULP_CLASS_HID_233c] = 921,\n+\t[BNXT_ULP_CLASS_HID_0f20] = 922,\n+\t[BNXT_ULP_CLASS_HID_2a7c] = 923,\n+\t[BNXT_ULP_CLASS_HID_3660] = 924,\n+\t[BNXT_ULP_CLASS_HID_4330] = 925,\n+\t[BNXT_ULP_CLASS_HID_2f24] = 926,\n+\t[BNXT_ULP_CLASS_HID_5584] = 927,\n+\t[BNXT_ULP_CLASS_HID_2198] = 928,\n+\t[BNXT_ULP_CLASS_HID_7588] = 929,\n+\t[BNXT_ULP_CLASS_HID_419c] = 930,\n+\t[BNXT_ULP_CLASS_HID_7758] = 931,\n+\t[BNXT_ULP_CLASS_HID_43ac] = 932,\n+\t[BNXT_ULP_CLASS_HID_0c10] = 933,\n+\t[BNXT_ULP_CLASS_HID_1864] = 934,\n+\t[BNXT_ULP_CLASS_HID_30c8] = 935,\n+\t[BNXT_ULP_CLASS_HID_1cdc] = 936,\n+\t[BNXT_ULP_CLASS_HID_50cc] = 937,\n+\t[BNXT_ULP_CLASS_HID_3d20] = 938,\n+\t[BNXT_ULP_CLASS_HID_529c] = 939,\n+\t[BNXT_ULP_CLASS_HID_3ef0] = 940,\n+\t[BNXT_ULP_CLASS_HID_72e0] = 941,\n+\t[BNXT_ULP_CLASS_HID_5ef4] = 942,\n+\t[BNXT_ULP_CLASS_HID_2dfc] = 943,\n+\t[BNXT_ULP_CLASS_HID_39e0] = 944,\n+\t[BNXT_ULP_CLASS_HID_4530] = 945,\n+\t[BNXT_ULP_CLASS_HID_5124] = 946,\n+\t[BNXT_ULP_CLASS_HID_4df0] = 947,\n+\t[BNXT_ULP_CLASS_HID_59e4] = 948,\n+\t[BNXT_ULP_CLASS_HID_1c78] = 949,\n+\t[BNXT_ULP_CLASS_HID_7118] = 950,\n+\t[BNXT_ULP_CLASS_HID_0998] = 951,\n+\t[BNXT_ULP_CLASS_HID_158c] = 952,\n+\t[BNXT_ULP_CLASS_HID_20dc] = 953,\n+\t[BNXT_ULP_CLASS_HID_0cc0] = 954,\n+\t[BNXT_ULP_CLASS_HID_299c] = 955,\n+\t[BNXT_ULP_CLASS_HID_3580] = 956,\n+\t[BNXT_ULP_CLASS_HID_40d0] = 957,\n+\t[BNXT_ULP_CLASS_HID_2cc4] = 958,\n+\t[BNXT_ULP_CLASS_HID_55a4] = 959,\n+\t[BNXT_ULP_CLASS_HID_21b8] = 960,\n+\t[BNXT_ULP_CLASS_HID_75a8] = 961,\n+\t[BNXT_ULP_CLASS_HID_41bc] = 962,\n+\t[BNXT_ULP_CLASS_HID_7778] = 963,\n+\t[BNXT_ULP_CLASS_HID_438c] = 964,\n+\t[BNXT_ULP_CLASS_HID_0c30] = 965,\n+\t[BNXT_ULP_CLASS_HID_1844] = 966,\n+\t[BNXT_ULP_CLASS_HID_30e8] = 967,\n+\t[BNXT_ULP_CLASS_HID_1cfc] = 968,\n+\t[BNXT_ULP_CLASS_HID_50ec] = 969,\n+\t[BNXT_ULP_CLASS_HID_3d00] = 970,\n+\t[BNXT_ULP_CLASS_HID_52bc] = 971,\n+\t[BNXT_ULP_CLASS_HID_3ed0] = 972,\n+\t[BNXT_ULP_CLASS_HID_72c0] = 973,\n+\t[BNXT_ULP_CLASS_HID_5ed4] = 974,\n+\t[BNXT_ULP_CLASS_HID_3866] = 975,\n+\t[BNXT_ULP_CLASS_HID_381e] = 976,\n+\t[BNXT_ULP_CLASS_HID_3860] = 977,\n+\t[BNXT_ULP_CLASS_HID_0454] = 978,\n+\t[BNXT_ULP_CLASS_HID_3818] = 979,\n+\t[BNXT_ULP_CLASS_HID_042c] = 980,\n+\t[BNXT_ULP_CLASS_HID_3846] = 981,\n+\t[BNXT_ULP_CLASS_HID_387e] = 982,\n+\t[BNXT_ULP_CLASS_HID_3ba6] = 983,\n+\t[BNXT_ULP_CLASS_HID_385e] = 984,\n+\t[BNXT_ULP_CLASS_HID_3840] = 985,\n+\t[BNXT_ULP_CLASS_HID_0474] = 986,\n+\t[BNXT_ULP_CLASS_HID_3878] = 987,\n+\t[BNXT_ULP_CLASS_HID_044c] = 988,\n+\t[BNXT_ULP_CLASS_HID_3ba0] = 989,\n+\t[BNXT_ULP_CLASS_HID_0794] = 990,\n+\t[BNXT_ULP_CLASS_HID_3858] = 991,\n+\t[BNXT_ULP_CLASS_HID_046c] = 992\n };\n \n /* Array for the proto matcher list */\n@@ -7165,7 +7309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }\n \t},\n \t[347] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_6165,\n+\t.class_hid = BNXT_ULP_CLASS_HID_e082,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 1313792,\n@@ -7176,7 +7320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7185,7 +7329,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }\n \t},\n \t[348] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2aa1,\n+\t.class_hid = BNXT_ULP_CLASS_HID_ab46,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 1321984,\n@@ -7196,7 +7340,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7206,7 +7350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }\n \t},\n \t[349] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_09cd,\n+\t.class_hid = BNXT_ULP_CLASS_HID_c82a,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 3410944,\n@@ -7217,7 +7361,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7227,7 +7371,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }\n \t},\n \t[350] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3845,\n+\t.class_hid = BNXT_ULP_CLASS_HID_f9a2,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 3419136,\n@@ -7238,7 +7382,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7249,10 +7393,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }\n \t},\n \t[351] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_11e9,\n+\t.class_hid = BNXT_ULP_CLASS_HID_d8ce,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2148797440,\n+\t.flow_sig_id = 538184704,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7260,20 +7404,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }\n \t},\n \t[352] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4361,\n+\t.class_hid = BNXT_ULP_CLASS_HID_a2d2,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2148805632,\n+\t.flow_sig_id = 538192896,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7281,7 +7425,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7289,13 +7433,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }\n \t},\n \t[353] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_218d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_c076,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2150894592,\n+\t.flow_sig_id = 540281856,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7303,7 +7447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7311,13 +7455,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }\n \t},\n \t[354] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5105,\n+\t.class_hid = BNXT_ULP_CLASS_HID_f1ee,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2150902784,\n+\t.flow_sig_id = 540290048,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7325,7 +7469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7334,13 +7478,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }\n \t},\n \t[355] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0c89,\n+\t.class_hid = BNXT_ULP_CLASS_HID_a96e,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4296281088,\n+\t.flow_sig_id = 1075055616,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7348,20 +7492,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[356] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3e81,\n+\t.class_hid = BNXT_ULP_CLASS_HID_dae6,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4296289280,\n+\t.flow_sig_id = 1075063808,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7369,7 +7513,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7377,13 +7521,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[357] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1dad,\n+\t.class_hid = BNXT_ULP_CLASS_HID_c7aa,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4298378240,\n+\t.flow_sig_id = 1077152768,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7391,7 +7535,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7399,13 +7543,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[358] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4ca5,\n+\t.class_hid = BNXT_ULP_CLASS_HID_c26e,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4298386432,\n+\t.flow_sig_id = 1077160960,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7413,7 +7557,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7422,13 +7566,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[359] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_25c9,\n+\t.class_hid = BNXT_ULP_CLASS_HID_a0fa,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 6443764736,\n+\t.flow_sig_id = 1611926528,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7436,21 +7580,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[360] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_57c1,\n+\t.class_hid = BNXT_ULP_CLASS_HID_d272,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 6443772928,\n+\t.flow_sig_id = 1611934720,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7458,7 +7602,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7466,14 +7610,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[361] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_33ed,\n+\t.class_hid = BNXT_ULP_CLASS_HID_fff6,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 6445861888,\n+\t.flow_sig_id = 1614023680,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7481,7 +7625,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7489,14 +7633,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[362] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_65e5,\n+\t.class_hid = BNXT_ULP_CLASS_HID_e16e,\n \t.class_tid = 2,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 6445870080,\n+\t.flow_sig_id = 1614031872,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7504,7 +7648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7513,11 +7657,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[363] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_6dd9,\n+\t.class_hid = BNXT_ULP_CLASS_HID_e165,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 1313792,\n@@ -7529,7 +7673,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7538,7 +7681,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }\n \t},\n \t[364] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_261d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_aaa1,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 1321984,\n@@ -7550,7 +7693,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7560,7 +7702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }\n \t},\n \t[365] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0571,\n+\t.class_hid = BNXT_ULP_CLASS_HID_c9cd,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 3410944,\n@@ -7572,7 +7714,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7582,7 +7723,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }\n \t},\n \t[366] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_34f9,\n+\t.class_hid = BNXT_ULP_CLASS_HID_f845,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 3419136,\n@@ -7594,7 +7735,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7605,7 +7745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }\n \t},\n \t[367] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1d55,\n+\t.class_hid = BNXT_ULP_CLASS_HID_90f9,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 2148797440,\n@@ -7617,7 +7757,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7627,7 +7766,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }\n \t},\n \t[368] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4fdd,\n+\t.class_hid = BNXT_ULP_CLASS_HID_c371,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 2148805632,\n@@ -7639,7 +7778,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7650,7 +7788,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }\n \t},\n \t[369] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2d31,\n+\t.class_hid = BNXT_ULP_CLASS_HID_e19d,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 2150894592,\n@@ -7662,7 +7800,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7673,7 +7810,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }\n \t},\n \t[370] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5db9,\n+\t.class_hid = BNXT_ULP_CLASS_HID_d015,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 2150902784,\n@@ -7685,7 +7822,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7697,7 +7833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }\n \t},\n \t[371] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0035,\n+\t.class_hid = BNXT_ULP_CLASS_HID_8c09,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 4296281088,\n@@ -7709,7 +7845,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7719,7 +7854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n \t},\n \t[372] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_323d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_be89,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 4296289280,\n@@ -7731,7 +7866,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7742,7 +7876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n \t},\n \t[373] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1111,\n+\t.class_hid = BNXT_ULP_CLASS_HID_ddad,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 4298378240,\n@@ -7754,7 +7888,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7765,7 +7898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n \t},\n \t[374] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4019,\n+\t.class_hid = BNXT_ULP_CLASS_HID_cc2d,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 4298386432,\n@@ -7777,7 +7910,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7789,7 +7921,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n \t},\n \t[375] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2975,\n+\t.class_hid = BNXT_ULP_CLASS_HID_a4d9,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 6443764736,\n@@ -7801,7 +7933,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7812,7 +7943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n \t},\n \t[376] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5b7d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_d759,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 6443772928,\n@@ -7824,7 +7955,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7836,7 +7966,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n \t},\n \t[377] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3f51,\n+\t.class_hid = BNXT_ULP_CLASS_HID_f27d,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 6445861888,\n@@ -7848,7 +7978,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7860,7 +7989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n \t},\n \t[378] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_6959,\n+\t.class_hid = BNXT_ULP_CLASS_HID_e4fd,\n \t.class_tid = 2,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 6445870080,\n@@ -7872,7 +8001,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n \t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n@@ -7885,10 +8013,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n \t},\n \t[379] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0e85,\n+\t.class_hid = BNXT_ULP_CLASS_HID_ecf6,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 8591248384,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 1313792,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7896,21 +8024,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }\n \t},\n \t[380] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_380d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_a732,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 8591256576,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 1321984,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7918,22 +8045,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }\n \t},\n \t[381] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1f21,\n+\t.class_hid = BNXT_ULP_CLASS_HID_c45e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 8593345536,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 3410944,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7941,22 +8067,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }\n \t},\n \t[382] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4ea9,\n+\t.class_hid = BNXT_ULP_CLASS_HID_f5d6,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 8593353728,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 3419136,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7964,23 +8089,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }\n \t},\n \t[383] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1705,\n+\t.class_hid = BNXT_ULP_CLASS_HID_d4ba,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 10738732032,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 538184704,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -7988,22 +8112,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }\n \t},\n \t[384] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_418d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_aea6,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 10738740224,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 538192896,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8011,23 +8134,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }\n \t},\n \t[385] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2721,\n+\t.class_hid = BNXT_ULP_CLASS_HID_cc02,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 10740829184,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 540281856,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8035,23 +8157,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }\n \t},\n \t[386] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_57a9,\n+\t.class_hid = BNXT_ULP_CLASS_HID_fd9a,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 10740837376,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 540290048,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8059,24 +8180,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }\n \t},\n \t[387] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1a25,\n+\t.class_hid = BNXT_ULP_CLASS_HID_a51a,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 12886215680,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 1075055616,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8084,22 +8204,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[388] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_342d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_d692,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 12886223872,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 1075063808,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8107,23 +8226,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[389] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2b01,\n+\t.class_hid = BNXT_ULP_CLASS_HID_cbde,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 12888312832,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 1077152768,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8131,23 +8249,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[390] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5a09,\n+\t.class_hid = BNXT_ULP_CLASS_HID_ce1a,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 12888321024,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 1077160960,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8155,24 +8272,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[391] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2325,\n+\t.class_hid = BNXT_ULP_CLASS_HID_ac8e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 15033699328,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 1611926528,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8180,23 +8296,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[392] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5d2d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_de06,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 15033707520,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 1611934720,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8204,24 +8319,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[393] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3101,\n+\t.class_hid = BNXT_ULP_CLASS_HID_f382,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 15035796480,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 1614023680,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8229,24 +8343,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[394] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_6309,\n+\t.class_hid = BNXT_ULP_CLASS_HID_ed1a,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 15035804672,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 1614031872,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8254,25 +8367,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }\n \t},\n \t[395] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0bad,\n+\t.class_hid = BNXT_ULP_CLASS_HID_9d6a,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 17181182976,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 2148797440,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8280,21 +8392,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[396] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2535,\n+\t.class_hid = BNXT_ULP_CLASS_HID_cee2,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 17181191168,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 2148805632,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8302,22 +8414,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[397] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1869,\n+\t.class_hid = BNXT_ULP_CLASS_HID_ec0e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 17183280128,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 2150894592,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8325,22 +8437,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[398] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4bf1,\n+\t.class_hid = BNXT_ULP_CLASS_HID_dd86,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 17183288320,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 2150902784,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8348,23 +8460,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[399] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_136d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_852e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 19328666624,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 2685668352,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8372,22 +8484,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[400] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_43f5,\n+\t.class_hid = BNXT_ULP_CLASS_HID_b6a6,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 19328674816,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 2685676544,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8395,23 +8507,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[401] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2129,\n+\t.class_hid = BNXT_ULP_CLASS_HID_eb82,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 19330763776,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 2687765504,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8419,23 +8531,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[402] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_53b1,\n+\t.class_hid = BNXT_ULP_CLASS_HID_c50a,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 19330771968,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 2687773696,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8443,24 +8555,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[403] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_072d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_ccca,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 21476150272,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 3222539264,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8468,22 +8580,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[404] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3135,\n+\t.class_hid = BNXT_ULP_CLASS_HID_8706,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 21476158464,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 3222547456,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8491,23 +8603,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[405] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1429,\n+\t.class_hid = BNXT_ULP_CLASS_HID_d38e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 21478247424,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 3224636416,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8515,23 +8627,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[406] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4731,\n+\t.class_hid = BNXT_ULP_CLASS_HID_d5ca,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 21478255616,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 3224644608,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8539,24 +8651,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[407] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2f6d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_b48e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 23623633920,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 3759410176,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8564,23 +8676,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[408] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5f75,\n+\t.class_hid = BNXT_ULP_CLASS_HID_8e8a,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 23623642112,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 3759418368,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8588,24 +8700,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[409] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3d69,\n+\t.class_hid = BNXT_ULP_CLASS_HID_db02,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 23625731072,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 3761507328,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8613,24 +8725,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n \t},\n \t[410] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_6f71,\n+\t.class_hid = BNXT_ULP_CLASS_HID_dd8e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 23625739264,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 3761515520,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8638,25 +8750,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n-\t},\n-\t[411] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0dbd,\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[411] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_819a,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 25771117568,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 4296281088,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8664,22 +8776,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[412] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3f25,\n+\t.class_hid = BNXT_ULP_CLASS_HID_b31a,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 25771125760,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 4296289280,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8687,23 +8798,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[413] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1239,\n+\t.class_hid = BNXT_ULP_CLASS_HID_d03e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 25773214720,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 4298378240,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8711,23 +8821,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[414] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4da1,\n+\t.class_hid = BNXT_ULP_CLASS_HID_c1be,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 25773222912,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 4298386432,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8735,24 +8844,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[415] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_153d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_890e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 27918601216,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 4833152000,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8760,23 +8868,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[416] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_45a5,\n+\t.class_hid = BNXT_ULP_CLASS_HID_ba8e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 27918609408,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 4833160192,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8784,24 +8891,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[417] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3bb9,\n+\t.class_hid = BNXT_ULP_CLASS_HID_dfaa,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 27920698368,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 4835249152,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8809,24 +8915,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[418] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_55a1,\n+\t.class_hid = BNXT_ULP_CLASS_HID_c93a,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 27920706560,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 4835257344,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8834,25 +8939,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[419] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_193d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_b11a,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 30066084864,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 5370022912,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8860,23 +8964,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[420] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4b25,\n+\t.class_hid = BNXT_ULP_CLASS_HID_8b4e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 30066093056,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 5370031104,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8884,24 +8987,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[421] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2e39,\n+\t.class_hid = BNXT_ULP_CLASS_HID_c79e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 30068182016,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 5372120064,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8909,24 +9011,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[422] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5921,\n+\t.class_hid = BNXT_ULP_CLASS_HID_d9da,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 30068190208,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 5372128256,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8934,25 +9035,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[423] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_213d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_b88e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 32213568512,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 5906893824,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8960,24 +9060,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[424] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5125,\n+\t.class_hid = BNXT_ULP_CLASS_HID_ea0e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 32213576704,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 5906902016,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -8985,25 +9084,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[425] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3739,\n+\t.class_hid = BNXT_ULP_CLASS_HID_cf0a,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 32215665664,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 5908990976,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -9011,25 +9109,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n \t},\n \t[426] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_093d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_c18e,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 32215673856,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 5908999168,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n \t.hdr_sig = { .bits =\n@@ -9037,25 +9134,3496 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n \t\tBNXT_ULP_HDR_BIT_I_ETH |\n-\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_I_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[427] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a94a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 6443764736,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[428] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_daca,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 6443772928,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[429] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ffee,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 6445861888,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[430] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e96e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 6445870080,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[431] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_910e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 6980635648,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[432] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c28e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 6980643840,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[433] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e7aa,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 6982732800,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[434] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d12a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 6982740992,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[435] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d8ca,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 7517506560,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[436] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_930e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 7517514752,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[437] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ef4e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 7519603712,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[438] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e18a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 7519611904,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[439] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c08e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 8054377472,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[440] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9a8a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 8054385664,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[441] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d70a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 8056474624,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[442] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e90e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 8056482816,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[443] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_edd9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 1313792,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }\n+\t},\n+\t[444] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a61d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 1321984,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }\n+\t},\n+\t[445] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c571,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 3410944,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }\n+\t},\n+\t[446] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f4f9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 3419136,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }\n+\t},\n+\t[447] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9c45,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 2148797440,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[448] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cfcd,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 2148805632,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[449] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ed21,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 2150894592,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[450] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dca9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 2150902784,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[451] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_80b5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 4296281088,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[452] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b235,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 4296289280,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[453] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d111,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 4298378240,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[454] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c091,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 4298386432,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[455] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a865,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 6443764736,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[456] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dbe5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 6443772928,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[457] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fec1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 6445861888,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[458] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e841,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 6445870080,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[459] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8e85,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 8591248384,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[460] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b80d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 8591256576,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[461] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_df65,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 8593345536,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[462] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ceed,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 8593353728,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[463] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9645,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10738732032,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[464] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c1cd,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10738740224,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[465] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e725,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10740829184,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[466] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d6ad,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10740837376,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[467] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9aa5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 12886215680,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[468] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b425,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 12886223872,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[469] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_eb05,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 12888312832,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[470] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_da85,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 12888321024,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[471] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a265,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 15033699328,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[472] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dde5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 15033707520,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[473] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f0c5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 15035796480,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[474] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e245,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 15035804672,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[475] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8b8f,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 17181182976,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[476] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a517,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 17181191168,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[477] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d86b,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 17183280128,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[478] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cbf3,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 17183288320,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[479] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_934f,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 19328666624,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[480] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c2c7,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 19328674816,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[481] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e02b,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 19330763776,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[482] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d3a3,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 19330771968,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[483] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_87a7,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 21476150272,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[484] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b137,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 21476158464,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[485] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d403,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 21478247424,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[486] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c793,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 21478255616,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[487] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_af67,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 23623633920,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[488] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dee7,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 23623642112,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[489] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fdc3,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 23625731072,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[490] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ef43,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 23625739264,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[491] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8dbf,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 25771117568,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[492] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bf07,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 25771125760,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[493] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d21f,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 25773214720,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[494] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cde7,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 25773222912,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[495] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_956f,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 27918601216,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[496] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c4c7,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 27918609408,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[497] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fbcf,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 27920698368,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[498] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d5a7,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 27920706560,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[499] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9957,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 30066084864,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[500] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cb27,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 30066093056,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[501] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ee37,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 30068182016,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[502] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d987,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 30068190208,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[503] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a107,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 32213568512,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[504] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d0e7,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 32213576704,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[505] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f7e7,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 32215665664,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[506] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c827,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 32215673856,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[507] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f76a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 1313792,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }\n+\t},\n+\t[508] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bcae,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 1321984,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }\n+\t},\n+\t[509] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dfc2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 3410944,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }\n+\t},\n+\t[510] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ee4a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 3419136,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }\n+\t},\n+\t[511] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cf26,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 538184704,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }\n+\t},\n+\t[512] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b53a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 538192896,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }\n+\t},\n+\t[513] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d79e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 540281856,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }\n+\t},\n+\t[514] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e606,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 540290048,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }\n+\t},\n+\t[515] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_be86,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 1075055616,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }\n+\t},\n+\t[516] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cd0e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 1075063808,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }\n+\t},\n+\t[517] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d042,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 1077152768,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }\n+\t},\n+\t[518] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d586,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 1077160960,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }\n+\t},\n+\t[519] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b712,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 1611926528,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }\n+\t},\n+\t[520] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c59a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 1611934720,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }\n+\t},\n+\t[521] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e81e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 1614023680,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }\n+\t},\n+\t[522] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f686,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 1614031872,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }\n+\t},\n+\t[523] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_86f6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 2148797440,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[524] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d57e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 2148805632,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[525] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f792,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 2150894592,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[526] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c61a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 2150902784,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[527] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9eb2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 2685668352,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[528] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ad3a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 2685676544,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[529] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f01e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 2687765504,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[530] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_de96,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 2687773696,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[531] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d756,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 3222539264,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[532] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9c9a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 3222547456,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[533] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c812,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 3224636416,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[534] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ce56,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 3224644608,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[535] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_af12,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 3759410176,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[536] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9516,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 3759418368,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[537] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c09e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 3761507328,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[538] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c612,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 3761515520,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[539] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9a06,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 4296281088,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[540] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a886,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 4296289280,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[541] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cba2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 4298378240,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[542] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_da22,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 4298386432,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[543] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9292,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 4833152000,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[544] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a112,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 4833160192,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[545] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c436,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 4835249152,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[546] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d2a6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 4835257344,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[547] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aa86,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 5370022912,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[548] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_90d2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 5370031104,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[549] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dc02,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 5372120064,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[550] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c246,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 5372128256,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[551] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a312,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 5906893824,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[552] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f192,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 5906902016,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[553] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d496,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 5908990976,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[554] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_da12,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 5908999168,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[555] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b2d6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 6443764736,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[556] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c156,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 6443772928,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[557] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e472,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 6445861888,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[558] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f2f2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 6445870080,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[559] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8a92,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 6980635648,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[560] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d912,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 6980643840,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[561] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fc36,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 6982732800,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[562] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cab6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 6982740992,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[563] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c356,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 7517506560,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[564] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8892,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 7517514752,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[565] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f4d2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 7519603712,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[566] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fa16,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 7519611904,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[567] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_db12,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 8054377472,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[568] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8116,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 8054385664,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[569] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cc96,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 8056474624,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[570] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f292,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 8056482816,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[427] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_684d,\n+\t[571] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e84d,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 1313792,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9068,15 +12636,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }\n \t},\n-\t[428] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2389,\n+\t[572] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a389,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 1321984,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9089,16 +12657,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }\n \t},\n-\t[429] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00e5,\n+\t[573] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c0e5,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 3410944,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9111,16 +12679,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }\n \t},\n-\t[430] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_316d,\n+\t[574] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f16d,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 3419136,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9133,17 +12701,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }\n \t},\n-\t[431] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_18c1,\n+\t[575] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_99d1,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 2148797440,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9156,16 +12724,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }\n \t},\n-\t[432] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4a49,\n+\t[576] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ca59,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 2148805632,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9178,17 +12746,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }\n \t},\n-\t[433] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_28a5,\n+\t[577] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e8b5,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 2150894592,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9201,17 +12769,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }\n \t},\n-\t[434] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_582d,\n+\t[578] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d93d,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 2150902784,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9224,18 +12792,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }\n \t},\n-\t[435] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_05a1,\n+\t[579] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8521,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 4296281088,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9248,16 +12816,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[436] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_37a9,\n+\t[580] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b7a1,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 4296289280,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9270,17 +12838,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[437] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1485,\n+\t[581] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d485,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 4298378240,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9293,17 +12861,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[438] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_458d,\n+\t[582] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c505,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 4298386432,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9316,18 +12884,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[439] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2ce1,\n+\t[583] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_adf1,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 6443764736,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9340,17 +12908,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[440] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5ee9,\n+\t[584] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_de71,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 6443772928,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9363,18 +12931,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[441] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3ac5,\n+\t[585] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fb55,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 6445861888,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9387,18 +12955,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[442] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_6ccd,\n+\t[586] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_edd5,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 6445870080,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9411,19 +12979,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[443] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0b11,\n+\t[587] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8b11,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 8591248384,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9436,16 +13004,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[444] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3d99,\n+\t[588] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bd99,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 8591256576,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9458,17 +13026,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[445] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1ab5,\n+\t[589] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_daf1,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 8593345536,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9481,17 +13049,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[446] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4b3d,\n+\t[590] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cb79,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 8593353728,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9504,18 +13072,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[447] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1291,\n+\t[591] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_93d1,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 10738732032,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9528,17 +13096,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[448] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4419,\n+\t[592] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c459,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 10738740224,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9551,18 +13119,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[449] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_22b5,\n+\t[593] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e2b1,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 10740829184,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9575,18 +13143,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[450] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_523d,\n+\t[594] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d339,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 10740837376,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9599,19 +13167,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[451] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1fb1,\n+\t[595] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9f31,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 12886215680,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9624,17 +13192,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[452] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_31b9,\n+\t[596] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b1b1,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 12886223872,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9647,18 +13215,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[453] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2e95,\n+\t[597] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ee91,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 12888312832,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9671,18 +13239,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[454] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5f9d,\n+\t[598] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_df11,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 12888321024,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9695,19 +13263,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[455] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_26b1,\n+\t[599] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a7f1,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 15033699328,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9720,18 +13288,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[456] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_58b9,\n+\t[600] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d871,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 15033707520,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9744,19 +13312,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[457] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3495,\n+\t[601] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f551,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 15035796480,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9769,19 +13337,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[458] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_669d,\n+\t[602] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e7d1,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 15035804672,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9794,20 +13362,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }\n \t},\n-\t[459] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0e39,\n+\t[603] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8e1b,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 17181182976,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9820,16 +13388,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[460] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_20a1,\n+\t[604] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a083,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 17181191168,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9842,17 +13410,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[461] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1dfd,\n+\t[605] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ddff,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 17183280128,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9865,17 +13433,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[462] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4e65,\n+\t[606] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ce67,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 17183288320,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9888,18 +13456,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[463] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_16f9,\n+\t[607] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_96db,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 19328666624,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9912,17 +13480,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[464] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4661,\n+\t[608] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c753,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 19328674816,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9935,18 +13503,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[465] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_24bd,\n+\t[609] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e5bf,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 19330763776,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9959,18 +13527,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[466] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5625,\n+\t[610] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d637,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 19330771968,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -9983,19 +13551,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[467] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_02b9,\n+\t[611] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8233,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 21476150272,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10008,17 +13576,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[468] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_34a1,\n+\t[612] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b4a3,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 21476158464,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10031,18 +13599,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[469] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_11bd,\n+\t[613] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d197,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 21478247424,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10055,18 +13623,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[470] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_42a5,\n+\t[614] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c207,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 21478255616,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10079,19 +13647,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[471] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2af9,\n+\t[615] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aaf3,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 23623633920,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10104,18 +13672,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[472] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5ae1,\n+\t[616] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_db73,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 23623642112,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10128,19 +13696,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[473] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_38fd,\n+\t[617] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f857,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 23625731072,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10153,19 +13721,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[474] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_6ae5,\n+\t[618] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ead7,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 23625739264,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10178,20 +13746,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[475] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0829,\n+\t[619] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_882b,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 25771117568,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10204,17 +13772,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[476] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3ab1,\n+\t[620] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ba93,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 25771125760,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10227,18 +13795,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[477] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_17ad,\n+\t[621] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d78b,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 25773214720,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10251,18 +13819,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[478] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4835,\n+\t[622] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c873,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 25773222912,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10275,19 +13843,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[479] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_10a9,\n+\t[623] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_90fb,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 27918601216,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10300,18 +13868,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[480] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4031,\n+\t[624] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c153,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 27918609408,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10324,19 +13892,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[481] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3e2d,\n+\t[625] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fe5b,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 27920698368,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10349,19 +13917,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[482] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5035,\n+\t[626] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d033,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 27920706560,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10374,20 +13942,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[483] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_1ca9,\n+\t[627] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9cc3,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 30066084864,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10400,18 +13968,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[484] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4eb1,\n+\t[628] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ceb3,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 30066093056,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10424,19 +13992,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[485] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2bad,\n+\t[629] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_eba3,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 30068182016,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10449,19 +14017,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[486] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5cb5,\n+\t[630] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dc13,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 30068190208,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10474,20 +14042,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[487] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_24a9,\n+\t[631] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a493,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 32213568512,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10500,19 +14068,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[488] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_54b1,\n+\t[632] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d573,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 32213576704,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10525,20 +14093,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[489] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_32ad,\n+\t[633] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f273,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 32215665664,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10551,20 +14119,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[490] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0ca9,\n+\t[634] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cdb3,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 6,\n \t.flow_sig_id = 32215673856,\n \t.flow_pattern_id = 1,\n \t.app_sig = 0,\n@@ -10577,21 +14145,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }\n \t},\n-\t[491] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_7f35,\n+\t[635] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ff35,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 1313792,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10604,15 +14172,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }\n \t},\n-\t[492] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_34f1,\n+\t[636] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b4f1,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 1321984,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10625,16 +14193,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }\n \t},\n-\t[493] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_179d,\n+\t[637] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d79d,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 3410944,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10647,16 +14215,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }\n \t},\n-\t[494] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2615,\n+\t[638] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e615,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 3419136,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10669,17 +14237,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }\n \t},\n-\t[495] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0fb9,\n+\t[639] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8ea9,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 2148797440,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10692,16 +14260,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }\n \t},\n-\t[496] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_5d31,\n+\t[640] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dd21,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 2148805632,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10714,17 +14282,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }\n \t},\n-\t[497] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3fdd,\n+\t[641] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ffcd,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 2150894592,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10737,17 +14305,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }\n \t},\n-\t[498] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4f55,\n+\t[642] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ce45,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 2150902784,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10760,18 +14328,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }\n \t},\n-\t[499] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_12d9,\n+\t[643] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9259,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 4296281088,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10784,16 +14352,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[500] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_20d1,\n+\t[644] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a0d9,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 4296289280,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10806,17 +14374,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[501] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_03fd,\n+\t[645] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c3fd,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 4298378240,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10829,17 +14397,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[502] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_52f5,\n+\t[646] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d27d,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 4298386432,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10852,18 +14420,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[503] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_3b99,\n+\t[647] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ba89,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 6443764736,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10876,17 +14444,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[504] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_4991,\n+\t[648] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c909,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 6443772928,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10899,18 +14467,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[505] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_2dbd,\n+\t[649] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ec2d,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 6445861888,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10923,18 +14491,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[506] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_7bb5,\n+\t[650] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_faad,\n \t.class_tid = 2,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 7,\n \t.flow_sig_id = 6445870080,\n \t.flow_pattern_id = 2,\n \t.app_sig = 0,\n@@ -10947,16 +14515,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_I_ICMP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }\n \t},\n-\t[507] = {\n+\t[651] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_34c6,\n \t.class_tid = 3,\n \t.hdr_sig_id = 0,\n@@ -10971,7 +14539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[508] = {\n+\t[652] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0c22,\n \t.class_tid = 3,\n \t.hdr_sig_id = 0,\n@@ -10987,7 +14555,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[509] = {\n+\t[653] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1cbe,\n \t.class_tid = 3,\n \t.hdr_sig_id = 0,\n@@ -11003,7 +14571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[510] = {\n+\t[654] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_179a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 0,\n@@ -11020,7 +14588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[511] = {\n+\t[655] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_59be,\n \t.class_tid = 3,\n \t.hdr_sig_id = 1,\n@@ -11035,7 +14603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[512] = {\n+\t[656] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_515a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 1,\n@@ -11051,7 +14619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[513] = {\n+\t[657] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1c72,\n \t.class_tid = 3,\n \t.hdr_sig_id = 1,\n@@ -11067,7 +14635,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[514] = {\n+\t[658] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_171e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 1,\n@@ -11084,7 +14652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[515] = {\n+\t[659] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_19c8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 2,\n@@ -11100,7 +14668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[516] = {\n+\t[660] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_112c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 2,\n@@ -11117,7 +14685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[517] = {\n+\t[661] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4d68,\n \t.class_tid = 3,\n \t.hdr_sig_id = 2,\n@@ -11134,7 +14702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[518] = {\n+\t[662] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_444c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 2,\n@@ -11152,7 +14720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[519] = {\n+\t[663] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0e8c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 2,\n@@ -11169,7 +14737,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[520] = {\n+\t[664] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_09e0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 2,\n@@ -11187,7 +14755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[521] = {\n+\t[665] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1af0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 2,\n@@ -11205,7 +14773,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[522] = {\n+\t[666] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_15d4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 2,\n@@ -11224,7 +14792,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[523] = {\n+\t[667] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1dd0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 3,\n@@ -11240,7 +14808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[524] = {\n+\t[668] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_14f4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 3,\n@@ -11257,7 +14825,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[525] = {\n+\t[669] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_70b0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 3,\n@@ -11274,7 +14842,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[526] = {\n+\t[670] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4854,\n \t.class_tid = 3,\n \t.hdr_sig_id = 3,\n@@ -11292,7 +14860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[527] = {\n+\t[671] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3dd4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 3,\n@@ -11309,7 +14877,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[528] = {\n+\t[672] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_34f8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 3,\n@@ -11327,7 +14895,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[529] = {\n+\t[673] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_09e8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 3,\n@@ -11345,7 +14913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[530] = {\n+\t[674] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_008c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 3,\n@@ -11364,7 +14932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[531] = {\n+\t[675] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_34e6,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11380,7 +14948,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[532] = {\n+\t[676] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0c02,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11397,7 +14965,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[533] = {\n+\t[677] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1c9e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11414,7 +14982,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[534] = {\n+\t[678] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_17ba,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11432,7 +15000,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[535] = {\n+\t[679] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_429e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11449,7 +15017,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[536] = {\n+\t[680] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5dba,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11467,7 +15035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[537] = {\n+\t[681] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2a16,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11485,7 +15053,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[538] = {\n+\t[682] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2532,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11504,7 +15072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[539] = {\n+\t[683] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2da2,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11521,7 +15089,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[540] = {\n+\t[684] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_24fe,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11539,7 +15107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[541] = {\n+\t[685] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_355a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11557,7 +15125,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[542] = {\n+\t[686] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0c76,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11576,7 +15144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[543] = {\n+\t[687] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_13e6,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11594,7 +15162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[544] = {\n+\t[688] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7276,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11613,7 +15181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[545] = {\n+\t[689] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_42d2,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11632,7 +15200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[546] = {\n+\t[690] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5dee,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -11652,7 +15220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[547] = {\n+\t[691] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_59de,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11668,7 +15236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[548] = {\n+\t[692] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_513a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11685,7 +15253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[549] = {\n+\t[693] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1c12,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11702,7 +15270,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[550] = {\n+\t[694] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_177e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11720,7 +15288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[551] = {\n+\t[695] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0e92,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11737,7 +15305,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[552] = {\n+\t[696] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_09fe,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11755,7 +15323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[553] = {\n+\t[697] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5c1a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11773,7 +15341,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[554] = {\n+\t[698] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5746,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11792,7 +15360,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[555] = {\n+\t[699] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_79da,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11809,7 +15377,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[556] = {\n+\t[700] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7106,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11827,7 +15395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[557] = {\n+\t[701] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3c1e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11845,7 +15413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[558] = {\n+\t[702] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_377a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11864,7 +15432,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[559] = {\n+\t[703] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2e9e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11882,7 +15450,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[560] = {\n+\t[704] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_29fa,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11901,7 +15469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[561] = {\n+\t[705] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_14d2,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11920,7 +15488,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[562] = {\n+\t[706] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7742,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -11940,7 +15508,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[563] = {\n+\t[707] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3706,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -11956,7 +15524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[564] = {\n+\t[708] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0fe2,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -11973,7 +15541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[565] = {\n+\t[709] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1f7e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -11990,7 +15558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[566] = {\n+\t[710] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_145a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -12008,7 +15576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[567] = {\n+\t[711] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_417e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -12025,7 +15593,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[568] = {\n+\t[712] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5e5a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -12043,7 +15611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[569] = {\n+\t[713] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_29f6,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -12061,7 +15629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[570] = {\n+\t[714] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_26d2,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -12080,7 +15648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[571] = {\n+\t[715] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2e42,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -12097,7 +15665,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[572] = {\n+\t[716] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_271e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -12115,7 +15683,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[573] = {\n+\t[717] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_36ba,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -12133,7 +15701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[574] = {\n+\t[718] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0f96,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -12152,7 +15720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[575] = {\n+\t[719] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1006,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -12170,7 +15738,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[576] = {\n+\t[720] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7196,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -12189,7 +15757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[577] = {\n+\t[721] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4132,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -12208,7 +15776,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[578] = {\n+\t[722] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5e0e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -12228,7 +15796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[579] = {\n+\t[723] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_59fe,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12244,7 +15812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[580] = {\n+\t[724] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_511a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12261,7 +15829,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[581] = {\n+\t[725] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1c32,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12278,7 +15846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[582] = {\n+\t[726] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_175e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12296,7 +15864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[583] = {\n+\t[727] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0eb2,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12313,7 +15881,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[584] = {\n+\t[728] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_09de,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12331,7 +15899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[585] = {\n+\t[729] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5c3a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12349,7 +15917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[586] = {\n+\t[730] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5766,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12368,7 +15936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[587] = {\n+\t[731] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_79fa,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12385,7 +15953,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[588] = {\n+\t[732] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7126,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12403,7 +15971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[589] = {\n+\t[733] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3c3e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12421,7 +15989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[590] = {\n+\t[734] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_375a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12440,7 +16008,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[591] = {\n+\t[735] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2ebe,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12458,7 +16026,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[592] = {\n+\t[736] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_29da,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12477,7 +16045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[593] = {\n+\t[737] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_14f2,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12496,7 +16064,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[594] = {\n+\t[738] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7762,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -12516,7 +16084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[595] = {\n+\t[739] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_19e8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12533,7 +16101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[596] = {\n+\t[740] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_110c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12551,7 +16119,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[597] = {\n+\t[741] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4d48,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12569,7 +16137,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[598] = {\n+\t[742] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_446c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12588,7 +16156,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[599] = {\n+\t[743] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0eac,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12606,7 +16174,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[600] = {\n+\t[744] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_09c0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12625,7 +16193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[601] = {\n+\t[745] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1ad0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12644,7 +16212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[602] = {\n+\t[746] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_15f4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12664,7 +16232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[603] = {\n+\t[747] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_39ec,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12682,7 +16250,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[604] = {\n+\t[748] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3100,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12701,7 +16269,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[605] = {\n+\t[749] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0210,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12720,7 +16288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[606] = {\n+\t[750] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1d34,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12740,7 +16308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[607] = {\n+\t[751] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2ea0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12759,7 +16327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[608] = {\n+\t[752] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_29c4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12779,7 +16347,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[609] = {\n+\t[753] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3ad4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12799,7 +16367,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[610] = {\n+\t[754] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_35e8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12820,7 +16388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[611] = {\n+\t[755] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5d80,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12838,7 +16406,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[612] = {\n+\t[756] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_54a4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12857,7 +16425,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[613] = {\n+\t[757] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_29b4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12876,7 +16444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[614] = {\n+\t[758] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_20c8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12896,7 +16464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[615] = {\n+\t[759] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7244,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12915,7 +16483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[616] = {\n+\t[760] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4d98,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12935,7 +16503,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[617] = {\n+\t[761] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5e68,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12955,7 +16523,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[618] = {\n+\t[762] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_598c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12976,7 +16544,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[619] = {\n+\t[763] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1248,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -12995,7 +16563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[620] = {\n+\t[764] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_74d8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -13015,7 +16583,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[621] = {\n+\t[765] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_49a8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -13035,7 +16603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[622] = {\n+\t[766] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_40cc,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -13056,7 +16624,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[623] = {\n+\t[767] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0b0c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -13076,7 +16644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[624] = {\n+\t[768] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0220,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -13097,7 +16665,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[625] = {\n+\t[769] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1730,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -13118,7 +16686,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[626] = {\n+\t[770] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7980,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -13140,7 +16708,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[627] = {\n+\t[771] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1db0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13157,7 +16725,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[628] = {\n+\t[772] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1494,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13175,7 +16743,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[629] = {\n+\t[773] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_70d0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13193,7 +16761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[630] = {\n+\t[774] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4834,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13212,7 +16780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[631] = {\n+\t[775] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3db4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13230,7 +16798,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[632] = {\n+\t[776] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3498,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13249,7 +16817,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[633] = {\n+\t[777] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0988,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13268,7 +16836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[634] = {\n+\t[778] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_00ec,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13288,7 +16856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[635] = {\n+\t[779] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3f44,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13306,7 +16874,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[636] = {\n+\t[780] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_36a8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13325,7 +16893,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[637] = {\n+\t[781] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0b58,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13344,7 +16912,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[638] = {\n+\t[782] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_02bc,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13364,7 +16932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[639] = {\n+\t[783] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5f48,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13383,7 +16951,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[640] = {\n+\t[784] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_56ac,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13403,7 +16971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[641] = {\n+\t[785] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2b5c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13423,7 +16991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[642] = {\n+\t[786] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2280,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13444,7 +17012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[643] = {\n+\t[787] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4000,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13462,7 +17030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[644] = {\n+\t[788] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5b64,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13481,7 +17049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[645] = {\n+\t[789] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2c14,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13500,7 +17068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[646] = {\n+\t[790] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2778,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13520,7 +17088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[647] = {\n+\t[791] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_18f8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13539,7 +17107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[648] = {\n+\t[792] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_13dc,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13559,7 +17127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[649] = {\n+\t[793] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4c18,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13579,7 +17147,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[650] = {\n+\t[794] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_477c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13600,7 +17168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[651] = {\n+\t[795] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1a88,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13619,7 +17187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[652] = {\n+\t[796] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_15ec,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13639,7 +17207,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[653] = {\n+\t[797] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4e28,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13659,7 +17227,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[654] = {\n+\t[798] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_490c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13680,7 +17248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[655] = {\n+\t[799] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3a8c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13700,7 +17268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[656] = {\n+\t[800] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_35f0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13721,7 +17289,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[657] = {\n+\t[801] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_06e0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13742,7 +17310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[658] = {\n+\t[802] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_01c4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -13764,7 +17332,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[659] = {\n+\t[803] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1a08,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -13781,7 +17349,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[660] = {\n+\t[804] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_12ec,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -13799,7 +17367,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[661] = {\n+\t[805] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4ea8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -13817,7 +17385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[662] = {\n+\t[806] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_478c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -13836,7 +17404,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[663] = {\n+\t[807] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0d4c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -13854,7 +17422,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[664] = {\n+\t[808] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0a20,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -13873,7 +17441,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[665] = {\n+\t[809] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1930,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -13892,7 +17460,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[666] = {\n+\t[810] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1614,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -13912,7 +17480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[667] = {\n+\t[811] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3a0c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -13930,7 +17498,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[668] = {\n+\t[812] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_32e0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -13949,7 +17517,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[669] = {\n+\t[813] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_01f0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -13968,7 +17536,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[670] = {\n+\t[814] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1ed4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -13988,7 +17556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[671] = {\n+\t[815] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2d40,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14007,7 +17575,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[672] = {\n+\t[816] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2a24,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14027,7 +17595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[673] = {\n+\t[817] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3934,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14047,7 +17615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[674] = {\n+\t[818] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3608,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14068,7 +17636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[675] = {\n+\t[819] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5e60,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14086,7 +17654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[676] = {\n+\t[820] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5744,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14105,7 +17673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[677] = {\n+\t[821] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2a54,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14124,7 +17692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[678] = {\n+\t[822] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2328,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14144,7 +17712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[679] = {\n+\t[823] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_71a4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14163,7 +17731,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[680] = {\n+\t[824] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4e78,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14183,7 +17751,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[681] = {\n+\t[825] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5d88,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14203,7 +17771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[682] = {\n+\t[826] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5a6c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14224,7 +17792,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[683] = {\n+\t[827] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_11a8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14243,7 +17811,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[684] = {\n+\t[828] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7738,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14263,7 +17831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[685] = {\n+\t[829] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4a48,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14283,7 +17851,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[686] = {\n+\t[830] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_432c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14304,7 +17872,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[687] = {\n+\t[831] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_08ec,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14324,7 +17892,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[688] = {\n+\t[832] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_01c0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14345,7 +17913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[689] = {\n+\t[833] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_14d0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14366,7 +17934,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[690] = {\n+\t[834] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7a60,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -14388,7 +17956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[691] = {\n+\t[835] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1d90,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14405,7 +17973,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[692] = {\n+\t[836] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_14b4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14423,7 +17991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[693] = {\n+\t[837] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_70f0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14441,7 +18009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[694] = {\n+\t[838] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4814,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14460,7 +18028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[695] = {\n+\t[839] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3d94,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14478,7 +18046,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[696] = {\n+\t[840] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_34b8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14497,7 +18065,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[697] = {\n+\t[841] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_09a8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14516,7 +18084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[698] = {\n+\t[842] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_00cc,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14536,7 +18104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[699] = {\n+\t[843] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3f64,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14554,7 +18122,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[700] = {\n+\t[844] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3688,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14573,7 +18141,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[701] = {\n+\t[845] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0b78,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14592,7 +18160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[702] = {\n+\t[846] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_029c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14612,7 +18180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[703] = {\n+\t[847] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5f68,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14631,7 +18199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[704] = {\n+\t[848] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_568c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14651,7 +18219,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[705] = {\n+\t[849] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2b7c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14671,7 +18239,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[706] = {\n+\t[850] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_22a0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14692,7 +18260,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[707] = {\n+\t[851] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4020,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14710,7 +18278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[708] = {\n+\t[852] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5b44,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14729,7 +18297,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[709] = {\n+\t[853] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2c34,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14748,7 +18316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[710] = {\n+\t[854] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2758,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14768,7 +18336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[711] = {\n+\t[855] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_18d8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14787,7 +18355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[712] = {\n+\t[856] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_13fc,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14807,7 +18375,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[713] = {\n+\t[857] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4c38,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14827,7 +18395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[714] = {\n+\t[858] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_475c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14848,7 +18416,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[715] = {\n+\t[859] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1aa8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14867,7 +18435,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[716] = {\n+\t[860] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_15cc,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14887,7 +18455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[717] = {\n+\t[861] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4e08,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14907,7 +18475,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[718] = {\n+\t[862] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_492c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14928,7 +18496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[719] = {\n+\t[863] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3aac,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14948,7 +18516,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[720] = {\n+\t[864] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_35d0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14969,7 +18537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[721] = {\n+\t[865] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_06c0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -14990,7 +18558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[722] = {\n+\t[866] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_01e4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -15012,7 +18580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[723] = {\n+\t[867] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4d32,\n \t.class_tid = 3,\n \t.hdr_sig_id = 0,\n@@ -15026,7 +18594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[724] = {\n+\t[868] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_54aa,\n \t.class_tid = 3,\n \t.hdr_sig_id = 0,\n@@ -15041,7 +18609,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[725] = {\n+\t[869] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0686,\n \t.class_tid = 3,\n \t.hdr_sig_id = 1,\n@@ -15055,7 +18623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[726] = {\n+\t[870] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_540e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 1,\n@@ -15070,7 +18638,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[727] = {\n+\t[871] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2e3c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 2,\n@@ -15085,7 +18653,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[728] = {\n+\t[872] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3a20,\n \t.class_tid = 3,\n \t.hdr_sig_id = 2,\n@@ -15101,7 +18669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[729] = {\n+\t[873] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_46f0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 2,\n@@ -15117,7 +18685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[730] = {\n+\t[874] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_52e4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 2,\n@@ -15134,7 +18702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[731] = {\n+\t[875] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_55e4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 3,\n@@ -15149,7 +18717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[732] = {\n+\t[876] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_21f8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 3,\n@@ -15165,7 +18733,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[733] = {\n+\t[877] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_75e8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 3,\n@@ -15181,7 +18749,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[734] = {\n+\t[878] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_41fc,\n \t.class_tid = 3,\n \t.hdr_sig_id = 3,\n@@ -15198,7 +18766,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[735] = {\n+\t[879] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4d12,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -15213,7 +18781,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[736] = {\n+\t[880] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_548a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -15229,7 +18797,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[737] = {\n+\t[881] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3356,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -15245,7 +18813,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[738] = {\n+\t[882] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1ace,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -15262,7 +18830,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[739] = {\n+\t[883] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1a9a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -15278,7 +18846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[740] = {\n+\t[884] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4d46,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -15295,7 +18863,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[741] = {\n+\t[885] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2812,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -15312,7 +18880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[742] = {\n+\t[886] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_338a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -15330,7 +18898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[743] = {\n+\t[887] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_06e6,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -15345,7 +18913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[744] = {\n+\t[888] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_546e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -15361,7 +18929,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[745] = {\n+\t[889] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_46ee,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -15377,7 +18945,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[746] = {\n+\t[890] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0d22,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -15394,7 +18962,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[747] = {\n+\t[891] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_26e2,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -15410,7 +18978,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[748] = {\n+\t[892] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_746a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -15427,7 +18995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[749] = {\n+\t[893] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1fa6,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -15444,7 +19012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[750] = {\n+\t[894] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2d2e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -15462,7 +19030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[751] = {\n+\t[895] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4ef2,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -15477,7 +19045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[752] = {\n+\t[896] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_576a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -15493,7 +19061,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[753] = {\n+\t[897] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_30b6,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -15509,7 +19077,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[754] = {\n+\t[898] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_192e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -15526,7 +19094,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[755] = {\n+\t[899] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_197a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -15542,7 +19110,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[756] = {\n+\t[900] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4ea6,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -15559,7 +19127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[757] = {\n+\t[901] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2bf2,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -15576,7 +19144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[758] = {\n+\t[902] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_306a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -15594,7 +19162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[759] = {\n+\t[903] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_06c6,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -15609,7 +19177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[760] = {\n+\t[904] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_544e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -15625,7 +19193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[761] = {\n+\t[905] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_46ce,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -15641,7 +19209,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[762] = {\n+\t[906] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0d02,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -15658,7 +19226,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[763] = {\n+\t[907] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_26c2,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -15674,7 +19242,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[764] = {\n+\t[908] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_744a,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -15691,7 +19259,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[765] = {\n+\t[909] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1f86,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -15708,7 +19276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[766] = {\n+\t[910] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2d0e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -15726,7 +19294,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[767] = {\n+\t[911] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2e1c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15742,7 +19310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[768] = {\n+\t[912] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3a00,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15759,7 +19327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[769] = {\n+\t[913] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_46d0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15776,7 +19344,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[770] = {\n+\t[914] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_52c4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15794,7 +19362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[771] = {\n+\t[915] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4e10,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15811,7 +19379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[772] = {\n+\t[916] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5a04,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15829,7 +19397,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[773] = {\n+\t[917] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1f98,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15847,7 +19415,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[774] = {\n+\t[918] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_72f8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15866,7 +19434,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[775] = {\n+\t[919] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0a78,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15883,7 +19451,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[776] = {\n+\t[920] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_166c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15901,7 +19469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[777] = {\n+\t[921] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_233c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15919,7 +19487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[778] = {\n+\t[922] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0f20,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15938,7 +19506,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[779] = {\n+\t[923] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2a7c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15956,7 +19524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[780] = {\n+\t[924] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3660,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15975,7 +19543,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[781] = {\n+\t[925] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4330,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -15994,7 +19562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[782] = {\n+\t[926] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2f24,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -16014,7 +19582,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[783] = {\n+\t[927] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5584,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16030,7 +19598,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[784] = {\n+\t[928] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2198,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16047,7 +19615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[785] = {\n+\t[929] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7588,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16064,7 +19632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[786] = {\n+\t[930] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_419c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16082,7 +19650,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[787] = {\n+\t[931] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7758,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16099,7 +19667,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[788] = {\n+\t[932] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_43ac,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16117,7 +19685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[789] = {\n+\t[933] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0c10,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16135,7 +19703,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[790] = {\n+\t[934] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1864,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16154,7 +19722,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[791] = {\n+\t[935] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_30c8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16171,7 +19739,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[792] = {\n+\t[936] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1cdc,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16189,7 +19757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[793] = {\n+\t[937] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_50cc,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16207,7 +19775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[794] = {\n+\t[938] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3d20,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16226,7 +19794,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[795] = {\n+\t[939] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_529c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16244,7 +19812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[796] = {\n+\t[940] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3ef0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16263,7 +19831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[797] = {\n+\t[941] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_72e0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16282,7 +19850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[798] = {\n+\t[942] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5ef4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -16302,7 +19870,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[799] = {\n+\t[943] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2dfc,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16318,7 +19886,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[800] = {\n+\t[944] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_39e0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16335,7 +19903,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[801] = {\n+\t[945] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4530,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16352,7 +19920,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[802] = {\n+\t[946] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5124,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16370,7 +19938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[803] = {\n+\t[947] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4df0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16387,7 +19955,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[804] = {\n+\t[948] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_59e4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16405,7 +19973,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[805] = {\n+\t[949] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1c78,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16423,7 +19991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[806] = {\n+\t[950] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7118,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16442,7 +20010,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[807] = {\n+\t[951] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0998,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16459,7 +20027,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[808] = {\n+\t[952] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_158c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16477,7 +20045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[809] = {\n+\t[953] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_20dc,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16495,7 +20063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[810] = {\n+\t[954] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0cc0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16514,7 +20082,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[811] = {\n+\t[955] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_299c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16532,7 +20100,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[812] = {\n+\t[956] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3580,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16551,7 +20119,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[813] = {\n+\t[957] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_40d0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16570,7 +20138,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[814] = {\n+\t[958] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2cc4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -16590,7 +20158,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[815] = {\n+\t[959] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_55a4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16606,7 +20174,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[816] = {\n+\t[960] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_21b8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16623,7 +20191,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[817] = {\n+\t[961] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_75a8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16640,7 +20208,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[818] = {\n+\t[962] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_41bc,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16658,7 +20226,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[819] = {\n+\t[963] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7778,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16675,7 +20243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[820] = {\n+\t[964] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_438c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16693,7 +20261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[821] = {\n+\t[965] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0c30,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16711,7 +20279,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[822] = {\n+\t[966] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1844,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16730,7 +20298,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[823] = {\n+\t[967] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_30e8,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16747,7 +20315,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[824] = {\n+\t[968] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1cfc,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16765,7 +20333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[825] = {\n+\t[969] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_50ec,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16783,7 +20351,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[826] = {\n+\t[970] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3d00,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16802,7 +20370,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[827] = {\n+\t[971] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_52bc,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16820,7 +20388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[828] = {\n+\t[972] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3ed0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16839,7 +20407,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[829] = {\n+\t[973] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_72c0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16858,7 +20426,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[830] = {\n+\t[974] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5ed4,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -16878,7 +20446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[831] = {\n+\t[975] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3866,\n \t.class_tid = 3,\n \t.hdr_sig_id = 0,\n@@ -16893,7 +20461,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC }\n \t},\n-\t[832] = {\n+\t[976] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_381e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 1,\n@@ -16908,7 +20476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC }\n \t},\n-\t[833] = {\n+\t[977] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3860,\n \t.class_tid = 3,\n \t.hdr_sig_id = 2,\n@@ -16924,7 +20492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC }\n \t},\n-\t[834] = {\n+\t[978] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0454,\n \t.class_tid = 3,\n \t.hdr_sig_id = 2,\n@@ -16941,7 +20509,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID }\n \t},\n-\t[835] = {\n+\t[979] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3818,\n \t.class_tid = 3,\n \t.hdr_sig_id = 3,\n@@ -16957,7 +20525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC }\n \t},\n-\t[836] = {\n+\t[980] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_042c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 3,\n@@ -16974,7 +20542,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID }\n \t},\n-\t[837] = {\n+\t[981] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3846,\n \t.class_tid = 3,\n \t.hdr_sig_id = 4,\n@@ -16990,7 +20558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC }\n \t},\n-\t[838] = {\n+\t[982] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_387e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 5,\n@@ -17006,7 +20574,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC }\n \t},\n-\t[839] = {\n+\t[983] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3ba6,\n \t.class_tid = 3,\n \t.hdr_sig_id = 6,\n@@ -17022,7 +20590,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC }\n \t},\n-\t[840] = {\n+\t[984] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_385e,\n \t.class_tid = 3,\n \t.hdr_sig_id = 7,\n@@ -17038,7 +20606,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC }\n \t},\n-\t[841] = {\n+\t[985] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3840,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -17055,7 +20623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC }\n \t},\n-\t[842] = {\n+\t[986] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0474,\n \t.class_tid = 3,\n \t.hdr_sig_id = 8,\n@@ -17073,7 +20641,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID }\n \t},\n-\t[843] = {\n+\t[987] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3878,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -17090,7 +20658,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC }\n \t},\n-\t[844] = {\n+\t[988] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_044c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 9,\n@@ -17108,7 +20676,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID }\n \t},\n-\t[845] = {\n+\t[989] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3ba0,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -17125,7 +20693,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC }\n \t},\n-\t[846] = {\n+\t[990] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0794,\n \t.class_tid = 3,\n \t.hdr_sig_id = 10,\n@@ -17143,7 +20711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID }\n \t},\n-\t[847] = {\n+\t[991] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3858,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\n@@ -17160,7 +20728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC }\n \t},\n-\t[848] = {\n+\t[992] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_046c,\n \t.class_tid = 3,\n \t.hdr_sig_id = 11,\ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h\nindex 84e3d92f41..c016e1940a 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Tue Jul 13 12:36:40 2021 */\n+/* date: Fri Aug 20 17:59:14 2021 */\n \n #ifndef ULP_TEMPLATE_DB_H_\n #define ULP_TEMPLATE_DB_H_\n@@ -11,14 +11,14 @@\n #define BNXT_ULP_REGFILE_MAX_SZ 42\n #define BNXT_ULP_MAX_NUM_DEVICES 4\n #define BNXT_ULP_LOG2_MAX_NUM_DEV 2\n-#define BNXT_ULP_GEN_TBL_MAX_SZ 12\n-#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 32768\n-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 849\n+#define BNXT_ULP_GEN_TBL_MAX_SZ 16\n+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 65536\n+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 993\n #define BNXT_ULP_CLASS_HID_LOW_PRIME 6701\n #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907\n-#define BNXT_ULP_CLASS_HID_SHFTR 24\n-#define BNXT_ULP_CLASS_HID_SHFTL 24\n-#define BNXT_ULP_CLASS_HID_MASK 32767\n+#define BNXT_ULP_CLASS_HID_SHFTR 28\n+#define BNXT_ULP_CLASS_HID_SHFTL 28\n+#define BNXT_ULP_CLASS_HID_MASK 65535\n #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048\n #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86\n #define BNXT_ULP_ACT_HID_LOW_PRIME 7919\n@@ -27,10 +27,10 @@\n #define BNXT_ULP_ACT_HID_SHFTL 26\n #define BNXT_ULP_ACT_HID_MASK 2047\n #define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8\n-#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 62\n+#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110\n #define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50\n-#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 206\n-#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6\n+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278\n+#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8\n #define BNXT_ULP_COND_GOTO_REJECT 1023\n #define BNXT_ULP_COND_GOTO_RF 0x10000\n #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7\n@@ -44,10 +44,10 @@\n #define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618\n #define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49\n #define ULP_THOR_CLASS_TMPL_LIST_SIZE 6\n-#define ULP_THOR_CLASS_TBL_LIST_SIZE 114\n-#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2305\n-#define ULP_THOR_CLASS_IDENT_LIST_SIZE 39\n-#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1192\n+#define ULP_THOR_CLASS_TBL_LIST_SIZE 116\n+#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2323\n+#define ULP_THOR_CLASS_IDENT_LIST_SIZE 38\n+#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313\n #define ULP_THOR_CLASS_COND_LIST_SIZE 55\n #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7\n #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35\n@@ -56,11 +56,11 @@\n #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536\n #define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39\n #define ULP_THOR_ACT_TMPL_LIST_SIZE 7\n-#define ULP_THOR_ACT_TBL_LIST_SIZE 28\n-#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 2\n-#define ULP_THOR_ACT_IDENT_LIST_SIZE 1\n-#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 479\n-#define ULP_THOR_ACT_COND_LIST_SIZE 20\n+#define ULP_THOR_ACT_TBL_LIST_SIZE 36\n+#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16\n+#define ULP_THOR_ACT_IDENT_LIST_SIZE 3\n+#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 505\n+#define ULP_THOR_ACT_COND_LIST_SIZE 27\n \n enum bnxt_ulp_act_bit {\n \tBNXT_ULP_ACT_BIT_MARK                = 0x0000000000000001,\n@@ -158,56 +158,60 @@ enum bnxt_ulp_cf_idx {\n \tBNXT_ULP_CF_IDX_O_L4_DST_PORT = 18,\n \tBNXT_ULP_CF_IDX_I_L4_SRC_PORT = 19,\n \tBNXT_ULP_CF_IDX_I_L4_DST_PORT = 20,\n-\tBNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT = 21,\n-\tBNXT_ULP_CF_IDX_O_L4_FB_DST_PORT = 22,\n-\tBNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT = 23,\n-\tBNXT_ULP_CF_IDX_I_L4_FB_DST_PORT = 24,\n-\tBNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID = 25,\n-\tBNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID = 26,\n-\tBNXT_ULP_CF_IDX_O_L3_PROTO_ID = 27,\n-\tBNXT_ULP_CF_IDX_I_L3_PROTO_ID = 28,\n-\tBNXT_ULP_CF_IDX_DEV_PORT_ID = 29,\n-\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 30,\n-\tBNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 31,\n-\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 32,\n-\tBNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 33,\n-\tBNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 34,\n-\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF = 35,\n-\tBNXT_ULP_CF_IDX_VF_FUNC_SPIF = 36,\n-\tBNXT_ULP_CF_IDX_VF_FUNC_PARIF = 37,\n-\tBNXT_ULP_CF_IDX_VF_FUNC_VNIC = 38,\n-\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF = 39,\n-\tBNXT_ULP_CF_IDX_PHY_PORT_SPIF = 40,\n-\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF = 41,\n-\tBNXT_ULP_CF_IDX_PHY_PORT_VPORT = 42,\n-\tBNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 43,\n-\tBNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 44,\n-\tBNXT_ULP_CF_IDX_ACT_DEC_TTL = 45,\n-\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 46,\n-\tBNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 47,\n-\tBNXT_ULP_CF_IDX_ACT_PORT_TYPE = 48,\n-\tBNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 49,\n-\tBNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 50,\n-\tBNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 51,\n-\tBNXT_ULP_CF_IDX_VF_TO_VF = 52,\n-\tBNXT_ULP_CF_IDX_L3_HDR_CNT = 53,\n-\tBNXT_ULP_CF_IDX_L4_HDR_CNT = 54,\n-\tBNXT_ULP_CF_IDX_VFR_MODE = 55,\n-\tBNXT_ULP_CF_IDX_L3_TUN = 56,\n-\tBNXT_ULP_CF_IDX_L3_TUN_DECAP = 57,\n-\tBNXT_ULP_CF_IDX_FID = 58,\n-\tBNXT_ULP_CF_IDX_HDR_SIG_ID = 59,\n-\tBNXT_ULP_CF_IDX_FLOW_SIG_ID = 60,\n-\tBNXT_ULP_CF_IDX_WC_MATCH = 61,\n-\tBNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62,\n-\tBNXT_ULP_CF_IDX_TUNNEL_ID = 63,\n-\tBNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,\n-\tBNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,\n-\tBNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 66,\n-\tBNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 67,\n-\tBNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 68,\n-\tBNXT_ULP_CF_IDX_II_VLAN_FB_VID = 69,\n-\tBNXT_ULP_CF_IDX_LAST = 70\n+\tBNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK = 21,\n+\tBNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK = 22,\n+\tBNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK = 23,\n+\tBNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK = 24,\n+\tBNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT = 25,\n+\tBNXT_ULP_CF_IDX_O_L4_FB_DST_PORT = 26,\n+\tBNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT = 27,\n+\tBNXT_ULP_CF_IDX_I_L4_FB_DST_PORT = 28,\n+\tBNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID = 29,\n+\tBNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID = 30,\n+\tBNXT_ULP_CF_IDX_O_L3_PROTO_ID = 31,\n+\tBNXT_ULP_CF_IDX_I_L3_PROTO_ID = 32,\n+\tBNXT_ULP_CF_IDX_DEV_PORT_ID = 33,\n+\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 34,\n+\tBNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 35,\n+\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 36,\n+\tBNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 37,\n+\tBNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 38,\n+\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF = 39,\n+\tBNXT_ULP_CF_IDX_VF_FUNC_SPIF = 40,\n+\tBNXT_ULP_CF_IDX_VF_FUNC_PARIF = 41,\n+\tBNXT_ULP_CF_IDX_VF_FUNC_VNIC = 42,\n+\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF = 43,\n+\tBNXT_ULP_CF_IDX_PHY_PORT_SPIF = 44,\n+\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF = 45,\n+\tBNXT_ULP_CF_IDX_PHY_PORT_VPORT = 46,\n+\tBNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 47,\n+\tBNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 48,\n+\tBNXT_ULP_CF_IDX_ACT_DEC_TTL = 49,\n+\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 50,\n+\tBNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 51,\n+\tBNXT_ULP_CF_IDX_ACT_PORT_TYPE = 52,\n+\tBNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 53,\n+\tBNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 54,\n+\tBNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 55,\n+\tBNXT_ULP_CF_IDX_VF_TO_VF = 56,\n+\tBNXT_ULP_CF_IDX_L3_HDR_CNT = 57,\n+\tBNXT_ULP_CF_IDX_L4_HDR_CNT = 58,\n+\tBNXT_ULP_CF_IDX_VFR_MODE = 59,\n+\tBNXT_ULP_CF_IDX_L3_TUN = 60,\n+\tBNXT_ULP_CF_IDX_L3_TUN_DECAP = 61,\n+\tBNXT_ULP_CF_IDX_FID = 62,\n+\tBNXT_ULP_CF_IDX_HDR_SIG_ID = 63,\n+\tBNXT_ULP_CF_IDX_FLOW_SIG_ID = 64,\n+\tBNXT_ULP_CF_IDX_WC_MATCH = 65,\n+\tBNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 66,\n+\tBNXT_ULP_CF_IDX_TUNNEL_ID = 67,\n+\tBNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 68,\n+\tBNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 69,\n+\tBNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 70,\n+\tBNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 71,\n+\tBNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72,\n+\tBNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73,\n+\tBNXT_ULP_CF_IDX_LAST = 74\n };\n \n enum bnxt_ulp_cond_list_opc {\n@@ -394,38 +398,49 @@ enum bnxt_ulp_glb_rf_idx {\n \tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 = 9,\n \tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 = 10,\n \tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 = 11,\n-\tBNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 12,\n-\tBNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 13,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6 = 12,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7 = 13,\n \tBNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 14,\n \tBNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 15,\n \tBNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 = 16,\n \tBNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3 = 17,\n \tBNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 = 18,\n-\tBNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 19,\n-\tBNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 20,\n-\tBNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 21,\n-\tBNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 22,\n-\tBNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 23,\n-\tBNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 24,\n-\tBNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 25,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 26,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 27,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 28,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 29,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 30,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 31,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 32,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 33,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 34,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 35,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 36,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 37,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 38,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 39,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 40,\n-\tBNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 41,\n-\tBNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 42,\n-\tBNXT_ULP_GLB_RF_IDX_LAST = 43\n+\tBNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 19,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 20,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2 = 21,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3 = 22,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4 = 23,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5 = 24,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6 = 25,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7 = 26,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 27,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 28,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2 = 29,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3 = 30,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_4 = 31,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 32,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 33,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 34,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 35,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 36,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 37,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 38,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 39,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 40,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 41,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 42,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 43,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 44,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 45,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 46,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 47,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 48,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 49,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 50,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 51,\n+\tBNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 52,\n+\tBNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 53,\n+\tBNXT_ULP_GLB_RF_IDX_LAST = 54\n };\n \n enum bnxt_ulp_hdr_type {\n@@ -608,7 +623,9 @@ enum bnxt_ulp_resource_sub_type {\n \tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2,\n \tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3,\n \tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4,\n-\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5\n+\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5,\n+\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE = 6,\n+\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7\n };\n \n enum bnxt_ulp_act_prop_sz {\n@@ -1526,166 +1543,310 @@ enum bnxt_ulp_class_hid {\n \tBNXT_ULP_CLASS_HID_315d = 0x315d,\n \tBNXT_ULP_CLASS_HID_3612 = 0x3612,\n \tBNXT_ULP_CLASS_HID_66da = 0x66da,\n-\tBNXT_ULP_CLASS_HID_6165 = 0x6165,\n-\tBNXT_ULP_CLASS_HID_2aa1 = 0x2aa1,\n-\tBNXT_ULP_CLASS_HID_09cd = 0x09cd,\n-\tBNXT_ULP_CLASS_HID_3845 = 0x3845,\n-\tBNXT_ULP_CLASS_HID_11e9 = 0x11e9,\n-\tBNXT_ULP_CLASS_HID_4361 = 0x4361,\n-\tBNXT_ULP_CLASS_HID_218d = 0x218d,\n-\tBNXT_ULP_CLASS_HID_5105 = 0x5105,\n-\tBNXT_ULP_CLASS_HID_0c89 = 0x0c89,\n-\tBNXT_ULP_CLASS_HID_3e81 = 0x3e81,\n-\tBNXT_ULP_CLASS_HID_1dad = 0x1dad,\n-\tBNXT_ULP_CLASS_HID_4ca5 = 0x4ca5,\n-\tBNXT_ULP_CLASS_HID_25c9 = 0x25c9,\n-\tBNXT_ULP_CLASS_HID_57c1 = 0x57c1,\n-\tBNXT_ULP_CLASS_HID_33ed = 0x33ed,\n-\tBNXT_ULP_CLASS_HID_65e5 = 0x65e5,\n-\tBNXT_ULP_CLASS_HID_6dd9 = 0x6dd9,\n-\tBNXT_ULP_CLASS_HID_261d = 0x261d,\n-\tBNXT_ULP_CLASS_HID_0571 = 0x0571,\n-\tBNXT_ULP_CLASS_HID_34f9 = 0x34f9,\n-\tBNXT_ULP_CLASS_HID_1d55 = 0x1d55,\n-\tBNXT_ULP_CLASS_HID_4fdd = 0x4fdd,\n-\tBNXT_ULP_CLASS_HID_2d31 = 0x2d31,\n-\tBNXT_ULP_CLASS_HID_5db9 = 0x5db9,\n-\tBNXT_ULP_CLASS_HID_0035 = 0x0035,\n-\tBNXT_ULP_CLASS_HID_323d = 0x323d,\n-\tBNXT_ULP_CLASS_HID_1111 = 0x1111,\n-\tBNXT_ULP_CLASS_HID_4019 = 0x4019,\n-\tBNXT_ULP_CLASS_HID_2975 = 0x2975,\n-\tBNXT_ULP_CLASS_HID_5b7d = 0x5b7d,\n-\tBNXT_ULP_CLASS_HID_3f51 = 0x3f51,\n-\tBNXT_ULP_CLASS_HID_6959 = 0x6959,\n-\tBNXT_ULP_CLASS_HID_0e85 = 0x0e85,\n-\tBNXT_ULP_CLASS_HID_380d = 0x380d,\n-\tBNXT_ULP_CLASS_HID_1f21 = 0x1f21,\n-\tBNXT_ULP_CLASS_HID_4ea9 = 0x4ea9,\n-\tBNXT_ULP_CLASS_HID_1705 = 0x1705,\n-\tBNXT_ULP_CLASS_HID_418d = 0x418d,\n-\tBNXT_ULP_CLASS_HID_2721 = 0x2721,\n-\tBNXT_ULP_CLASS_HID_57a9 = 0x57a9,\n-\tBNXT_ULP_CLASS_HID_1a25 = 0x1a25,\n-\tBNXT_ULP_CLASS_HID_342d = 0x342d,\n-\tBNXT_ULP_CLASS_HID_2b01 = 0x2b01,\n-\tBNXT_ULP_CLASS_HID_5a09 = 0x5a09,\n-\tBNXT_ULP_CLASS_HID_2325 = 0x2325,\n-\tBNXT_ULP_CLASS_HID_5d2d = 0x5d2d,\n-\tBNXT_ULP_CLASS_HID_3101 = 0x3101,\n-\tBNXT_ULP_CLASS_HID_6309 = 0x6309,\n-\tBNXT_ULP_CLASS_HID_0bad = 0x0bad,\n-\tBNXT_ULP_CLASS_HID_2535 = 0x2535,\n-\tBNXT_ULP_CLASS_HID_1869 = 0x1869,\n-\tBNXT_ULP_CLASS_HID_4bf1 = 0x4bf1,\n-\tBNXT_ULP_CLASS_HID_136d = 0x136d,\n-\tBNXT_ULP_CLASS_HID_43f5 = 0x43f5,\n-\tBNXT_ULP_CLASS_HID_2129 = 0x2129,\n-\tBNXT_ULP_CLASS_HID_53b1 = 0x53b1,\n-\tBNXT_ULP_CLASS_HID_072d = 0x072d,\n-\tBNXT_ULP_CLASS_HID_3135 = 0x3135,\n-\tBNXT_ULP_CLASS_HID_1429 = 0x1429,\n-\tBNXT_ULP_CLASS_HID_4731 = 0x4731,\n-\tBNXT_ULP_CLASS_HID_2f6d = 0x2f6d,\n-\tBNXT_ULP_CLASS_HID_5f75 = 0x5f75,\n-\tBNXT_ULP_CLASS_HID_3d69 = 0x3d69,\n-\tBNXT_ULP_CLASS_HID_6f71 = 0x6f71,\n-\tBNXT_ULP_CLASS_HID_0dbd = 0x0dbd,\n-\tBNXT_ULP_CLASS_HID_3f25 = 0x3f25,\n-\tBNXT_ULP_CLASS_HID_1239 = 0x1239,\n-\tBNXT_ULP_CLASS_HID_4da1 = 0x4da1,\n-\tBNXT_ULP_CLASS_HID_153d = 0x153d,\n-\tBNXT_ULP_CLASS_HID_45a5 = 0x45a5,\n-\tBNXT_ULP_CLASS_HID_3bb9 = 0x3bb9,\n-\tBNXT_ULP_CLASS_HID_55a1 = 0x55a1,\n-\tBNXT_ULP_CLASS_HID_193d = 0x193d,\n-\tBNXT_ULP_CLASS_HID_4b25 = 0x4b25,\n-\tBNXT_ULP_CLASS_HID_2e39 = 0x2e39,\n-\tBNXT_ULP_CLASS_HID_5921 = 0x5921,\n-\tBNXT_ULP_CLASS_HID_213d = 0x213d,\n-\tBNXT_ULP_CLASS_HID_5125 = 0x5125,\n-\tBNXT_ULP_CLASS_HID_3739 = 0x3739,\n-\tBNXT_ULP_CLASS_HID_093d = 0x093d,\n-\tBNXT_ULP_CLASS_HID_684d = 0x684d,\n-\tBNXT_ULP_CLASS_HID_2389 = 0x2389,\n-\tBNXT_ULP_CLASS_HID_00e5 = 0x00e5,\n-\tBNXT_ULP_CLASS_HID_316d = 0x316d,\n-\tBNXT_ULP_CLASS_HID_18c1 = 0x18c1,\n-\tBNXT_ULP_CLASS_HID_4a49 = 0x4a49,\n-\tBNXT_ULP_CLASS_HID_28a5 = 0x28a5,\n-\tBNXT_ULP_CLASS_HID_582d = 0x582d,\n-\tBNXT_ULP_CLASS_HID_05a1 = 0x05a1,\n-\tBNXT_ULP_CLASS_HID_37a9 = 0x37a9,\n-\tBNXT_ULP_CLASS_HID_1485 = 0x1485,\n-\tBNXT_ULP_CLASS_HID_458d = 0x458d,\n-\tBNXT_ULP_CLASS_HID_2ce1 = 0x2ce1,\n-\tBNXT_ULP_CLASS_HID_5ee9 = 0x5ee9,\n-\tBNXT_ULP_CLASS_HID_3ac5 = 0x3ac5,\n-\tBNXT_ULP_CLASS_HID_6ccd = 0x6ccd,\n-\tBNXT_ULP_CLASS_HID_0b11 = 0x0b11,\n-\tBNXT_ULP_CLASS_HID_3d99 = 0x3d99,\n-\tBNXT_ULP_CLASS_HID_1ab5 = 0x1ab5,\n-\tBNXT_ULP_CLASS_HID_4b3d = 0x4b3d,\n-\tBNXT_ULP_CLASS_HID_1291 = 0x1291,\n-\tBNXT_ULP_CLASS_HID_4419 = 0x4419,\n-\tBNXT_ULP_CLASS_HID_22b5 = 0x22b5,\n-\tBNXT_ULP_CLASS_HID_523d = 0x523d,\n-\tBNXT_ULP_CLASS_HID_1fb1 = 0x1fb1,\n-\tBNXT_ULP_CLASS_HID_31b9 = 0x31b9,\n-\tBNXT_ULP_CLASS_HID_2e95 = 0x2e95,\n-\tBNXT_ULP_CLASS_HID_5f9d = 0x5f9d,\n-\tBNXT_ULP_CLASS_HID_26b1 = 0x26b1,\n-\tBNXT_ULP_CLASS_HID_58b9 = 0x58b9,\n-\tBNXT_ULP_CLASS_HID_3495 = 0x3495,\n-\tBNXT_ULP_CLASS_HID_669d = 0x669d,\n-\tBNXT_ULP_CLASS_HID_0e39 = 0x0e39,\n-\tBNXT_ULP_CLASS_HID_20a1 = 0x20a1,\n-\tBNXT_ULP_CLASS_HID_1dfd = 0x1dfd,\n-\tBNXT_ULP_CLASS_HID_4e65 = 0x4e65,\n-\tBNXT_ULP_CLASS_HID_16f9 = 0x16f9,\n-\tBNXT_ULP_CLASS_HID_4661 = 0x4661,\n-\tBNXT_ULP_CLASS_HID_24bd = 0x24bd,\n-\tBNXT_ULP_CLASS_HID_5625 = 0x5625,\n-\tBNXT_ULP_CLASS_HID_02b9 = 0x02b9,\n-\tBNXT_ULP_CLASS_HID_34a1 = 0x34a1,\n-\tBNXT_ULP_CLASS_HID_11bd = 0x11bd,\n-\tBNXT_ULP_CLASS_HID_42a5 = 0x42a5,\n-\tBNXT_ULP_CLASS_HID_2af9 = 0x2af9,\n-\tBNXT_ULP_CLASS_HID_5ae1 = 0x5ae1,\n-\tBNXT_ULP_CLASS_HID_38fd = 0x38fd,\n-\tBNXT_ULP_CLASS_HID_6ae5 = 0x6ae5,\n-\tBNXT_ULP_CLASS_HID_0829 = 0x0829,\n-\tBNXT_ULP_CLASS_HID_3ab1 = 0x3ab1,\n-\tBNXT_ULP_CLASS_HID_17ad = 0x17ad,\n-\tBNXT_ULP_CLASS_HID_4835 = 0x4835,\n-\tBNXT_ULP_CLASS_HID_10a9 = 0x10a9,\n-\tBNXT_ULP_CLASS_HID_4031 = 0x4031,\n-\tBNXT_ULP_CLASS_HID_3e2d = 0x3e2d,\n-\tBNXT_ULP_CLASS_HID_5035 = 0x5035,\n-\tBNXT_ULP_CLASS_HID_1ca9 = 0x1ca9,\n-\tBNXT_ULP_CLASS_HID_4eb1 = 0x4eb1,\n-\tBNXT_ULP_CLASS_HID_2bad = 0x2bad,\n-\tBNXT_ULP_CLASS_HID_5cb5 = 0x5cb5,\n-\tBNXT_ULP_CLASS_HID_24a9 = 0x24a9,\n-\tBNXT_ULP_CLASS_HID_54b1 = 0x54b1,\n-\tBNXT_ULP_CLASS_HID_32ad = 0x32ad,\n-\tBNXT_ULP_CLASS_HID_0ca9 = 0x0ca9,\n-\tBNXT_ULP_CLASS_HID_7f35 = 0x7f35,\n-\tBNXT_ULP_CLASS_HID_34f1 = 0x34f1,\n-\tBNXT_ULP_CLASS_HID_179d = 0x179d,\n-\tBNXT_ULP_CLASS_HID_2615 = 0x2615,\n-\tBNXT_ULP_CLASS_HID_0fb9 = 0x0fb9,\n-\tBNXT_ULP_CLASS_HID_5d31 = 0x5d31,\n-\tBNXT_ULP_CLASS_HID_3fdd = 0x3fdd,\n-\tBNXT_ULP_CLASS_HID_4f55 = 0x4f55,\n-\tBNXT_ULP_CLASS_HID_12d9 = 0x12d9,\n-\tBNXT_ULP_CLASS_HID_20d1 = 0x20d1,\n-\tBNXT_ULP_CLASS_HID_03fd = 0x03fd,\n-\tBNXT_ULP_CLASS_HID_52f5 = 0x52f5,\n-\tBNXT_ULP_CLASS_HID_3b99 = 0x3b99,\n-\tBNXT_ULP_CLASS_HID_4991 = 0x4991,\n-\tBNXT_ULP_CLASS_HID_2dbd = 0x2dbd,\n-\tBNXT_ULP_CLASS_HID_7bb5 = 0x7bb5,\n+\tBNXT_ULP_CLASS_HID_e082 = 0xe082,\n+\tBNXT_ULP_CLASS_HID_ab46 = 0xab46,\n+\tBNXT_ULP_CLASS_HID_c82a = 0xc82a,\n+\tBNXT_ULP_CLASS_HID_f9a2 = 0xf9a2,\n+\tBNXT_ULP_CLASS_HID_d8ce = 0xd8ce,\n+\tBNXT_ULP_CLASS_HID_a2d2 = 0xa2d2,\n+\tBNXT_ULP_CLASS_HID_c076 = 0xc076,\n+\tBNXT_ULP_CLASS_HID_f1ee = 0xf1ee,\n+\tBNXT_ULP_CLASS_HID_a96e = 0xa96e,\n+\tBNXT_ULP_CLASS_HID_dae6 = 0xdae6,\n+\tBNXT_ULP_CLASS_HID_c7aa = 0xc7aa,\n+\tBNXT_ULP_CLASS_HID_c26e = 0xc26e,\n+\tBNXT_ULP_CLASS_HID_a0fa = 0xa0fa,\n+\tBNXT_ULP_CLASS_HID_d272 = 0xd272,\n+\tBNXT_ULP_CLASS_HID_fff6 = 0xfff6,\n+\tBNXT_ULP_CLASS_HID_e16e = 0xe16e,\n+\tBNXT_ULP_CLASS_HID_e165 = 0xe165,\n+\tBNXT_ULP_CLASS_HID_aaa1 = 0xaaa1,\n+\tBNXT_ULP_CLASS_HID_c9cd = 0xc9cd,\n+\tBNXT_ULP_CLASS_HID_f845 = 0xf845,\n+\tBNXT_ULP_CLASS_HID_90f9 = 0x90f9,\n+\tBNXT_ULP_CLASS_HID_c371 = 0xc371,\n+\tBNXT_ULP_CLASS_HID_e19d = 0xe19d,\n+\tBNXT_ULP_CLASS_HID_d015 = 0xd015,\n+\tBNXT_ULP_CLASS_HID_8c09 = 0x8c09,\n+\tBNXT_ULP_CLASS_HID_be89 = 0xbe89,\n+\tBNXT_ULP_CLASS_HID_ddad = 0xddad,\n+\tBNXT_ULP_CLASS_HID_cc2d = 0xcc2d,\n+\tBNXT_ULP_CLASS_HID_a4d9 = 0xa4d9,\n+\tBNXT_ULP_CLASS_HID_d759 = 0xd759,\n+\tBNXT_ULP_CLASS_HID_f27d = 0xf27d,\n+\tBNXT_ULP_CLASS_HID_e4fd = 0xe4fd,\n+\tBNXT_ULP_CLASS_HID_ecf6 = 0xecf6,\n+\tBNXT_ULP_CLASS_HID_a732 = 0xa732,\n+\tBNXT_ULP_CLASS_HID_c45e = 0xc45e,\n+\tBNXT_ULP_CLASS_HID_f5d6 = 0xf5d6,\n+\tBNXT_ULP_CLASS_HID_d4ba = 0xd4ba,\n+\tBNXT_ULP_CLASS_HID_aea6 = 0xaea6,\n+\tBNXT_ULP_CLASS_HID_cc02 = 0xcc02,\n+\tBNXT_ULP_CLASS_HID_fd9a = 0xfd9a,\n+\tBNXT_ULP_CLASS_HID_a51a = 0xa51a,\n+\tBNXT_ULP_CLASS_HID_d692 = 0xd692,\n+\tBNXT_ULP_CLASS_HID_cbde = 0xcbde,\n+\tBNXT_ULP_CLASS_HID_ce1a = 0xce1a,\n+\tBNXT_ULP_CLASS_HID_ac8e = 0xac8e,\n+\tBNXT_ULP_CLASS_HID_de06 = 0xde06,\n+\tBNXT_ULP_CLASS_HID_f382 = 0xf382,\n+\tBNXT_ULP_CLASS_HID_ed1a = 0xed1a,\n+\tBNXT_ULP_CLASS_HID_9d6a = 0x9d6a,\n+\tBNXT_ULP_CLASS_HID_cee2 = 0xcee2,\n+\tBNXT_ULP_CLASS_HID_ec0e = 0xec0e,\n+\tBNXT_ULP_CLASS_HID_dd86 = 0xdd86,\n+\tBNXT_ULP_CLASS_HID_852e = 0x852e,\n+\tBNXT_ULP_CLASS_HID_b6a6 = 0xb6a6,\n+\tBNXT_ULP_CLASS_HID_eb82 = 0xeb82,\n+\tBNXT_ULP_CLASS_HID_c50a = 0xc50a,\n+\tBNXT_ULP_CLASS_HID_ccca = 0xccca,\n+\tBNXT_ULP_CLASS_HID_8706 = 0x8706,\n+\tBNXT_ULP_CLASS_HID_d38e = 0xd38e,\n+\tBNXT_ULP_CLASS_HID_d5ca = 0xd5ca,\n+\tBNXT_ULP_CLASS_HID_b48e = 0xb48e,\n+\tBNXT_ULP_CLASS_HID_8e8a = 0x8e8a,\n+\tBNXT_ULP_CLASS_HID_db02 = 0xdb02,\n+\tBNXT_ULP_CLASS_HID_dd8e = 0xdd8e,\n+\tBNXT_ULP_CLASS_HID_819a = 0x819a,\n+\tBNXT_ULP_CLASS_HID_b31a = 0xb31a,\n+\tBNXT_ULP_CLASS_HID_d03e = 0xd03e,\n+\tBNXT_ULP_CLASS_HID_c1be = 0xc1be,\n+\tBNXT_ULP_CLASS_HID_890e = 0x890e,\n+\tBNXT_ULP_CLASS_HID_ba8e = 0xba8e,\n+\tBNXT_ULP_CLASS_HID_dfaa = 0xdfaa,\n+\tBNXT_ULP_CLASS_HID_c93a = 0xc93a,\n+\tBNXT_ULP_CLASS_HID_b11a = 0xb11a,\n+\tBNXT_ULP_CLASS_HID_8b4e = 0x8b4e,\n+\tBNXT_ULP_CLASS_HID_c79e = 0xc79e,\n+\tBNXT_ULP_CLASS_HID_d9da = 0xd9da,\n+\tBNXT_ULP_CLASS_HID_b88e = 0xb88e,\n+\tBNXT_ULP_CLASS_HID_ea0e = 0xea0e,\n+\tBNXT_ULP_CLASS_HID_cf0a = 0xcf0a,\n+\tBNXT_ULP_CLASS_HID_c18e = 0xc18e,\n+\tBNXT_ULP_CLASS_HID_a94a = 0xa94a,\n+\tBNXT_ULP_CLASS_HID_daca = 0xdaca,\n+\tBNXT_ULP_CLASS_HID_ffee = 0xffee,\n+\tBNXT_ULP_CLASS_HID_e96e = 0xe96e,\n+\tBNXT_ULP_CLASS_HID_910e = 0x910e,\n+\tBNXT_ULP_CLASS_HID_c28e = 0xc28e,\n+\tBNXT_ULP_CLASS_HID_e7aa = 0xe7aa,\n+\tBNXT_ULP_CLASS_HID_d12a = 0xd12a,\n+\tBNXT_ULP_CLASS_HID_d8ca = 0xd8ca,\n+\tBNXT_ULP_CLASS_HID_930e = 0x930e,\n+\tBNXT_ULP_CLASS_HID_ef4e = 0xef4e,\n+\tBNXT_ULP_CLASS_HID_e18a = 0xe18a,\n+\tBNXT_ULP_CLASS_HID_c08e = 0xc08e,\n+\tBNXT_ULP_CLASS_HID_9a8a = 0x9a8a,\n+\tBNXT_ULP_CLASS_HID_d70a = 0xd70a,\n+\tBNXT_ULP_CLASS_HID_e90e = 0xe90e,\n+\tBNXT_ULP_CLASS_HID_edd9 = 0xedd9,\n+\tBNXT_ULP_CLASS_HID_a61d = 0xa61d,\n+\tBNXT_ULP_CLASS_HID_c571 = 0xc571,\n+\tBNXT_ULP_CLASS_HID_f4f9 = 0xf4f9,\n+\tBNXT_ULP_CLASS_HID_9c45 = 0x9c45,\n+\tBNXT_ULP_CLASS_HID_cfcd = 0xcfcd,\n+\tBNXT_ULP_CLASS_HID_ed21 = 0xed21,\n+\tBNXT_ULP_CLASS_HID_dca9 = 0xdca9,\n+\tBNXT_ULP_CLASS_HID_80b5 = 0x80b5,\n+\tBNXT_ULP_CLASS_HID_b235 = 0xb235,\n+\tBNXT_ULP_CLASS_HID_d111 = 0xd111,\n+\tBNXT_ULP_CLASS_HID_c091 = 0xc091,\n+\tBNXT_ULP_CLASS_HID_a865 = 0xa865,\n+\tBNXT_ULP_CLASS_HID_dbe5 = 0xdbe5,\n+\tBNXT_ULP_CLASS_HID_fec1 = 0xfec1,\n+\tBNXT_ULP_CLASS_HID_e841 = 0xe841,\n+\tBNXT_ULP_CLASS_HID_8e85 = 0x8e85,\n+\tBNXT_ULP_CLASS_HID_b80d = 0xb80d,\n+\tBNXT_ULP_CLASS_HID_df65 = 0xdf65,\n+\tBNXT_ULP_CLASS_HID_ceed = 0xceed,\n+\tBNXT_ULP_CLASS_HID_9645 = 0x9645,\n+\tBNXT_ULP_CLASS_HID_c1cd = 0xc1cd,\n+\tBNXT_ULP_CLASS_HID_e725 = 0xe725,\n+\tBNXT_ULP_CLASS_HID_d6ad = 0xd6ad,\n+\tBNXT_ULP_CLASS_HID_9aa5 = 0x9aa5,\n+\tBNXT_ULP_CLASS_HID_b425 = 0xb425,\n+\tBNXT_ULP_CLASS_HID_eb05 = 0xeb05,\n+\tBNXT_ULP_CLASS_HID_da85 = 0xda85,\n+\tBNXT_ULP_CLASS_HID_a265 = 0xa265,\n+\tBNXT_ULP_CLASS_HID_dde5 = 0xdde5,\n+\tBNXT_ULP_CLASS_HID_f0c5 = 0xf0c5,\n+\tBNXT_ULP_CLASS_HID_e245 = 0xe245,\n+\tBNXT_ULP_CLASS_HID_8b8f = 0x8b8f,\n+\tBNXT_ULP_CLASS_HID_a517 = 0xa517,\n+\tBNXT_ULP_CLASS_HID_d86b = 0xd86b,\n+\tBNXT_ULP_CLASS_HID_cbf3 = 0xcbf3,\n+\tBNXT_ULP_CLASS_HID_934f = 0x934f,\n+\tBNXT_ULP_CLASS_HID_c2c7 = 0xc2c7,\n+\tBNXT_ULP_CLASS_HID_e02b = 0xe02b,\n+\tBNXT_ULP_CLASS_HID_d3a3 = 0xd3a3,\n+\tBNXT_ULP_CLASS_HID_87a7 = 0x87a7,\n+\tBNXT_ULP_CLASS_HID_b137 = 0xb137,\n+\tBNXT_ULP_CLASS_HID_d403 = 0xd403,\n+\tBNXT_ULP_CLASS_HID_c793 = 0xc793,\n+\tBNXT_ULP_CLASS_HID_af67 = 0xaf67,\n+\tBNXT_ULP_CLASS_HID_dee7 = 0xdee7,\n+\tBNXT_ULP_CLASS_HID_fdc3 = 0xfdc3,\n+\tBNXT_ULP_CLASS_HID_ef43 = 0xef43,\n+\tBNXT_ULP_CLASS_HID_8dbf = 0x8dbf,\n+\tBNXT_ULP_CLASS_HID_bf07 = 0xbf07,\n+\tBNXT_ULP_CLASS_HID_d21f = 0xd21f,\n+\tBNXT_ULP_CLASS_HID_cde7 = 0xcde7,\n+\tBNXT_ULP_CLASS_HID_956f = 0x956f,\n+\tBNXT_ULP_CLASS_HID_c4c7 = 0xc4c7,\n+\tBNXT_ULP_CLASS_HID_fbcf = 0xfbcf,\n+\tBNXT_ULP_CLASS_HID_d5a7 = 0xd5a7,\n+\tBNXT_ULP_CLASS_HID_9957 = 0x9957,\n+\tBNXT_ULP_CLASS_HID_cb27 = 0xcb27,\n+\tBNXT_ULP_CLASS_HID_ee37 = 0xee37,\n+\tBNXT_ULP_CLASS_HID_d987 = 0xd987,\n+\tBNXT_ULP_CLASS_HID_a107 = 0xa107,\n+\tBNXT_ULP_CLASS_HID_d0e7 = 0xd0e7,\n+\tBNXT_ULP_CLASS_HID_f7e7 = 0xf7e7,\n+\tBNXT_ULP_CLASS_HID_c827 = 0xc827,\n+\tBNXT_ULP_CLASS_HID_f76a = 0xf76a,\n+\tBNXT_ULP_CLASS_HID_bcae = 0xbcae,\n+\tBNXT_ULP_CLASS_HID_dfc2 = 0xdfc2,\n+\tBNXT_ULP_CLASS_HID_ee4a = 0xee4a,\n+\tBNXT_ULP_CLASS_HID_cf26 = 0xcf26,\n+\tBNXT_ULP_CLASS_HID_b53a = 0xb53a,\n+\tBNXT_ULP_CLASS_HID_d79e = 0xd79e,\n+\tBNXT_ULP_CLASS_HID_e606 = 0xe606,\n+\tBNXT_ULP_CLASS_HID_be86 = 0xbe86,\n+\tBNXT_ULP_CLASS_HID_cd0e = 0xcd0e,\n+\tBNXT_ULP_CLASS_HID_d042 = 0xd042,\n+\tBNXT_ULP_CLASS_HID_d586 = 0xd586,\n+\tBNXT_ULP_CLASS_HID_b712 = 0xb712,\n+\tBNXT_ULP_CLASS_HID_c59a = 0xc59a,\n+\tBNXT_ULP_CLASS_HID_e81e = 0xe81e,\n+\tBNXT_ULP_CLASS_HID_f686 = 0xf686,\n+\tBNXT_ULP_CLASS_HID_86f6 = 0x86f6,\n+\tBNXT_ULP_CLASS_HID_d57e = 0xd57e,\n+\tBNXT_ULP_CLASS_HID_f792 = 0xf792,\n+\tBNXT_ULP_CLASS_HID_c61a = 0xc61a,\n+\tBNXT_ULP_CLASS_HID_9eb2 = 0x9eb2,\n+\tBNXT_ULP_CLASS_HID_ad3a = 0xad3a,\n+\tBNXT_ULP_CLASS_HID_f01e = 0xf01e,\n+\tBNXT_ULP_CLASS_HID_de96 = 0xde96,\n+\tBNXT_ULP_CLASS_HID_d756 = 0xd756,\n+\tBNXT_ULP_CLASS_HID_9c9a = 0x9c9a,\n+\tBNXT_ULP_CLASS_HID_c812 = 0xc812,\n+\tBNXT_ULP_CLASS_HID_ce56 = 0xce56,\n+\tBNXT_ULP_CLASS_HID_af12 = 0xaf12,\n+\tBNXT_ULP_CLASS_HID_9516 = 0x9516,\n+\tBNXT_ULP_CLASS_HID_c09e = 0xc09e,\n+\tBNXT_ULP_CLASS_HID_c612 = 0xc612,\n+\tBNXT_ULP_CLASS_HID_9a06 = 0x9a06,\n+\tBNXT_ULP_CLASS_HID_a886 = 0xa886,\n+\tBNXT_ULP_CLASS_HID_cba2 = 0xcba2,\n+\tBNXT_ULP_CLASS_HID_da22 = 0xda22,\n+\tBNXT_ULP_CLASS_HID_9292 = 0x9292,\n+\tBNXT_ULP_CLASS_HID_a112 = 0xa112,\n+\tBNXT_ULP_CLASS_HID_c436 = 0xc436,\n+\tBNXT_ULP_CLASS_HID_d2a6 = 0xd2a6,\n+\tBNXT_ULP_CLASS_HID_aa86 = 0xaa86,\n+\tBNXT_ULP_CLASS_HID_90d2 = 0x90d2,\n+\tBNXT_ULP_CLASS_HID_dc02 = 0xdc02,\n+\tBNXT_ULP_CLASS_HID_c246 = 0xc246,\n+\tBNXT_ULP_CLASS_HID_a312 = 0xa312,\n+\tBNXT_ULP_CLASS_HID_f192 = 0xf192,\n+\tBNXT_ULP_CLASS_HID_d496 = 0xd496,\n+\tBNXT_ULP_CLASS_HID_da12 = 0xda12,\n+\tBNXT_ULP_CLASS_HID_b2d6 = 0xb2d6,\n+\tBNXT_ULP_CLASS_HID_c156 = 0xc156,\n+\tBNXT_ULP_CLASS_HID_e472 = 0xe472,\n+\tBNXT_ULP_CLASS_HID_f2f2 = 0xf2f2,\n+\tBNXT_ULP_CLASS_HID_8a92 = 0x8a92,\n+\tBNXT_ULP_CLASS_HID_d912 = 0xd912,\n+\tBNXT_ULP_CLASS_HID_fc36 = 0xfc36,\n+\tBNXT_ULP_CLASS_HID_cab6 = 0xcab6,\n+\tBNXT_ULP_CLASS_HID_c356 = 0xc356,\n+\tBNXT_ULP_CLASS_HID_8892 = 0x8892,\n+\tBNXT_ULP_CLASS_HID_f4d2 = 0xf4d2,\n+\tBNXT_ULP_CLASS_HID_fa16 = 0xfa16,\n+\tBNXT_ULP_CLASS_HID_db12 = 0xdb12,\n+\tBNXT_ULP_CLASS_HID_8116 = 0x8116,\n+\tBNXT_ULP_CLASS_HID_cc96 = 0xcc96,\n+\tBNXT_ULP_CLASS_HID_f292 = 0xf292,\n+\tBNXT_ULP_CLASS_HID_e84d = 0xe84d,\n+\tBNXT_ULP_CLASS_HID_a389 = 0xa389,\n+\tBNXT_ULP_CLASS_HID_c0e5 = 0xc0e5,\n+\tBNXT_ULP_CLASS_HID_f16d = 0xf16d,\n+\tBNXT_ULP_CLASS_HID_99d1 = 0x99d1,\n+\tBNXT_ULP_CLASS_HID_ca59 = 0xca59,\n+\tBNXT_ULP_CLASS_HID_e8b5 = 0xe8b5,\n+\tBNXT_ULP_CLASS_HID_d93d = 0xd93d,\n+\tBNXT_ULP_CLASS_HID_8521 = 0x8521,\n+\tBNXT_ULP_CLASS_HID_b7a1 = 0xb7a1,\n+\tBNXT_ULP_CLASS_HID_d485 = 0xd485,\n+\tBNXT_ULP_CLASS_HID_c505 = 0xc505,\n+\tBNXT_ULP_CLASS_HID_adf1 = 0xadf1,\n+\tBNXT_ULP_CLASS_HID_de71 = 0xde71,\n+\tBNXT_ULP_CLASS_HID_fb55 = 0xfb55,\n+\tBNXT_ULP_CLASS_HID_edd5 = 0xedd5,\n+\tBNXT_ULP_CLASS_HID_8b11 = 0x8b11,\n+\tBNXT_ULP_CLASS_HID_bd99 = 0xbd99,\n+\tBNXT_ULP_CLASS_HID_daf1 = 0xdaf1,\n+\tBNXT_ULP_CLASS_HID_cb79 = 0xcb79,\n+\tBNXT_ULP_CLASS_HID_93d1 = 0x93d1,\n+\tBNXT_ULP_CLASS_HID_c459 = 0xc459,\n+\tBNXT_ULP_CLASS_HID_e2b1 = 0xe2b1,\n+\tBNXT_ULP_CLASS_HID_d339 = 0xd339,\n+\tBNXT_ULP_CLASS_HID_9f31 = 0x9f31,\n+\tBNXT_ULP_CLASS_HID_b1b1 = 0xb1b1,\n+\tBNXT_ULP_CLASS_HID_ee91 = 0xee91,\n+\tBNXT_ULP_CLASS_HID_df11 = 0xdf11,\n+\tBNXT_ULP_CLASS_HID_a7f1 = 0xa7f1,\n+\tBNXT_ULP_CLASS_HID_d871 = 0xd871,\n+\tBNXT_ULP_CLASS_HID_f551 = 0xf551,\n+\tBNXT_ULP_CLASS_HID_e7d1 = 0xe7d1,\n+\tBNXT_ULP_CLASS_HID_8e1b = 0x8e1b,\n+\tBNXT_ULP_CLASS_HID_a083 = 0xa083,\n+\tBNXT_ULP_CLASS_HID_ddff = 0xddff,\n+\tBNXT_ULP_CLASS_HID_ce67 = 0xce67,\n+\tBNXT_ULP_CLASS_HID_96db = 0x96db,\n+\tBNXT_ULP_CLASS_HID_c753 = 0xc753,\n+\tBNXT_ULP_CLASS_HID_e5bf = 0xe5bf,\n+\tBNXT_ULP_CLASS_HID_d637 = 0xd637,\n+\tBNXT_ULP_CLASS_HID_8233 = 0x8233,\n+\tBNXT_ULP_CLASS_HID_b4a3 = 0xb4a3,\n+\tBNXT_ULP_CLASS_HID_d197 = 0xd197,\n+\tBNXT_ULP_CLASS_HID_c207 = 0xc207,\n+\tBNXT_ULP_CLASS_HID_aaf3 = 0xaaf3,\n+\tBNXT_ULP_CLASS_HID_db73 = 0xdb73,\n+\tBNXT_ULP_CLASS_HID_f857 = 0xf857,\n+\tBNXT_ULP_CLASS_HID_ead7 = 0xead7,\n+\tBNXT_ULP_CLASS_HID_882b = 0x882b,\n+\tBNXT_ULP_CLASS_HID_ba93 = 0xba93,\n+\tBNXT_ULP_CLASS_HID_d78b = 0xd78b,\n+\tBNXT_ULP_CLASS_HID_c873 = 0xc873,\n+\tBNXT_ULP_CLASS_HID_90fb = 0x90fb,\n+\tBNXT_ULP_CLASS_HID_c153 = 0xc153,\n+\tBNXT_ULP_CLASS_HID_fe5b = 0xfe5b,\n+\tBNXT_ULP_CLASS_HID_d033 = 0xd033,\n+\tBNXT_ULP_CLASS_HID_9cc3 = 0x9cc3,\n+\tBNXT_ULP_CLASS_HID_ceb3 = 0xceb3,\n+\tBNXT_ULP_CLASS_HID_eba3 = 0xeba3,\n+\tBNXT_ULP_CLASS_HID_dc13 = 0xdc13,\n+\tBNXT_ULP_CLASS_HID_a493 = 0xa493,\n+\tBNXT_ULP_CLASS_HID_d573 = 0xd573,\n+\tBNXT_ULP_CLASS_HID_f273 = 0xf273,\n+\tBNXT_ULP_CLASS_HID_cdb3 = 0xcdb3,\n+\tBNXT_ULP_CLASS_HID_ff35 = 0xff35,\n+\tBNXT_ULP_CLASS_HID_b4f1 = 0xb4f1,\n+\tBNXT_ULP_CLASS_HID_d79d = 0xd79d,\n+\tBNXT_ULP_CLASS_HID_e615 = 0xe615,\n+\tBNXT_ULP_CLASS_HID_8ea9 = 0x8ea9,\n+\tBNXT_ULP_CLASS_HID_dd21 = 0xdd21,\n+\tBNXT_ULP_CLASS_HID_ffcd = 0xffcd,\n+\tBNXT_ULP_CLASS_HID_ce45 = 0xce45,\n+\tBNXT_ULP_CLASS_HID_9259 = 0x9259,\n+\tBNXT_ULP_CLASS_HID_a0d9 = 0xa0d9,\n+\tBNXT_ULP_CLASS_HID_c3fd = 0xc3fd,\n+\tBNXT_ULP_CLASS_HID_d27d = 0xd27d,\n+\tBNXT_ULP_CLASS_HID_ba89 = 0xba89,\n+\tBNXT_ULP_CLASS_HID_c909 = 0xc909,\n+\tBNXT_ULP_CLASS_HID_ec2d = 0xec2d,\n+\tBNXT_ULP_CLASS_HID_faad = 0xfaad,\n \tBNXT_ULP_CLASS_HID_34c6 = 0x34c6,\n \tBNXT_ULP_CLASS_HID_0c22 = 0x0c22,\n \tBNXT_ULP_CLASS_HID_1cbe = 0x1cbe,\ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h\nindex 1d7bbfe2cc..0a5c7e3d6e 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Thu May 20 11:56:39 2021 */\n+/* date: Fri Aug  6 11:15:47 2021 */\n \n #ifndef ULP_HDR_FIELD_ENUMS_H_\n #define ULP_HDR_FIELD_ENUMS_H_\n@@ -459,16 +459,14 @@ enum bnxt_ulp_hf_0_2_1_bitmask {\n \tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC          = 0x0000080000000000,\n \tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC          = 0x0000040000000000,\n \tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE          = 0x0000020000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_VER          = 0x0000010000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TOS          = 0x0000008000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_LEN          = 0x0000004000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_ID      = 0x0000002000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_OFF     = 0x0000001000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TTL          = 0x0000000800000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_PROTO_ID     = 0x0000000400000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_CSUM         = 0x0000000200000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR     = 0x0000000100000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR     = 0x0000000080000000\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_VER          = 0x0000010000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_TC           = 0x0000008000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_FLOW_LABEL   = 0x0000004000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_PAYLOAD_LEN  = 0x0000002000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_PROTO_ID     = 0x0000001000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_TTL          = 0x0000000800000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR     = 0x0000000400000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR     = 0x0000000200000000\n };\n \n enum bnxt_ulp_hf_0_2_2_bitmask {\n@@ -504,16 +502,7 @@ enum bnxt_ulp_hf_0_2_2_bitmask {\n \tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID     = 0x0000000400000000,\n \tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM         = 0x0000000200000000,\n \tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR     = 0x0000000100000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR     = 0x0000000080000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT      = 0x0000000040000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT      = 0x0000000020000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SENT_SEQ      = 0x0000000010000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RECV_ACK      = 0x0000000008000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DATA_OFF      = 0x0000000004000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_TCP_FLAGS     = 0x0000000002000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RX_WIN        = 0x0000000001000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_CSUM          = 0x0000000000800000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_URP           = 0x0000000000400000\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR     = 0x0000000080000000\n };\n \n enum bnxt_ulp_hf_0_2_3_bitmask {\n@@ -540,20 +529,23 @@ enum bnxt_ulp_hf_0_2_3_bitmask {\n \tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC          = 0x0000080000000000,\n \tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC          = 0x0000040000000000,\n \tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_TYPE          = 0x0000020000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_VER          = 0x0000010000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TOS          = 0x0000008000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_LEN          = 0x0000004000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_ID      = 0x0000002000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_OFF     = 0x0000001000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TTL          = 0x0000000800000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_PROTO_ID     = 0x0000000400000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_CSUM         = 0x0000000200000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR     = 0x0000000100000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR     = 0x0000000080000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT      = 0x0000000040000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT      = 0x0000000020000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_LENGTH        = 0x0000000010000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_CSUM          = 0x0000000008000000\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_VER          = 0x0000010000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_TC           = 0x0000008000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_FLOW_LABEL   = 0x0000004000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_PAYLOAD_LEN  = 0x0000002000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_PROTO_ID     = 0x0000001000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_TTL          = 0x0000000800000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR     = 0x0000000400000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR     = 0x0000000200000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT      = 0x0000000100000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT      = 0x0000000080000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SENT_SEQ      = 0x0000000040000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_RECV_ACK      = 0x0000000020000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DATA_OFF      = 0x0000000010000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_TCP_FLAGS     = 0x0000000008000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_RX_WIN        = 0x0000000004000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_CSUM          = 0x0000000002000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_TCP_URP           = 0x0000000001000000\n };\n \n enum bnxt_ulp_hf_0_2_4_bitmask {\n@@ -590,11 +582,134 @@ enum bnxt_ulp_hf_0_2_4_bitmask {\n \tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM         = 0x0000000200000000,\n \tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR     = 0x0000000100000000,\n \tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR     = 0x0000000080000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_TYPE         = 0x0000000040000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CODE         = 0x0000000020000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CSUM         = 0x0000000010000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_IDENT        = 0x0000000008000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_SEQ_NUM      = 0x0000000004000000\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT      = 0x0000000040000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT      = 0x0000000020000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SENT_SEQ      = 0x0000000010000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_RECV_ACK      = 0x0000000008000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DATA_OFF      = 0x0000000004000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_TCP_FLAGS     = 0x0000000002000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_RX_WIN        = 0x0000000001000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_CSUM          = 0x0000000000800000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_TCP_URP           = 0x0000000000400000\n+};\n+\n+enum bnxt_ulp_hf_0_2_5_bitmask {\n+\tBNXT_ULP_HF_0_2_5_BITMASK_WM                  = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_VER          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TOS          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_LEN          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_ID      = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_OFF     = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TTL          = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_PROTO_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_CSUM         = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR     = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_SRC_PORT      = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT      = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_LENGTH        = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_O_UDP_CSUM          = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_FLAGS       = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_RSVD0       = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI         = 0x0000200000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_RSVD1       = 0x0000100000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC          = 0x0000080000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC          = 0x0000040000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_ETH_TYPE          = 0x0000020000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_VER          = 0x0000010000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_TC           = 0x0000008000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_FLOW_LABEL   = 0x0000004000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_PAYLOAD_LEN  = 0x0000002000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_PROTO_ID     = 0x0000001000000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_TTL          = 0x0000000800000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR     = 0x0000000400000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR     = 0x0000000200000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT      = 0x0000000100000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT      = 0x0000000080000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_LENGTH        = 0x0000000040000000,\n+\tBNXT_ULP_HF_0_2_5_BITMASK_I_UDP_CSUM          = 0x0000000020000000\n+};\n+\n+enum bnxt_ulp_hf_0_2_6_bitmask {\n+\tBNXT_ULP_HF_0_2_6_BITMASK_WM                  = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_VER          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_TOS          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_LEN          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_FRAG_ID      = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_FRAG_OFF     = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_TTL          = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_PROTO_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_CSUM         = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR     = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT      = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT      = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH        = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM          = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_FLAGS       = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD0       = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI         = 0x0000200000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD1       = 0x0000100000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC          = 0x0000080000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC          = 0x0000040000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_ETH_TYPE          = 0x0000020000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_VER          = 0x0000010000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_TOS          = 0x0000008000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_LEN          = 0x0000004000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_FRAG_ID      = 0x0000002000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_FRAG_OFF     = 0x0000001000000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_TTL          = 0x0000000800000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_PROTO_ID     = 0x0000000400000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_CSUM         = 0x0000000200000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR     = 0x0000000100000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR     = 0x0000000080000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT      = 0x0000000040000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT      = 0x0000000020000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_LENGTH        = 0x0000000010000000,\n+\tBNXT_ULP_HF_0_2_6_BITMASK_I_UDP_CSUM          = 0x0000000008000000\n+};\n+\n+enum bnxt_ulp_hf_0_2_7_bitmask {\n+\tBNXT_ULP_HF_0_2_7_BITMASK_WM                  = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_VER          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TOS          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_LEN          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_ID      = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_OFF     = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TTL          = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_PROTO_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_CSUM         = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR     = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT      = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT      = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_LENGTH        = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_CSUM          = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_FLAGS       = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_RSVD0       = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI         = 0x0000200000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_RSVD1       = 0x0000100000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC          = 0x0000080000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC          = 0x0000040000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_ETH_TYPE          = 0x0000020000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_VER          = 0x0000010000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_TOS          = 0x0000008000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_LEN          = 0x0000004000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_FRAG_ID      = 0x0000002000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_FRAG_OFF     = 0x0000001000000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_TTL          = 0x0000000800000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_PROTO_ID     = 0x0000000400000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_CSUM         = 0x0000000200000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR     = 0x0000000100000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR     = 0x0000000080000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_TYPE         = 0x0000000040000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_CODE         = 0x0000000020000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_CSUM         = 0x0000000010000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_IDENT        = 0x0000000008000000,\n+\tBNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_SEQ_NUM      = 0x0000000004000000\n };\n \n enum bnxt_ulp_hf_0_3_0_bitmask {\ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c\nindex 3d1e95d18c..684fa66f48 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Thu Jul  8 08:44:00 2021 */\n+/* date: Tue Aug 17 12:16:42 2021 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -131,6 +131,46 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {\n \t.num_buckets             = 8,\n \t.hash_tbl_entries        = 1024,\n \t.result_byte_order       = BNXT_ULP_BYTE_ORDER_LE\n+\t},\n+\t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 |\n+\t\tBNXT_ULP_DIRECTION_INGRESS] = {\n+\t.name                    = \"INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE\",\n+\t.result_num_entries      = 0,\n+\t.result_num_bytes        = 6,\n+\t.key_num_bytes           = 10,\n+\t.num_buckets             = 4,\n+\t.hash_tbl_entries        = 0,\n+\t.result_byte_order       = BNXT_ULP_BYTE_ORDER_LE\n+\t},\n+\t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 |\n+\t\t\t\tBNXT_ULP_DIRECTION_EGRESS] = {\n+\t.name                    = \"INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE\",\n+\t.result_num_entries      = 128,\n+\t.result_num_bytes        = 6,\n+\t.key_num_bytes           = 10,\n+\t.num_buckets             = 4,\n+\t.hash_tbl_entries        = 512,\n+\t.result_byte_order       = BNXT_ULP_BYTE_ORDER_LE\n+\t},\n+\t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 |\n+\t\tBNXT_ULP_DIRECTION_INGRESS] = {\n+\t.name                    = \"INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE\",\n+\t.result_num_entries      = 0,\n+\t.result_num_bytes        = 6,\n+\t.key_num_bytes           = 17,\n+\t.num_buckets             = 8,\n+\t.hash_tbl_entries        = 0,\n+\t.result_byte_order       = BNXT_ULP_BYTE_ORDER_LE\n+\t},\n+\t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 |\n+\t\tBNXT_ULP_DIRECTION_EGRESS] = {\n+\t.name                    = \"INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE\",\n+\t.result_num_entries      = 256,\n+\t.result_num_bytes        = 6,\n+\t.key_num_bytes           = 17,\n+\t.num_buckets             = 8,\n+\t.hash_tbl_entries        = 1024,\n+\t.result_byte_order       = BNXT_ULP_BYTE_ORDER_LE\n \t}\n };\n \n@@ -222,6 +262,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {\n \t.byte_count_shift        = 0,\n \t.packet_count_shift      = 36,\n \t.dynamic_pad_en          = 0,\n+\t.dynamic_sram_en         = 0,\n \t.dev_tbls                = ulp_template_wh_plus_tbls\n \t},\n \t[BNXT_ULP_DEVICE_ID_THOR] = {\n@@ -246,12 +287,24 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {\n \t.byte_count_shift        = 0,\n \t.packet_count_shift      = 35,\n \t.dynamic_pad_en          = 1,\n+\t.dynamic_sram_en         = 1,\n+\t.dyn_encap_list_size     = 4,\n+\t.dyn_encap_sizes         = {{64, TF_TBL_TYPE_ACT_ENCAP_8B},\n+\t\t\t\t\t{128, TF_TBL_TYPE_ACT_ENCAP_16B},\n+\t\t\t\t\t{256, TF_TBL_TYPE_ACT_ENCAP_32B},\n+\t\t\t\t\t{512, TF_TBL_TYPE_ACT_ENCAP_64B}},\n+\t.dyn_modify_list_size    = 4,\n+\t.dyn_modify_sizes        = {{64, TF_TBL_TYPE_ACT_MODIFY_8B},\n+\t\t\t\t\t{128, TF_TBL_TYPE_ACT_MODIFY_16B},\n+\t\t\t\t\t{256, TF_TBL_TYPE_ACT_MODIFY_32B},\n+\t\t\t\t\t{512, TF_TBL_TYPE_ACT_MODIFY_64B}},\n \t.em_blk_size_bits        = 100,\n \t.em_blk_align_bits       = 128,\n \t.em_key_align_bytes      = 80,\n \t.wc_slice_width          = 160,\n \t.wc_max_slices           = 4,\n-\t.wc_mode_list            = {0x0000000c, 0x0000000e, 0x0000000f, 0x0000000f},\n+\t.wc_mode_list            = {0x0000000c, 0x0000000e,\n+\t\t\t\t\t0x0000000f, 0x0000000f},\n \t.wc_mod_list_max_size    = 4,\n \t.wc_ctl_size_bits        = 32,\n \t.dev_tbls                = ulp_template_thor_tbls\n@@ -307,6 +360,16 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = {\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.flags                   = BNXT_ULP_APP_CAP_SHARED_EN |\n \t\t\t\t   BNXT_ULP_APP_CAP_UNICAST_ONLY\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.flags                   = BNXT_ULP_APP_CAP_UNICAST_ONLY\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.flags                   = BNXT_ULP_APP_CAP_UNICAST_ONLY\n \t}\n };\n \n@@ -1279,333 +1342,1261 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {\n \t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,\n \t.direction               = TF_DIR_TX\n-\t}\n-};\n-\n-/* List of tf resources required to be reserved per app/device */\n-struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n+\t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_HIGH,\n-\t.count                   = 422\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_LOW,\n-\t.count                   = 6\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,\n+\t.direction               = TF_DIR_TX\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n-\t.count                   = 191\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,\n+\t.direction               = TF_DIR_TX\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n-\t.count                   = 63\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n-\t.count                   = 192\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,\n+\t.direction               = TF_DIR_TX\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t.count                   = 8192\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n-\t.count                   = 6912\n+\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_16B,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_ACT_MODIFY_IPV4,\n-\t.count                   = 1023\n+\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_16B,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,\n+\t.direction               = TF_DIR_TX\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_8B,\n-\t.count                   = 511\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_16B,\n-\t.count                   = 15\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC,\n-\t.count                   = 255\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,\n+\t.direction               = TF_DIR_TX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_MIRROR_CONFIG,\n-\t.count                   = 1\n+\t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,\n+\t.direction               = TF_DIR_TX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.count                   = 422\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.count                   = 6\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,\n+\t.direction               = TF_DIR_TX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type           = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.count                   = 960\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n-\t.count                   = 88\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n-\t.resource_type           = TF_EM_TBL_TYPE_EM_RECORD,\n-\t.count                   = 13168\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_16B,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_RX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n-\t.resource_type           = TF_EM_TBL_TYPE_TBL_SCOPE,\n-\t.count                   = 1\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_16B,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,\n+\t.direction               = TF_DIR_TX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_TX,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_HIGH,\n-\t.count                   = 292\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_TX,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_LOW,\n-\t.count                   = 148\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_TX,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n-\t.count                   = 191\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_TX,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n-\t.count                   = 63\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_TX,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n-\t.count                   = 192\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_TX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t.count                   = 8192\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,\n+\t.direction               = TF_DIR_RX\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_WC_FKB,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_WC_FKB,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_WC_FKB,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_WC_FKB,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_WC_FKB,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_WC_FKB,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,\n+\t.direction               = TF_DIR_TX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_WC_FKB,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,\n+\t.direction               = TF_DIR_TX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,\n+\t.direction               = TF_DIR_TX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,\n+\t.direction               = TF_DIR_TX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_EM_FKB,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_EM_FKB,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_EM_FKB,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,\n+\t.direction               = TF_DIR_RX\n+\t},\n+\t{\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_EM_FKB,\n+\t.glb_regfile_index       = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,\n+\t.direction               = TF_DIR_RX\n+\t}\n+};\n+\n+/* List of tf resources required to be reserved per app/device */\n+struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_HIGH,\n+\t.count                   = 422\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_LOW,\n+\t.count                   = 6\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.count                   = 191\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.count                   = 63\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.count                   = 192\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.count                   = 8192\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n+\t.count                   = 6912\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_MODIFY_IPV4,\n+\t.count                   = 1023\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t.count                   = 511\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_16B,\n+\t.count                   = 15\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC,\n+\t.count                   = 255\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_MIRROR_CONFIG,\n+\t.count                   = 1\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n+\t.count                   = 422\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.count                   = 6\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_PROF_TCAM,\n+\t.count                   = 960\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n+\t.count                   = 88\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n+\t.resource_type           = TF_EM_TBL_TYPE_EM_RECORD,\n+\t.count                   = 13168\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n+\t.resource_type           = TF_EM_TBL_TYPE_TBL_SCOPE,\n+\t.count                   = 1\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_HIGH,\n+\t.count                   = 292\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_LOW,\n+\t.count                   = 148\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.count                   = 191\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.count                   = 63\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.count                   = 192\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.count                   = 8192\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n+\t.count                   = 6912\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_MODIFY_IPV4,\n+\t.count                   = 1023\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_64B,\n+\t.count                   = 511\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_16B,\n+\t.count                   = 223\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t.count                   = 255\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n+\t.count                   = 488\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,\n+\t.count                   = 511\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_MIRROR_CONFIG,\n+\t.count                   = 1\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n+\t.count                   = 292\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.count                   = 144\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_PROF_TCAM,\n+\t.count                   = 960\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n+\t.count                   = 928\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n+\t.resource_type           = TF_EM_TBL_TYPE_EM_RECORD,\n+\t.count                   = 15232\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n+\t.resource_type           = TF_EM_TBL_TYPE_TBL_SCOPE,\n+\t.count                   = 1\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_HIGH,\n+\t.count                   = 272\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_LOW,\n+\t.count                   = 6\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.count                   = 32\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.count                   = 32\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.count                   = 32\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.count                   = 8192\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n+\t.count                   = 8192\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_MIRROR_CONFIG,\n+\t.count                   = 5\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_EM_FKB,\n+\t.count                   = 32\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_WC_FKB,\n+\t.count                   = 31\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_64B,\n+\t.count                   = 64\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n+\t.count                   = 64\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n+\t.count                   = 272\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.count                   = 6\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_PROF_TCAM,\n+\t.count                   = 128\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n+\t.count                   = 4096\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n+\t.resource_type           = TF_EM_TBL_TYPE_EM_RECORD,\n+\t.count                   = 16384\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_LOW,\n+\t.count                   = 272\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.count                   = 32\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.count                   = 63\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.count                   = 32\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.count                   = 8192\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n+\t.count                   = 8192\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_MIRROR_CONFIG,\n+\t.count                   = 5\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_EM_FKB,\n+\t.count                   = 32\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_WC_FKB,\n+\t.count                   = 32\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_64B,\n+\t.count                   = 64\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n+\t.count                   = 100\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_MODIFY_64B,\n+\t.count                   = 32\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.count                   = 272\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_PROF_TCAM,\n+\t.count                   = 128\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n+\t.count                   = 4096\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n+\t.resource_type           = TF_EM_TBL_TYPE_EM_RECORD,\n+\t.count                   = 16384\n+\t},\n+\t{\n+\t.app_id                  = 0,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_METADATA,\n+\t.count                   = 1\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_HIGH,\n+\t.count                   = 32\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_LOW,\n+\t.count                   = 2\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.count                   = 4\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.count                   = 4\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.count                   = 4\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.count                   = 128\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n+\t.count                   = 128\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_MODIFY_IPV4,\n+\t.count                   = 4\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t.count                   = 4\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_16B,\n+\t.count                   = 4\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC,\n+\t.count                   = 4\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n+\t.count                   = 32\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.count                   = 2\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_PROF_TCAM,\n+\t.count                   = 32\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n+\t.count                   = 4\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n+\t.resource_type           = TF_EM_TBL_TYPE_EM_RECORD,\n+\t.count                   = 1024\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_HIGH,\n+\t.count                   = 32\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_L2_CTXT_LOW,\n+\t.count                   = 2\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n+\t.count                   = 4\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n+\t.count                   = 4\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n+\t.count                   = 4\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.count                   = 128\n+\t},\n+\t{\n+\t.app_id                  = 1,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n-\t.count                   = 6912\n+\t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_MODIFY_IPV4,\n-\t.count                   = 1023\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_64B,\n-\t.count                   = 511\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_16B,\n-\t.count                   = 223\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_8B,\n-\t.count                   = 255\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n-\t.count                   = 488\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,\n-\t.count                   = 511\n-\t},\n-\t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_TX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_MIRROR_CONFIG,\n-\t.count                   = 1\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.count                   = 292\n+\t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.count                   = 144\n+\t.count                   = 2\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.count                   = 960\n+\t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n-\t.count                   = 928\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n \t.resource_type           = TF_EM_TBL_TYPE_EM_RECORD,\n-\t.count                   = 15232\n-\t},\n-\t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.direction               = TF_DIR_TX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n-\t.resource_type           = TF_EM_TBL_TYPE_TBL_SCOPE,\n-\t.count                   = 1\n+\t.count                   = 1024\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_L2_CTXT_HIGH,\n-\t.count                   = 422\n+\t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_L2_CTXT_LOW,\n-\t.count                   = 6\n+\t.count                   = 2\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -1613,15 +2604,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n-\t.count                   = 32\n+\t.count                   = 16\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -1629,255 +2620,223 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n-\t.direction               = TF_DIR_RX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t.count                   = 2048\n-\t},\n-\t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n-\t.count                   = 512\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.count                   = 528\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_MIRROR_CONFIG,\n-\t.count                   = 5\n+\t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n+\t.count                   = 256\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_EM_FKB,\n-\t.count                   = 32\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_WC_FKB,\n-\t.count                   = 31\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_64B,\n-\t.count                   = 64\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n-\t.count                   = 64\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.count                   = 300\n+\t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.count                   = 6\n+\t.count                   = 2\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.count                   = 128\n+\t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n-\t.count                   = 2048\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n \t.resource_type           = TF_EM_TBL_TYPE_EM_RECORD,\n-\t.count                   = 13200\n+\t.count                   = 1024\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_L2_CTXT_HIGH,\n-\t.count                   = 26\n+\t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_L2_CTXT_LOW,\n-\t.count                   = 26\n+\t.count                   = 2\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n-\t.count                   = 32\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n-\t.count                   = 63\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n-\t.count                   = 32\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t.count                   = 1023\n-\t},\n-\t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n-\t.direction               = TF_DIR_TX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n \t.count                   = 512\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_MIRROR_CONFIG,\n-\t.count                   = 5\n+\t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n+\t.count                   = 256\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_EM_FKB,\n-\t.count                   = 32\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_WC_FKB,\n-\t.count                   = 32\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_64B,\n-\t.count                   = 64\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n-\t.count                   = 100\n-\t},\n-\t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n-\t.direction               = TF_DIR_TX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_ACT_MODIFY_64B,\n-\t.count                   = 32\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.count                   = 200\n+\t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.count                   = 110\n+\t.count                   = 2\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.count                   = 128\n+\t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n-\t.count                   = 2048\n+\t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 0,\n+\t.app_id                  = 1,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n \t.resource_type           = TF_EM_TBL_TYPE_EM_RECORD,\n-\t.count                   = 15232\n-\t},\n-\t{\n-\t.app_id                  = 0,\n-\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n-\t.direction               = TF_DIR_TX,\n-\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type           = TF_TBL_TYPE_METADATA,\n-\t.count                   = 1\n+\t.count                   = 1024\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -1885,7 +2844,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -1893,7 +2852,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 2\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -1901,7 +2860,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -1909,7 +2868,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -1917,7 +2876,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -1925,7 +2884,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -1933,7 +2892,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -1941,7 +2900,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -1949,7 +2908,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -1957,7 +2916,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -1965,7 +2924,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n@@ -1973,7 +2932,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n@@ -1981,7 +2940,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 2\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n@@ -1989,15 +2948,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n-\t.count                   = 4\n+\t.count                   = 64\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n@@ -2005,7 +2964,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 1024\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2013,7 +2972,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2021,7 +2980,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 2\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2029,7 +2988,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2037,7 +2996,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2045,7 +3004,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2053,7 +3012,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2061,7 +3020,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2069,7 +3028,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2077,7 +3036,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2085,7 +3044,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2093,7 +3052,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2101,7 +3060,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2109,7 +3068,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n@@ -2117,7 +3076,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n@@ -2125,7 +3084,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 2\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n@@ -2133,7 +3092,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n@@ -2141,7 +3100,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n@@ -2149,7 +3108,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 1024\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2157,7 +3116,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2165,7 +3124,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 2\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2173,7 +3132,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2181,7 +3140,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 16\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2189,7 +3148,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2197,7 +3156,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 528\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2205,7 +3164,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 256\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2213,7 +3172,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2221,7 +3180,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2229,7 +3188,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2237,7 +3196,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n@@ -2245,7 +3204,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n@@ -2253,7 +3212,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 2\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n@@ -2261,15 +3220,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n-\t.count                   = 4\n+\t.count                   = 512\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n@@ -2277,7 +3236,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 1024\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2285,7 +3244,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2293,7 +3252,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 2\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2301,7 +3260,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2309,7 +3268,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -2317,7 +3276,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2325,7 +3284,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 512\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2333,7 +3292,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 256\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2341,7 +3300,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2349,7 +3308,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2357,7 +3316,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2365,7 +3324,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n@@ -2373,7 +3332,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n@@ -2381,7 +3340,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 2\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n@@ -2389,7 +3348,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n@@ -2397,7 +3356,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 4\n \t},\n \t{\n-\t.app_id                  = 1,\n+\t.app_id                  = 2,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n@@ -2405,532 +3364,596 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {\n \t.count                   = 1024\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_L2_CTXT_HIGH,\n-\t.count                   = 32\n+\t.count                   = 422\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_L2_CTXT_LOW,\n-\t.count                   = 2\n+\t.count                   = 6\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n-\t.count                   = 4\n+\t.count                   = 191\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n-\t.count                   = 4\n+\t.count                   = 63\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n-\t.count                   = 4\n+\t.count                   = 192\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t.count                   = 128\n+\t.count                   = 8192\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n-\t.count                   = 128\n+\t.count                   = 7168\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_MODIFY_IPV4,\n-\t.count                   = 4\n+\t.count                   = 1023\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_8B,\n-\t.count                   = 4\n+\t.count                   = 511\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_16B,\n-\t.count                   = 4\n+\t.count                   = 15\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC,\n-\t.count                   = 4\n+\t.count                   = 255\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_MIRROR_CONFIG,\n+\t.count                   = 1\n+\t},\n+\t{\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.count                   = 32\n+\t.count                   = 422\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.count                   = 2\n+\t.count                   = 6\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.count                   = 32\n+\t.count                   = 960\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n-\t.count                   = 64\n+\t.count                   = 88\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n \t.resource_type           = TF_EM_TBL_TYPE_EM_RECORD,\n-\t.count                   = 1024\n+\t.count                   = 13168\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n+\t.resource_type           = TF_EM_TBL_TYPE_TBL_SCOPE,\n+\t.count                   = 1\n+\t},\n+\t{\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_L2_CTXT_HIGH,\n-\t.count                   = 32\n+\t.count                   = 292\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_L2_CTXT_LOW,\n-\t.count                   = 2\n+\t.count                   = 148\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n-\t.count                   = 4\n+\t.count                   = 191\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n-\t.count                   = 4\n+\t.count                   = 63\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n-\t.count                   = 4\n+\t.count                   = 192\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t.count                   = 128\n+\t.count                   = 8192\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n-\t.count                   = 128\n+\t.count                   = 7168\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_MODIFY_IPV4,\n-\t.count                   = 4\n+\t.count                   = 1023\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_64B,\n-\t.count                   = 4\n+\t.count                   = 511\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_16B,\n-\t.count                   = 4\n+\t.count                   = 223\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_8B,\n-\t.count                   = 4\n+\t.count                   = 255\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n-\t.count                   = 4\n+\t.count                   = 488\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,\n-\t.count                   = 4\n+\t.count                   = 511\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_MIRROR_CONFIG,\n+\t.count                   = 1\n+\t},\n+\t{\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.count                   = 32\n+\t.count                   = 292\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.count                   = 2\n+\t.count                   = 144\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.count                   = 32\n+\t.count                   = 960\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n-\t.count                   = 4\n+\t.count                   = 928\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n \t.resource_type           = TF_EM_TBL_TYPE_EM_RECORD,\n-\t.count                   = 1024\n+\t.count                   = 15232\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n+\t.resource_type           = TF_EM_TBL_TYPE_TBL_SCOPE,\n+\t.count                   = 1\n+\t},\n+\t{\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_L2_CTXT_HIGH,\n-\t.count                   = 32\n+\t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_L2_CTXT_LOW,\n-\t.count                   = 2\n+\t.count                   = 6\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n-\t.count                   = 32\n+\t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n-\t.count                   = 16\n+\t.count                   = 63\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n-\t.count                   = 32\n+\t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t.count                   = 528\n+\t.count                   = 4096\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n-\t.count                   = 256\n+\t.count                   = 1024\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_MIRROR_CONFIG,\n+\t.count                   = 1\n+\t},\n+\t{\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_EM_FKB,\n-\t.count                   = 4\n+\t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_WC_FKB,\n-\t.count                   = 4\n+\t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_64B,\n-\t.count                   = 4\n+\t.count                   = 1024\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n-\t.count                   = 4\n+\t.count                   = 1024\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_RX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_MODIFY_64B,\n+\t.count                   = 1024\n+\t},\n+\t{\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.count                   = 32\n+\t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.count                   = 2\n+\t.count                   = 6\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.count                   = 32\n+\t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n-\t.count                   = 512\n+\t.count                   = 2048\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_RX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n \t.resource_type           = TF_EM_TBL_TYPE_EM_RECORD,\n-\t.count                   = 1024\n+\t.count                   = 6144\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_L2_CTXT_HIGH,\n-\t.count                   = 32\n+\t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_L2_CTXT_LOW,\n-\t.count                   = 2\n+\t.count                   = 6\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_WC_PROF,\n-\t.count                   = 4\n+\t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_PROF_FUNC,\n-\t.count                   = 4\n+\t.count                   = 63\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n \t.resource_type           = TF_IDENT_TYPE_EM_PROF,\n-\t.count                   = 4\n+\t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t.count                   = 512\n+\t.count                   = 4096\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_STATS_64,\n-\t.count                   = 256\n+\t.count                   = 1024\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_MIRROR_CONFIG,\n+\t.count                   = 1\n+\t},\n+\t{\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_EM_FKB,\n-\t.count                   = 4\n+\t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_WC_FKB,\n-\t.count                   = 4\n+\t.count                   = 32\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_ENCAP_64B,\n-\t.count                   = 4\n+\t.count                   = 1024\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type           = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n-\t.count                   = 4\n+\t.count                   = 1024\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n+\t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n+\t.direction               = TF_DIR_TX,\n+\t.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type           = TF_TBL_TYPE_ACT_MODIFY_64B,\n+\t.count                   = 1024\n+\t},\n+\t{\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.count                   = 32\n+\t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.count                   = 2\n+\t.count                   = 6\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.count                   = 32\n+\t.count                   = 128\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type           = TF_TCAM_TBL_TYPE_WC_TCAM,\n-\t.count                   = 4\n+\t.count                   = 2048\n \t},\n \t{\n-\t.app_id                  = 2,\n+\t.app_id                  = 3,\n \t.device_id               = BNXT_ULP_DEVICE_ID_THOR,\n \t.direction               = TF_DIR_TX,\n \t.resource_func           = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n \t.resource_type           = TF_EM_TBL_TYPE_EM_RECORD,\n-\t.count                   = 1024\n+\t.count                   = 6144\n \t}\n };\n \n@@ -3322,25 +4345,23 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[4229] = 21,\n \t[4231] = 22,\n \t[4244] = 2,\n-\t[4245] = 23,\n \t[4246] = 3,\n-\t[4247] = 24,\n \t[4248] = 4,\n-\t[4249] = 25,\n \t[4250] = 5,\n-\t[4251] = 26,\n \t[4252] = 6,\n-\t[4253] = 27,\n \t[4254] = 7,\n-\t[4255] = 28,\n \t[4256] = 8,\n-\t[4257] = 29,\n \t[4258] = 9,\n-\t[4259] = 30,\n \t[4260] = 10,\n-\t[4261] = 31,\n \t[4262] = 11,\n-\t[4263] = 32,\n+\t[4265] = 23,\n+\t[4267] = 24,\n+\t[4269] = 25,\n+\t[4271] = 26,\n+\t[4273] = 27,\n+\t[4275] = 28,\n+\t[4277] = 29,\n+\t[4279] = 30,\n \t[4298] = 12,\n \t[4300] = 13,\n \t[4302] = 14,\n@@ -3374,15 +4395,6 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[4389] = 31,\n \t[4390] = 11,\n \t[4391] = 32,\n-\t[4409] = 33,\n-\t[4411] = 34,\n-\t[4413] = 35,\n-\t[4415] = 36,\n-\t[4417] = 37,\n-\t[4419] = 38,\n-\t[4421] = 39,\n-\t[4423] = 40,\n-\t[4425] = 41,\n \t[4426] = 12,\n \t[4428] = 13,\n \t[4430] = 14,\n@@ -3397,33 +4409,36 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[4485] = 21,\n \t[4487] = 22,\n \t[4500] = 2,\n-\t[4501] = 23,\n \t[4502] = 3,\n-\t[4503] = 24,\n \t[4504] = 4,\n-\t[4505] = 25,\n \t[4506] = 5,\n-\t[4507] = 26,\n \t[4508] = 6,\n-\t[4509] = 27,\n \t[4510] = 7,\n-\t[4511] = 28,\n \t[4512] = 8,\n-\t[4513] = 29,\n \t[4514] = 9,\n-\t[4515] = 30,\n \t[4516] = 10,\n-\t[4517] = 31,\n \t[4518] = 11,\n-\t[4519] = 32,\n+\t[4521] = 23,\n+\t[4523] = 24,\n+\t[4525] = 25,\n+\t[4527] = 26,\n+\t[4529] = 27,\n+\t[4531] = 28,\n+\t[4533] = 29,\n+\t[4535] = 30,\n+\t[4537] = 31,\n+\t[4539] = 32,\n+\t[4541] = 33,\n+\t[4543] = 34,\n+\t[4545] = 35,\n+\t[4547] = 36,\n+\t[4549] = 37,\n+\t[4551] = 38,\n+\t[4553] = 39,\n \t[4554] = 12,\n-\t[4555] = 33,\n \t[4556] = 13,\n-\t[4557] = 34,\n \t[4558] = 14,\n-\t[4559] = 35,\n \t[4560] = 15,\n-\t[4561] = 36,\n \t[4574] = 16,\n \t[4575] = 17,\n \t[4576] = 18,\n@@ -3433,11 +4448,6 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[4611] = 20,\n \t[4613] = 21,\n \t[4615] = 22,\n-\t[4619] = 33,\n-\t[4621] = 34,\n-\t[4623] = 35,\n-\t[4625] = 36,\n-\t[4627] = 37,\n \t[4628] = 2,\n \t[4629] = 23,\n \t[4630] = 3,\n@@ -3458,6 +4468,15 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[4645] = 31,\n \t[4646] = 11,\n \t[4647] = 32,\n+\t[4665] = 33,\n+\t[4667] = 34,\n+\t[4669] = 35,\n+\t[4671] = 36,\n+\t[4673] = 37,\n+\t[4675] = 38,\n+\t[4677] = 39,\n+\t[4679] = 40,\n+\t[4681] = 41,\n \t[4682] = 12,\n \t[4684] = 13,\n \t[4686] = 14,\n@@ -3466,6 +4485,116 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[4703] = 17,\n \t[4704] = 18,\n \t[4705] = 19,\n+\t[4736] = 0,\n+\t[4737] = 1,\n+\t[4739] = 20,\n+\t[4741] = 21,\n+\t[4743] = 22,\n+\t[4756] = 2,\n+\t[4758] = 3,\n+\t[4760] = 4,\n+\t[4762] = 5,\n+\t[4764] = 6,\n+\t[4766] = 7,\n+\t[4768] = 8,\n+\t[4770] = 9,\n+\t[4772] = 10,\n+\t[4774] = 11,\n+\t[4777] = 23,\n+\t[4779] = 24,\n+\t[4781] = 25,\n+\t[4783] = 26,\n+\t[4785] = 27,\n+\t[4787] = 28,\n+\t[4789] = 29,\n+\t[4791] = 30,\n+\t[4810] = 12,\n+\t[4811] = 31,\n+\t[4812] = 13,\n+\t[4813] = 32,\n+\t[4814] = 14,\n+\t[4815] = 33,\n+\t[4816] = 15,\n+\t[4817] = 34,\n+\t[4830] = 16,\n+\t[4831] = 17,\n+\t[4832] = 18,\n+\t[4833] = 19,\n+\t[4864] = 0,\n+\t[4865] = 1,\n+\t[4867] = 20,\n+\t[4869] = 21,\n+\t[4871] = 22,\n+\t[4884] = 2,\n+\t[4885] = 23,\n+\t[4886] = 3,\n+\t[4887] = 24,\n+\t[4888] = 4,\n+\t[4889] = 25,\n+\t[4890] = 5,\n+\t[4891] = 26,\n+\t[4892] = 6,\n+\t[4893] = 27,\n+\t[4894] = 7,\n+\t[4895] = 28,\n+\t[4896] = 8,\n+\t[4897] = 29,\n+\t[4898] = 9,\n+\t[4899] = 30,\n+\t[4900] = 10,\n+\t[4901] = 31,\n+\t[4902] = 11,\n+\t[4903] = 32,\n+\t[4938] = 12,\n+\t[4939] = 33,\n+\t[4940] = 13,\n+\t[4941] = 34,\n+\t[4942] = 14,\n+\t[4943] = 35,\n+\t[4944] = 15,\n+\t[4945] = 36,\n+\t[4958] = 16,\n+\t[4959] = 17,\n+\t[4960] = 18,\n+\t[4961] = 19,\n+\t[4992] = 0,\n+\t[4993] = 1,\n+\t[4995] = 20,\n+\t[4997] = 21,\n+\t[4999] = 22,\n+\t[5003] = 33,\n+\t[5005] = 34,\n+\t[5007] = 35,\n+\t[5009] = 36,\n+\t[5011] = 37,\n+\t[5012] = 2,\n+\t[5013] = 23,\n+\t[5014] = 3,\n+\t[5015] = 24,\n+\t[5016] = 4,\n+\t[5017] = 25,\n+\t[5018] = 5,\n+\t[5019] = 26,\n+\t[5020] = 6,\n+\t[5021] = 27,\n+\t[5022] = 7,\n+\t[5023] = 28,\n+\t[5024] = 8,\n+\t[5025] = 29,\n+\t[5026] = 9,\n+\t[5027] = 30,\n+\t[5028] = 10,\n+\t[5029] = 31,\n+\t[5030] = 11,\n+\t[5031] = 32,\n+\t[5066] = 12,\n+\t[5068] = 13,\n+\t[5070] = 14,\n+\t[5072] = 15,\n+\t[5086] = 16,\n+\t[5087] = 17,\n+\t[5088] = 18,\n+\t[5089] = 19,\n \t[6144] = 0,\n \t[6145] = 1,\n \t[6146] = 2,\n@@ -3705,4 +4834,3 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[7638] = 6,\n \t[7642] = 7\n };\n-\ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c\nindex 223ecbf843..e49c1151d3 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Thu Jul  8 08:44:00 2021 */\n+/* date: Tue Aug 17 12:16:42 2021 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {\n \t/* act_tid: 1, ingress */\n \t[1] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_THOR,\n-\t.num_tbls = 4,\n+\t.num_tbls = 5,\n \t.start_tbl_idx = 0,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n@@ -26,7 +26,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {\n \t[2] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_THOR,\n \t.num_tbls = 6,\n-\t.start_tbl_idx = 4,\n+\t.start_tbl_idx = 5,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n \t\t.cond_start_idx = 3,\n@@ -36,7 +36,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {\n \t[3] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_THOR,\n \t.num_tbls = 4,\n-\t.start_tbl_idx = 10,\n+\t.start_tbl_idx = 11,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n \t\t.cond_start_idx = 4,\n@@ -45,8 +45,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {\n \t/* act_tid: 4, egress */\n \t[4] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_THOR,\n-\t.num_tbls = 4,\n-\t.start_tbl_idx = 14,\n+\t.num_tbls = 5,\n+\t.start_tbl_idx = 15,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n \t\t.cond_start_idx = 7,\n@@ -56,20 +56,20 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {\n \t[5] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_THOR,\n \t.num_tbls = 4,\n-\t.start_tbl_idx = 18,\n+\t.start_tbl_idx = 20,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 12,\n \t\t.cond_nums = 0 }\n \t},\n \t/* act_tid: 6, egress */\n \t[6] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_THOR,\n-\t.num_tbls = 6,\n-\t.start_tbl_idx = 22,\n+\t.num_tbls = 12,\n+\t.start_tbl_idx = 24,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 13,\n+\t\t.cond_start_idx = 15,\n \t\t.cond_nums = 0 }\n \t}\n };\n@@ -125,14 +125,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 1,\n+\t\t.cond_false_goto = 2,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n \t\t.cond_start_idx = 2,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.record_size = 64,\n \t.result_start_idx = 1,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n@@ -146,7 +145,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 0,\n-\t\t.cond_false_goto = 0,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 3,\n \t\t.cond_nums = 0 },\n@@ -158,6 +157,26 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.result_bit_size = 128,\n \t.result_num_fields = 17\n \t},\n+\t{ /* act_tid: 1, , table: int_compact_act_record.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 3,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.result_start_idx = 65,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 13\n+\t},\n \t{ /* act_tid: 2, , table: control.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n \t.direction = TF_DIR_RX,\n@@ -187,7 +206,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 65,\n+\t.result_start_idx = 78,\n \t.result_bit_size = 32,\n \t.result_num_fields = 5\n \t},\n@@ -208,13 +227,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 70,\n+\t.result_start_idx = 83,\n \t.result_bit_size = 64,\n \t.result_num_fields = 1\n \t},\n-\t{ /* act_tid: 2, , table: int_full_act_record.0 */\n+\t{ /* act_tid: 2, , table: int_compact_act_record.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_RX,\n@@ -229,9 +248,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 71,\n-\t.result_bit_size = 128,\n-\t.result_num_fields = 17,\n+\t.result_start_idx = 84,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 13,\n \t.encap_num_fields = 0\n \t},\n \t{ /* act_tid: 2, , table: mirror_tbl.wr */\n@@ -250,7 +269,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 88,\n+\t.result_start_idx = 97,\n \t.result_bit_size = 32,\n \t.result_num_fields = 5\n \t},\n@@ -273,7 +292,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.blob_key_bit_size = 1,\n \t.key_bit_size = 1,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 93,\n+\t.result_start_idx = 102,\n \t.result_bit_size = 36,\n \t.result_num_fields = 2\n \t},\n@@ -292,7 +311,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.result_start_idx = 95,\n+\t.result_start_idx = 104,\n \t.result_bit_size = 64,\n \t.result_num_fields = 1\n \t},\n@@ -311,8 +330,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.record_size = 64,\n-\t.result_start_idx = 96,\n+\t.result_start_idx = 105,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n \t.encap_num_fields = 47\n@@ -332,8 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.record_size = 64,\n-\t.result_start_idx = 143,\n+\t.result_start_idx = 152,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n \t.encap_num_fields = 47\n@@ -353,7 +370,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.result_start_idx = 190,\n+\t.result_start_idx = 199,\n \t.result_bit_size = 128,\n \t.result_num_fields = 17\n \t},\n@@ -372,7 +389,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.result_start_idx = 207,\n+\t.result_start_idx = 216,\n \t.result_bit_size = 64,\n \t.result_num_fields = 1\n \t},\n@@ -391,8 +408,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.record_size = 8,\n-\t.result_start_idx = 208,\n+\t.result_start_idx = 217,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n \t.encap_num_fields = 11\n@@ -412,8 +428,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.record_size = 64,\n-\t.result_start_idx = 219,\n+\t.result_start_idx = 228,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n \t.encap_num_fields = 47\n@@ -426,17 +441,36 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 0,\n-\t\t.cond_false_goto = 0,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 10,\n-\t\t.cond_nums = 0 },\n+\t\t.cond_nums = 2 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.result_start_idx = 266,\n+\t.result_start_idx = 275,\n \t.result_bit_size = 128,\n \t.result_num_fields = 17\n \t},\n+\t{ /* act_tid: 4, , table: int_compact_act_record.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 12,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 292,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 13\n+\t},\n \t{ /* act_tid: 5, , table: int_flow_counter_tbl.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_ACT_STATS_64,\n@@ -447,12 +481,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 12,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.result_start_idx = 283,\n+\t.result_start_idx = 305,\n \t.result_bit_size = 64,\n \t.result_num_fields = 1\n \t},\n@@ -466,13 +500,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t\t.cond_true_goto  = 2,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 11,\n+\t\t.cond_start_idx = 13,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.record_size = 64,\n-\t.result_start_idx = 284,\n+\t.result_start_idx = 306,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n \t.encap_num_fields = 47\n@@ -487,13 +520,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 12,\n+\t\t.cond_start_idx = 14,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.record_size = 64,\n-\t.result_start_idx = 331,\n+\t.result_start_idx = 353,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n \t.encap_num_fields = 47\n@@ -508,12 +540,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t\t.cond_true_goto  = 0,\n \t\t.cond_false_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 13,\n+\t\t.cond_start_idx = 15,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.result_start_idx = 378,\n+\t.result_start_idx = 400,\n \t.result_bit_size = 128,\n \t.result_num_fields = 17\n \t},\n@@ -527,15 +559,48 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 13,\n+\t\t.cond_start_idx = 15,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.result_start_idx = 395,\n+\t.result_start_idx = 417,\n \t.result_bit_size = 64,\n \t.result_num_fields = 1\n \t},\n+\t{ /* act_tid: 6, , table: source_property_cache.rd */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 16,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 2,\n+\t.blob_key_bit_size = 80,\n+\t.key_bit_size = 80,\n+\t.key_num_fields = 2,\n+\t.ident_start_idx = 1,\n+\t.ident_nums = 1\n+\t},\n+\t{ /* act_tid: 6, , table: control.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 3,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 17,\n+\t\t.cond_nums = 1 },\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID\n+\t},\n \t{ /* act_tid: 6, , table: sp_smac_ipv4.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n@@ -546,17 +611,40 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 14,\n+\t\t.cond_start_idx = 18,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.record_size = 16,\n-\t.result_start_idx = 396,\n+\t.result_start_idx = 418,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n \t.encap_num_fields = 3\n \t},\n+\t{ /* act_tid: 6, , table: source_property_cache.wr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 19,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 4,\n+\t.blob_key_bit_size = 80,\n+\t.key_bit_size = 80,\n+\t.key_num_fields = 2,\n+\t.result_start_idx = 421,\n+\t.result_bit_size = 48,\n+\t.result_num_fields = 2\n+\t},\n \t{ /* act_tid: 6, , table: sp_smac_ipv6.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,\n@@ -567,17 +655,50 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 15,\n+\t\t.cond_start_idx = 19,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.record_size = 32,\n-\t.result_start_idx = 399,\n+\t.result_start_idx = 423,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n \t.encap_num_fields = 3\n \t},\n+\t{ /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 20,\n+\t\t.cond_nums = 2 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 6,\n+\t.blob_key_bit_size = 136,\n+\t.key_bit_size = 136,\n+\t.key_num_fields = 5,\n+\t.ident_start_idx = 2,\n+\t.ident_nums = 1\n+\t},\n+\t{ /* act_tid: 6, , table: control.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 3,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 22,\n+\t\t.cond_nums = 1 },\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID\n+\t},\n \t{ /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,\n@@ -588,17 +709,39 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 16,\n+\t\t.cond_start_idx = 23,\n \t\t.cond_nums = 2 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.record_size = 64,\n-\t.result_start_idx = 402,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.result_start_idx = 426,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n \t.encap_num_fields = 30\n \t},\n+\t{ /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 25,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 11,\n+\t.blob_key_bit_size = 136,\n+\t.key_bit_size = 136,\n+\t.key_num_fields = 5,\n+\t.result_start_idx = 456,\n+\t.result_bit_size = 48,\n+\t.result_num_fields = 2\n+\t},\n \t{ /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,\n@@ -609,13 +752,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 18,\n+\t\t.cond_start_idx = 25,\n \t\t.cond_nums = 2 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.record_size = 64,\n-\t.result_start_idx = 432,\n+\t.result_start_idx = 458,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n \t.encap_num_fields = 30\n@@ -630,13 +772,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {\n \t\t.cond_true_goto  = 0,\n \t\t.cond_false_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 20,\n+\t\t.cond_start_idx = 27,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 462,\n+\t.result_start_idx = 488,\n \t.result_bit_size = 128,\n \t.result_num_fields = 17\n \t}\n@@ -693,6 +835,15 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {\n \t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n \t.cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL\n \t},\n+\t/* cond_execute: act_tid: 4, int_full_act_record.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN\n+\t},\n \t/* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n@@ -713,6 +864,16 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {\n \t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n \t.cond_operand = BNXT_ULP_ACT_BIT_COUNT\n \t},\n+\t/* cond_execute: act_tid: 6, source_property_cache.rd */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n+\t.cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG\n+\t},\n+\t/* cond_execute: act_tid: 6, control.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n+\t},\n \t/* cond_execute: act_tid: 6, sp_smac_ipv4.0 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n@@ -723,6 +884,20 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {\n \t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG\n \t},\n+\t/* cond_execute: act_tid: 6, vxlan_encap_rec_cache.rd */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN\n+\t},\n+\t/* cond_execute: act_tid: 6, control.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n+\t},\n \t/* cond_execute: act_tid: 6, int_tun_encap_record.ipv4_vxlan */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,\n@@ -783,6 +958,316 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = {\n \t\t(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,\n \t\tBNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}\n \t\t}\n+\t},\n+\t/* act_tid: 6, , table: source_property_cache.rd */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"ipv4_src_addr\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"ipv4_src_addr\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}\n+\t\t}\n+\t},\n+\t/* act_tid: 6, , table: source_property_cache.wr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"ipv4_src_addr\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"ipv4_src_addr\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}\n+\t\t}\n+\t},\n+\t/* act_tid: 6, , table: vxlan_encap_rec_cache.rd */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"ipv4_dst_addr\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"ipv4_dst_addr\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"udp_sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"udp_sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"udp_dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"udp_dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"vni\",\n+\t\t.field_bit_size = 24,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"vni\",\n+\t\t.field_bit_size = 24,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,\n+\t\tBNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}\n+\t\t}\n+\t},\n+\t/* act_tid: 6, , table: vxlan_encap_rec_cache.wr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"ipv4_dst_addr\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"ipv4_dst_addr\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"udp_sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"udp_sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"udp_dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"udp_dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"vni\",\n+\t\t.field_bit_size = 24,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"vni\",\n+\t\t.field_bit_size = 24,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,\n+\t\tBNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}\n+\t\t}\n \t}\n };\n \n@@ -1069,38 +1554,178 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"encap_ptr\",\n-\t.field_bit_size = 16,\n+\t.description = \"encap_ptr\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"mod_rec_ptr\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,\n+\t(uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr2 = {\n+\t\t(BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},\n+\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"rsvd1\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"rsvd0\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"decap_func\",\n+\t.field_bit_size = 5,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,\n+\t(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr2 = {\n+\t\tULP_THOR_SYM_DECAP_FUNC_THRU_TUN},\n+\t.field_src3 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr3 = {\n+\tULP_THOR_SYM_DECAP_FUNC_NONE}\n+\t},\n+\t{\n+\t.description = \"meter\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"stats_op\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"stats_ptr\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"vnic_or_vport\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n+\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n+\t},\n+\t{\n+\t.description = \"use_default\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"mirror\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,\n+\t(uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr2 = {\n+\t\t(BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},\n+\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"cond_copy\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"mod_rec_ptr\",\n-\t.field_bit_size = 16,\n+\t.description = \"vlan_del_rpt\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n \t.field_opr1 = {\n-\t((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,\n-\t((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,\n-\t((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,\n-\t((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,\n-\t((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,\n-\t((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,\n-\t((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,\n-\t(uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_RF,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,\n+\t(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr2 = {\n-\t\t(BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},\n+\t\tULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},\n \t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"rsvd1\",\n-\t.field_bit_size = 16,\n+\t.description = \"drop\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,\n+\t(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}\n+\t},\n+\t{\n+\t.description = \"hit\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n+\t.description = \"type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t/* act_tid: 1, , table: int_compact_act_record.0 */\n+\t{\n \t.description = \"rsvd0\",\n \t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n@@ -1137,7 +1762,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {\n \t.description = \"stats_op\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"stats_ptr\",\n@@ -1233,9 +1860,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {\n \t.description = \"type\",\n \t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t/* act_tid: 2, , table: mirror_tbl.alloc */\n \t{\n@@ -1277,31 +1902,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* act_tid: 2, , table: int_full_act_record.0 */\n-\t{\n-\t.description = \"sp_rec_ptr\",\n-\t.field_bit_size = 16,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"encap_ptr\",\n-\t.field_bit_size = 16,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"mod_rec_ptr\",\n-\t.field_bit_size = 16,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"rsvd1\",\n-\t.field_bit_size = 16,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n+\t/* act_tid: 2, , table: int_compact_act_record.0 */\n \t{\n \t.description = \"rsvd0\",\n \t.field_bit_size = 8,\n@@ -1324,7 +1925,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {\n \t.description = \"stats_op\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"stats_ptr\",\n@@ -1387,9 +1990,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {\n \t.description = \"type\",\n \t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t/* act_tid: 2, , table: mirror_tbl.wr */\n \t{\n@@ -2250,7 +2851,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {\n \t.description = \"stats_op\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"stats_ptr\",\n@@ -2721,16 +3324,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {\n \t.description = \"stats_op\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,\n-\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,\n-\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,\n-\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,\n-\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,\n-\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,\n-\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,\n-\t(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}\n+\t1}\n \t},\n \t{\n \t.description = \"stats_ptr\",\n@@ -2803,6 +3399,102 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {\n \t.field_opr1 = {\n \t1}\n \t},\n+\t/* act_tid: 4, , table: int_compact_act_record.0 */\n+\t{\n+\t.description = \"rsvd0\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"decap_func\",\n+\t.field_bit_size = 5,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"stats_op\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"stats_ptr\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"vnic_or_vport\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,\n+\tBNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}\n+\t},\n+\t{\n+\t.description = \"use_default\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"mirror\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"cond_copy\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vlan_del_rpt\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"drop\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,\n+\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,\n+\t(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}\n+\t},\n+\t{\n+\t.description = \"hit\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n \t/* act_tid: 5, , table: int_flow_counter_tbl.0 */\n \t{\n \t.description = \"count\",\n@@ -3708,6 +4400,25 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* act_tid: 6, , table: source_property_cache.wr */\n+\t{\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_RID & 0xff}\n+\t},\n+\t{\n+\t.description = \"sp_rec_ptr\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}\n+\t},\n \t/* act_tid: 6, , table: sp_smac_ipv6.0 */\n \t{\n \t.description = \"smac\",\n@@ -4021,6 +4732,25 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {\n \t(BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,\n \tBNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}\n \t},\n+\t/* act_tid: 6, , table: vxlan_encap_rec_cache.wr */\n+\t{\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_RID & 0xff}\n+\t},\n+\t{\n+\t.description = \"enc_rec_ptr\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}\n+\t},\n \t/* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */\n \t{\n \t.description = \"ecv_valid\",\n@@ -4351,7 +5081,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {\n \t.description = \"stats_op\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"stats_ptr\",\n@@ -4424,5 +5156,19 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = {\n \t.regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,\n \t.ident_bit_size = 4,\n \t.ident_bit_pos = 32\n+\t},\n+\t/* act_tid: 6, , table: source_property_cache.rd */\n+\t{\n+\t.description = \"sp_rec_ptr\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_MAIN_SP_PTR,\n+\t.ident_bit_size = 16,\n+\t.ident_bit_pos = 32\n+\t},\n+\t/* act_tid: 6, , table: vxlan_encap_rec_cache.rd */\n+\t{\n+\t.description = \"enc_rec_ptr\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n+\t.ident_bit_size = 16,\n+\t.ident_bit_pos = 32\n \t}\n };\ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c\nindex bcb204ae13..68c1e292b2 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Fri Jul 30 09:57:44 2021 */\n+/* date: Fri Aug 20 18:05:25 2021 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -25,7 +25,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {\n \t/* class_tid: 2, ingress */\n \t[2] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_THOR,\n-\t.num_tbls = 17,\n+\t.num_tbls = 24,\n \t.start_tbl_idx = 28,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n@@ -35,18 +35,18 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {\n \t/* class_tid: 3, egress */\n \t[3] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_THOR,\n-\t.num_tbls = 24,\n-\t.start_tbl_idx = 45,\n+\t.num_tbls = 18,\n+\t.start_tbl_idx = 52,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 36,\n+\t\t.cond_start_idx = 39,\n \t\t.cond_nums = 0 }\n \t},\n \t/* class_tid: 4, ingress */\n \t[4] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_THOR,\n \t.num_tbls = 21,\n-\t.start_tbl_idx = 69,\n+\t.start_tbl_idx = 70,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n \t\t.cond_start_idx = 48,\n@@ -55,8 +55,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {\n \t/* class_tid: 5, egress */\n \t[5] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_THOR,\n-\t.num_tbls = 24,\n-\t.start_tbl_idx = 90,\n+\t.num_tbls = 25,\n+\t.start_tbl_idx = 91,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n \t\t.cond_start_idx = 52,\n@@ -855,18 +855,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_bit_size = 62,\n \t.result_num_fields = 4\n \t},\n-\t{ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */\n+\t{ /* class_tid: 2, , table: control.ipv6_check */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 8,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 32,\n+\t\t.cond_nums = 1 },\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP\n+\t},\n+\t{ /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 32,\n-\t\t.cond_nums = 0 },\n+\t\t.cond_false_goto = 1023,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 33,\n+\t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n@@ -875,38 +885,57 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n \t.ident_start_idx = 19,\n-\t.ident_nums = 3\n+\t.ident_nums = 4\n \t},\n-\t{ /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */\n+\t{ /* class_tid: 2, , table: control.f2_ipv6_prof_cache_check */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 4,\n+\t\t.cond_true_goto  = 2,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 32,\n+\t\t.cond_start_idx = 34,\n \t\t.cond_nums = 1 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID\n \t},\n-\t{ /* class_tid: 2, , table: fkb_select.f2_wm */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type = TF_TBL_TYPE_WC_FKB,\n+\t{ /* class_tid: 2, , table: control.f2_v6_conflict_check */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 1,\n+\t\t.cond_true_goto  = 4,\n+\t\t.cond_false_goto = 1023,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 33,\n+\t\t.cond_start_idx = 35,\n \t\t.cond_nums = 1 },\n-\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,\n-\t.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n+\t.func_info = {\n+\t\t.func_opc = BNXT_ULP_FUNC_OPC_EQ,\n+\t\t.func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,\n+\t\t.func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,\n+\t\t.func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,\n+\t\t.func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,\n+\t\t.func_dst_opr = BNXT_ULP_RF_IDX_CC }\n+\t},\n+\t{ /* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_EM_FKB,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 36,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.result_start_idx = 426,\n \t.result_bit_size = 106,\n \t.result_num_fields = 106\n \t},\n-\t{ /* class_tid: 2, , table: profile_tcam.f2 */\n+\t{ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.direction = TF_DIR_RX,\n@@ -914,14 +943,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 34,\n+\t\t.cond_start_idx = 36,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n-\t.pri_operand = 1,\n+\t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n \t.key_start_idx = 1146,\n@@ -930,9 +959,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.key_num_fields = 43,\n \t.result_start_idx = 532,\n \t.result_bit_size = 33,\n-\t.result_num_fields = 8\n+\t.result_num_fields = 8,\n+\t.ident_start_idx = 23,\n+\t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */\n+\t{ /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.resource_sub_type =\n@@ -942,7 +973,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 34,\n+\t\t.cond_start_idx = 36,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n@@ -955,135 +986,81 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_bit_size = 138,\n \t.result_num_fields = 7\n \t},\n-\t{ /* class_tid: 2, , table: wm.l3_l4.ipv4 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,\n+\t{ /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n+\t.resource_type = TF_MEM_INTERNAL,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 0,\n \t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 34,\n-\t\t.cond_nums = 1 },\n-\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 36,\n+\t\t.cond_nums = 0 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n-\t.pri_operand = 0,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n \t.key_start_idx = 1192,\n \t.blob_key_bit_size = 0,\n \t.key_bit_size = 0,\n \t.key_num_fields = 114,\n \t.result_start_idx = 547,\n-\t.result_bit_size = 38,\n-\t.result_num_fields = 5\n-\t},\n-\t{ /* class_tid: 2, , table: wm.l3_l4.ipv6 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 0,\n-\t\t.cond_false_goto = 0,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 35,\n-\t\t.cond_nums = 1 },\n-\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n-\t.pri_operand = 0,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 1306,\n-\t.blob_key_bit_size = 0,\n-\t.key_bit_size = 0,\n-\t.key_num_fields = 114,\n-\t.result_start_idx = 552,\n-\t.result_bit_size = 38,\n-\t.result_num_fields = 5\n-\t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n-\t.direction = TF_DIR_TX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 6,\n-\t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 36,\n-\t\t.cond_nums = 1 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n-\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 1420,\n-\t.blob_key_bit_size = 8,\n-\t.key_bit_size = 8,\n-\t.key_num_fields = 1,\n-\t.ident_start_idx = 22,\n-\t.ident_nums = 1\n+\t.result_bit_size = 0,\n+\t.result_num_fields = 6\n \t},\n-\t{ /* class_tid: 3, , table: mac_addr_cache.rd */\n+\t{ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,\n-\t.direction = TF_DIR_TX,\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 37,\n+\t\t.cond_start_idx = 36,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n-\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 1421,\n-\t.blob_key_bit_size = 73,\n-\t.key_bit_size = 73,\n-\t.key_num_fields = 5,\n-\t.ident_start_idx = 23,\n-\t.ident_nums = 1\n+\t.key_start_idx = 1306,\n+\t.blob_key_bit_size = 14,\n+\t.key_bit_size = 14,\n+\t.key_num_fields = 3,\n+\t.ident_start_idx = 24,\n+\t.ident_nums = 3\n \t},\n-\t{ /* class_tid: 3, , table: control.0 */\n+\t{ /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 4,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 37,\n+\t\t.cond_start_idx = 36,\n \t\t.cond_nums = 1 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID\n \t},\n-\t{ /* class_tid: 3, , table: port_table.egr.rd */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,\n-\t.direction = TF_DIR_TX,\n+\t{ /* class_tid: 2, , table: fkb_select.f2_wm */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_WC_FKB,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 38,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n-\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 37,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,\n+\t.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n-\t.key_start_idx = 1426,\n-\t.blob_key_bit_size = 10,\n-\t.key_bit_size = 10,\n-\t.key_num_fields = 1,\n-\t.ident_start_idx = 24,\n-\t.ident_nums = 3\n+\t.result_start_idx = 553,\n+\t.result_bit_size = 106,\n+\t.result_num_fields = 106\n \t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam.0 */\n+\t{ /* class_tid: 2, , table: profile_tcam.f2 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.direction = TF_DIR_TX,\n+\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n@@ -1091,26 +1068,27 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_start_idx = 38,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n-\t.pri_operand = 0,\n-\t.key_start_idx = 1427,\n-\t.blob_key_bit_size = 213,\n-\t.key_bit_size = 213,\n-\t.key_num_fields = 21,\n-\t.result_start_idx = 557,\n-\t.result_bit_size = 43,\n-\t.result_num_fields = 6,\n-\t.ident_start_idx = 27,\n-\t.ident_nums = 1\n+\t.pri_operand = 1,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n+\t.key_start_idx = 1309,\n+\t.blob_key_bit_size = 94,\n+\t.key_bit_size = 94,\n+\t.key_num_fields = 43,\n+\t.result_start_idx = 659,\n+\t.result_bit_size = 33,\n+\t.result_num_fields = 8\n \t},\n-\t{ /* class_tid: 3, , table: mac_addr_cache.wr */\n+\t{ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,\n-\t.direction = TF_DIR_TX,\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n@@ -1118,15 +1096,61 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_start_idx = 38,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n-\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 1448,\n-\t.blob_key_bit_size = 73,\n-\t.key_bit_size = 73,\n-\t.key_num_fields = 5,\n-\t.result_start_idx = 563,\n-\t.result_bit_size = 62,\n-\t.result_num_fields = 4\n+\t.key_start_idx = 1352,\n+\t.blob_key_bit_size = 14,\n+\t.key_bit_size = 14,\n+\t.key_num_fields = 3,\n+\t.result_start_idx = 667,\n+\t.result_bit_size = 138,\n+\t.result_num_fields = 7\n+\t},\n+\t{ /* class_tid: 2, , table: wm.l3_l4.ipv4 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 38,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n+\t.pri_operand = 0,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n+\t.key_start_idx = 1355,\n+\t.blob_key_bit_size = 0,\n+\t.key_bit_size = 0,\n+\t.key_num_fields = 114,\n+\t.result_start_idx = 674,\n+\t.result_bit_size = 38,\n+\t.result_num_fields = 5\n+\t},\n+\t{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 39,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 1469,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 27,\n+\t.ident_nums = 1\n \t},\n \t{ /* class_tid: 3, , table: control.ipv6_check */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n@@ -1135,7 +1159,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 8,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 38,\n+\t\t.cond_start_idx = 39,\n \t\t.cond_nums = 1 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP\n \t},\n@@ -1148,12 +1172,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1023,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 39,\n+\t\t.cond_start_idx = 40,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 1453,\n+\t.key_start_idx = 1470,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n@@ -1167,7 +1191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_true_goto  = 2,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 40,\n+\t\t.cond_start_idx = 41,\n \t\t.cond_nums = 1 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID\n@@ -1179,7 +1203,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_true_goto  = 4,\n \t\t.cond_false_goto = 1023,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 41,\n+\t\t.cond_start_idx = 42,\n \t\t.cond_nums = 1 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n \t.func_info = {\n@@ -1198,13 +1222,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 42,\n+\t\t.cond_start_idx = 43,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n-\t.result_start_idx = 567,\n+\t.result_start_idx = 679,\n \t.result_bit_size = 106,\n \t.result_num_fields = 106\n \t},\n@@ -1216,7 +1240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 42,\n+\t\t.cond_start_idx = 43,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n@@ -1226,11 +1250,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 1456,\n+\t.key_start_idx = 1473,\n \t.blob_key_bit_size = 94,\n \t.key_bit_size = 94,\n \t.key_num_fields = 43,\n-\t.result_start_idx = 673,\n+\t.result_start_idx = 785,\n \t.result_bit_size = 33,\n \t.result_num_fields = 8,\n \t.ident_start_idx = 32,\n@@ -1246,16 +1270,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 42,\n+\t\t.cond_start_idx = 43,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 1499,\n+\t.key_start_idx = 1516,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n-\t.result_start_idx = 681,\n+\t.result_start_idx = 793,\n \t.result_bit_size = 138,\n \t.result_num_fields = 7\n \t},\n@@ -1267,15 +1291,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_true_goto  = 0,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 42,\n+\t\t.cond_start_idx = 43,\n \t\t.cond_nums = 0 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 1502,\n+\t.key_start_idx = 1519,\n \t.blob_key_bit_size = 0,\n \t.key_bit_size = 0,\n \t.key_num_fields = 114,\n-\t.result_start_idx = 688,\n+\t.result_start_idx = 800,\n \t.result_bit_size = 0,\n \t.result_num_fields = 6\n \t},\n@@ -1288,12 +1312,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 42,\n+\t\t.cond_start_idx = 43,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 1616,\n+\t.key_start_idx = 1633,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n@@ -1304,32 +1328,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 2,\n-\t\t.cond_false_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 5,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 42,\n+\t\t.cond_start_idx = 43,\n \t\t.cond_nums = 1 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID\n \t},\n-\t{ /* class_tid: 3, , table: control.conflict_check */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n-\t.direction = TF_DIR_TX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 5,\n-\t\t.cond_false_goto = 1023,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 43,\n-\t\t.cond_nums = 1 },\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n-\t.func_info = {\n-\t\t.func_opc = BNXT_ULP_FUNC_OPC_EQ,\n-\t\t.func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,\n-\t\t.func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,\n-\t\t.func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,\n-\t\t.func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,\n-\t\t.func_dst_opr = BNXT_ULP_RF_IDX_CC }\n-\t},\n \t{ /* class_tid: 3, , table: fkb_select.l3_l4_wc */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_WC_FKB,\n@@ -1343,7 +1349,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,\n \t.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n-\t.result_start_idx = 694,\n+\t.result_start_idx = 806,\n \t.result_bit_size = 106,\n \t.result_num_fields = 106\n \t},\n@@ -1365,11 +1371,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 1619,\n+\t.key_start_idx = 1636,\n \t.blob_key_bit_size = 94,\n \t.key_bit_size = 94,\n \t.key_num_fields = 43,\n-\t.result_start_idx = 800,\n+\t.result_start_idx = 912,\n \t.result_bit_size = 33,\n \t.result_num_fields = 8,\n \t.ident_start_idx = 35,\n@@ -1393,11 +1399,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 1662,\n+\t.key_start_idx = 1679,\n \t.blob_key_bit_size = 94,\n \t.key_bit_size = 94,\n \t.key_num_fields = 43,\n-\t.result_start_idx = 808,\n+\t.result_start_idx = 920,\n \t.result_bit_size = 33,\n \t.result_num_fields = 8,\n \t.ident_start_idx = 35,\n@@ -1418,11 +1424,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 1705,\n+\t.key_start_idx = 1722,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n-\t.result_start_idx = 816,\n+\t.result_start_idx = 928,\n \t.result_bit_size = 138,\n \t.result_num_fields = 7\n \t},\n@@ -1443,11 +1449,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 1708,\n+\t.key_start_idx = 1725,\n \t.blob_key_bit_size = 0,\n \t.key_bit_size = 0,\n \t.key_num_fields = 114,\n-\t.result_start_idx = 823,\n+\t.result_start_idx = 935,\n \t.result_bit_size = 38,\n \t.result_num_fields = 5\n \t},\n@@ -1468,11 +1474,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 1822,\n+\t.key_start_idx = 1839,\n \t.blob_key_bit_size = 0,\n \t.key_bit_size = 0,\n \t.key_num_fields = 114,\n-\t.result_start_idx = 828,\n+\t.result_start_idx = 940,\n \t.result_bit_size = 38,\n \t.result_num_fields = 5\n \t},\n@@ -1493,11 +1499,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 1936,\n+\t.key_start_idx = 1953,\n \t.blob_key_bit_size = 0,\n \t.key_bit_size = 0,\n \t.key_num_fields = 114,\n-\t.result_start_idx = 833,\n+\t.result_start_idx = 945,\n \t.result_bit_size = 38,\n \t.result_num_fields = 5\n \t},\n@@ -1517,7 +1523,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 838,\n+\t.result_start_idx = 950,\n \t.result_bit_size = 128,\n \t.result_num_fields = 17\n \t},\n@@ -1535,11 +1541,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 2050,\n+\t.key_start_idx = 2067,\n \t.blob_key_bit_size = 10,\n \t.key_bit_size = 10,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 855,\n+\t.result_start_idx = 967,\n \t.result_bit_size = 152,\n \t.result_num_fields = 5\n \t},\n@@ -1557,7 +1563,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 2051,\n+\t.key_start_idx = 2068,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n@@ -1594,11 +1600,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 2052,\n+\t.key_start_idx = 2069,\n \t.blob_key_bit_size = 213,\n \t.key_bit_size = 213,\n \t.key_num_fields = 21,\n-\t.result_start_idx = 860,\n+\t.result_start_idx = 972,\n \t.result_bit_size = 43,\n \t.result_num_fields = 6,\n \t.ident_start_idx = 35,\n@@ -1618,11 +1624,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 2073,\n+\t.key_start_idx = 2090,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 866,\n+\t.result_start_idx = 978,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4\n \t},\n@@ -1639,7 +1645,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n-\t.result_start_idx = 870,\n+\t.result_start_idx = 982,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n@@ -1656,7 +1662,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n-\t.result_start_idx = 871,\n+\t.result_start_idx = 983,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n@@ -1676,7 +1682,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 872,\n+\t.result_start_idx = 984,\n \t.result_bit_size = 128,\n \t.result_num_fields = 17,\n \t.encap_num_fields = 0\n@@ -1695,11 +1701,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 2074,\n+\t.key_start_idx = 2091,\n \t.blob_key_bit_size = 10,\n \t.key_bit_size = 10,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 889,\n+\t.result_start_idx = 1001,\n \t.result_bit_size = 152,\n \t.result_num_fields = 5\n \t},\n@@ -1728,7 +1734,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 2075,\n+\t.key_start_idx = 2092,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n@@ -1761,7 +1767,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n-\t.result_start_idx = 894,\n+\t.result_start_idx = 1006,\n \t.result_bit_size = 64,\n \t.result_num_fields = 8\n \t},\n@@ -1779,11 +1785,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 2076,\n+\t.key_start_idx = 2093,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 902,\n+\t.result_start_idx = 1014,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4\n \t},\n@@ -1801,7 +1807,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 2077,\n+\t.key_start_idx = 2094,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n@@ -1836,11 +1842,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 2078,\n+\t.key_start_idx = 2095,\n \t.blob_key_bit_size = 213,\n \t.key_bit_size = 213,\n \t.key_num_fields = 21,\n-\t.result_start_idx = 906,\n+\t.result_start_idx = 1018,\n \t.result_bit_size = 43,\n \t.result_num_fields = 6,\n \t.ident_start_idx = 36,\n@@ -1860,11 +1866,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 2099,\n+\t.key_start_idx = 2116,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 912,\n+\t.result_start_idx = 1024,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4\n \t},\n@@ -1881,7 +1887,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.result_start_idx = 916,\n+\t.result_start_idx = 1028,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n@@ -1898,7 +1904,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.result_start_idx = 917,\n+\t.result_start_idx = 1029,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n@@ -1918,11 +1924,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 918,\n+\t.result_start_idx = 1030,\n \t.result_bit_size = 128,\n \t.result_num_fields = 17,\n \t.encap_num_fields = 0\n \t},\n+\t{ /* class_tid: 5, , table: port_table.egr_wr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 52,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 2117,\n+\t.blob_key_bit_size = 10,\n+\t.key_bit_size = 10,\n+\t.key_num_fields = 1,\n+\t.result_start_idx = 1047,\n+\t.result_bit_size = 152,\n+\t.result_num_fields = 5\n+\t},\n \t{ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n@@ -1937,7 +1965,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 2100,\n+\t.key_start_idx = 2118,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n@@ -1972,11 +2000,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n-\t.key_start_idx = 2101,\n+\t.key_start_idx = 2119,\n \t.blob_key_bit_size = 213,\n \t.key_bit_size = 213,\n \t.key_num_fields = 21,\n-\t.result_start_idx = 935,\n+\t.result_start_idx = 1052,\n \t.result_bit_size = 43,\n \t.result_num_fields = 6,\n \t.ident_start_idx = 37,\n@@ -1996,11 +2024,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 2122,\n+\t.key_start_idx = 2140,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 941,\n+\t.result_start_idx = 1058,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4\n \t},\n@@ -2017,7 +2045,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,\n \t.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.result_start_idx = 945,\n+\t.result_start_idx = 1062,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n@@ -2034,7 +2062,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,\n \t.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.result_start_idx = 946,\n+\t.result_start_idx = 1063,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n@@ -2054,7 +2082,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,\n-\t.result_start_idx = 947,\n+\t.result_start_idx = 1064,\n \t.result_bit_size = 128,\n \t.result_num_fields = 17,\n \t.encap_num_fields = 0\n@@ -2072,7 +2100,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.result_start_idx = 964,\n+\t.result_start_idx = 1081,\n \t.result_bit_size = 64,\n \t.result_num_fields = 8\n \t},\n@@ -2091,7 +2119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 2123,\n+\t.key_start_idx = 2141,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n@@ -2124,7 +2152,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n-\t.result_start_idx = 972,\n+\t.result_start_idx = 1089,\n \t.result_bit_size = 64,\n \t.result_num_fields = 8\n \t},\n@@ -2142,11 +2170,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 2124,\n+\t.key_start_idx = 2142,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 980,\n+\t.result_start_idx = 1097,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4\n \t},\n@@ -2165,7 +2193,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,\n \t.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n-\t.result_start_idx = 984,\n+\t.result_start_idx = 1101,\n \t.result_bit_size = 16,\n \t.result_num_fields = 1\n \t},\n@@ -2184,8 +2212,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.record_size = 64,\n-\t.result_start_idx = 985,\n+\t.result_start_idx = 1102,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n \t.encap_num_fields = 47\n@@ -2206,7 +2233,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 1032,\n+\t.result_start_idx = 1149,\n \t.result_bit_size = 128,\n \t.result_num_fields = 17\n \t},\n@@ -2224,7 +2251,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 2125,\n+\t.key_start_idx = 2143,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n@@ -2261,11 +2288,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 2126,\n+\t.key_start_idx = 2144,\n \t.blob_key_bit_size = 213,\n \t.key_bit_size = 213,\n \t.key_num_fields = 21,\n-\t.result_start_idx = 1049,\n+\t.result_start_idx = 1166,\n \t.result_bit_size = 43,\n \t.result_num_fields = 6,\n \t.ident_start_idx = 38,\n@@ -2284,7 +2311,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,\n \t.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n-\t.result_start_idx = 1055,\n+\t.result_start_idx = 1172,\n \t.result_bit_size = 106,\n \t.result_num_fields = 106\n \t},\n@@ -2306,11 +2333,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 2147,\n+\t.key_start_idx = 2165,\n \t.blob_key_bit_size = 94,\n \t.key_bit_size = 94,\n \t.key_num_fields = 43,\n-\t.result_start_idx = 1161,\n+\t.result_start_idx = 1278,\n \t.result_bit_size = 33,\n \t.result_num_fields = 8\n \t},\n@@ -2325,15 +2352,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 55,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.key_start_idx = 2190,\n+\t.key_start_idx = 2208,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.ident_start_idx = 38,\n-\t.ident_nums = 1\n+\t.result_start_idx = 1286,\n+\t.result_bit_size = 62,\n+\t.result_num_fields = 4\n \t},\n \t{ /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -2351,7 +2379,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 1169,\n+\t.result_start_idx = 1290,\n \t.result_bit_size = 128,\n \t.result_num_fields = 17\n \t},\n@@ -2367,11 +2395,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t\t.cond_nums = 0 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 2191,\n+\t.key_start_idx = 2209,\n \t.blob_key_bit_size = 0,\n \t.key_bit_size = 0,\n \t.key_num_fields = 114,\n-\t.result_start_idx = 1186,\n+\t.result_start_idx = 1307,\n \t.result_bit_size = 0,\n \t.result_num_fields = 6\n \t}\n@@ -2529,6 +2557,26 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n \t},\n+\t/* cond_execute: class_tid: 2, control.ipv6_check */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_I_IPV6\n+\t},\n+\t/* cond_execute: class_tid: 2, profile_tcam_cache.f2_ipv6_rd */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,\n+\t.cond_operand = BNXT_ULP_CF_IDX_WC_MATCH\n+\t},\n+\t/* cond_execute: class_tid: 2, control.f2_ipv6_prof_cache_check */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n+\t},\n+\t/* cond_execute: class_tid: 2, control.f2_v6_conflict_check */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_CC\n+\t},\n \t/* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n@@ -2544,21 +2592,6 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {\n \t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n \t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n \t},\n-\t/* cond_execute: class_tid: 2, wm.l3_l4.ipv6 */\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV6\n-\t},\n-\t/* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,\n-\t.cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC\n-\t},\n-\t/* cond_execute: class_tid: 3, control.0 */\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n-\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n-\t},\n \t/* cond_execute: class_tid: 3, control.ipv6_check */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n@@ -2584,11 +2617,6 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n \t},\n-\t/* cond_execute: class_tid: 3, control.conflict_check */\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n-\t.cond_operand = BNXT_ULP_RF_IDX_CC\n-\t},\n \t/* cond_execute: class_tid: 3, profile_tcam.l3_l4.ip */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n@@ -5115,12 +5143,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t}\n \t},\n \t{\n@@ -8346,7 +8386,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,\n \t\tBNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},\n \t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n@@ -8373,7 +8416,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,\n \t\tBNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},\n \t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n@@ -15050,7 +15096,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,\n \t\tBNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},\n \t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n@@ -15077,7 +15126,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,\n \t\tBNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},\n \t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n@@ -16551,7 +16603,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,\n \t\tBNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},\n \t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n@@ -16578,7 +16633,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,\n \t\tBNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},\n \t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n@@ -18283,7 +18341,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: profile_tcam_cache.f2_rd */\n+\t/* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"recycle_cnt\",\n@@ -18338,7 +18396,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: profile_tcam.f2 */\n+\t/* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l4_hdr_is_udp_tcp\",\n@@ -18357,14 +18415,34 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l4_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_I_L4 & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_I_TCP & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_THOR_SYM_L4_HDR_TYPE_TCP},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr3 = {\n+\t\tULP_THOR_SYM_L4_HDR_TYPE_UDP}\n \t\t}\n \t},\n \t{\n@@ -18372,7 +18450,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.description = \"l4_hdr_error\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_I_L4 & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4_hdr_error\",\n@@ -18386,13 +18467,19 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.description = \"l4_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_I_L4 & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_I_L4 & 0xff}\n \t\t}\n \t},\n \t{\n@@ -18456,13 +18543,17 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.description = \"l3_hdr_type\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_hdr_type\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_THOR_SYM_L3_HDR_TYPE_IPV6}\n \t\t}\n \t},\n \t{\n@@ -18470,7 +18561,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.description = \"l3_hdr_error\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_hdr_error\",\n@@ -18484,13 +18577,17 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.description = \"l3_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_THOR_SYM_L3_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n@@ -18526,7 +18623,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.description = \"l2_uc_mc_bc\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_uc_mc_bc\",\n@@ -18990,15 +19089,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: profile_tcam_cache.f2_wr */\n+\t/* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"recycle_cnt\",\n@@ -19045,10 +19142,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: wm.l3_l4.ipv4 */\n+\t/* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"wc_profile_id\",\n+\t\t.description = \"em_profile_id\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n@@ -19056,13 +19153,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"wc_profile_id\",\n+\t\t.description = \"em_profile_id\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}\n+\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t\t}\n \t},\n \t{\n@@ -19401,20 +19498,12 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"tl3.dip.ipv4\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl3.dip.ipv4\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n@@ -19766,7 +19855,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.field_opr2 = {\n \t\t\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n \t\t\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tids\",\n@@ -19780,7 +19869,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.field_opr2 = {\n \t\t\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n \t\t\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t}\n \t},\n \t{\n@@ -19879,12 +19968,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l2_smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t}\n \t},\n \t{\n@@ -20059,12 +20166,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l3.sip.ipv6\",\n \t\t.field_bit_size = 128,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3.sip.ipv6\",\n \t\t.field_bit_size = 128,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t}\n \t},\n \t{\n@@ -20083,42 +20208,42 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l3.dip.ipv4\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3.dip.ipv4\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l3.dip.ipv6\",\n \t\t.field_bit_size = 128,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3.dip.ipv6\",\n \t\t.field_bit_size = 128,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t}\n \t},\n \t{\n@@ -20149,12 +20274,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t}\n \t},\n \t{\n@@ -20341,24 +20478,50 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l4.src\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4.src\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l4.dst\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4.dst\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t}\n \t},\n \t{\n@@ -20481,2254 +20644,2585 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: wm.l3_l4.ipv6 */\n+\t/* class_tid: 2, , table: profile_tcam_cache.f2_rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"wc_profile_id\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"wc_profile_id\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}\n+\t\t(BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 2, , table: profile_tcam.f2 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"parif\",\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"parif\",\n+\t\t.description = \"l4_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"spif\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"spif\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 11,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 11,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"lcos\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"ieh\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"lcos\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"ieh\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"meta\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"meta\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"rcyc_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"rcyc_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"loopback\",\n+\t\t.description = \"l3_hdr_isIP\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"loopback\",\n+\t\t.description = \"l3_hdr_isIP\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_l2type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_l2type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_dmac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_dmac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_smac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_smac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_THOR_SYM_L3_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_dt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_dt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_sa\",\n+\t\t.description = \"l2_vtag_present\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_sa\",\n+\t\t.description = \"l2_vtag_present\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_nvt\",\n+\t\t.description = \"l2_uc_mc_bc\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_nvt\",\n+\t\t.description = \"l2_uc_mc_bc\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ovp\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ovp\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ovd\",\n+\t\t.description = \"l2_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ovd\",\n+\t\t.description = \"l2_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ovv\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ovv\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_THOR_SYM_L2_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ovt\",\n+\t\t.description = \"tun_hdr_flags\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ovt\",\n+\t\t.description = \"tun_hdr_flags\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ivp\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ivp\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ivd\",\n+\t\t.description = \"tun_hdr_err\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ivd\",\n+\t\t.description = \"tun_hdr_err\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ivv\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ivv\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ivt\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ivt\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_THOR_SYM_TUN_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_etype\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_etype\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.l3type\",\n+\t\t.description = \"tl4_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.l3type\",\n+\t\t.description = \"tl4_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_THOR_SYM_TL4_HDR_TYPE_UDP}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.sip.ipv4\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.sip.ipv4\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.sip.ipv6\",\n-\t\t.field_bit_size = 128,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.sip.ipv6\",\n-\t\t.field_bit_size = 128,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_THOR_SYM_TL4_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.sip_selcmp.ipv6\",\n-\t\t.field_bit_size = 72,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.sip_selcmp.ipv6\",\n-\t\t.field_bit_size = 72,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.dip.ipv4\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.dip.ipv4\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.dip.ipv6\",\n-\t\t.field_bit_size = 128,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.dip.ipv6\",\n-\t\t.field_bit_size = 128,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.dip_selcmp.ipv6\",\n-\t\t.field_bit_size = 72,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.dip_selcmp.ipv6\",\n-\t\t.field_bit_size = 72,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.ttl\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3.ttl\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3.prot\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3.prot\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3.fid.ipv4\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3.fid.ipv4\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3.fid.ipv6\",\n-\t\t.field_bit_size = 20,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3.fid.ipv6\",\n-\t\t.field_bit_size = 20,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3.qos\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3.qos\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3.ieh_nonext\",\n+\t\t.description = \"tl3_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.ieh_nonext\",\n+\t\t.description = \"tl3_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.ieh_esp\",\n+\t\t.description = \"tl3_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.ieh_esp\",\n+\t\t.description = \"tl3_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_THOR_SYM_TL3_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.ieh_auth\",\n+\t\t.description = \"tl2_two_vtags\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.ieh_auth\",\n+\t\t.description = \"tl2_two_vtags\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.ieh_dest\",\n+\t\t.description = \"tl2_vtag_present\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.ieh_dest\",\n+\t\t.description = \"tl2_vtag_present\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.ieh_frag\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.ieh_frag\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.ieh_rthdr\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.ieh_rthdr\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tl2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.ieh_hop\",\n+\t\t.description = \"tl2_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.ieh_hop\",\n+\t\t.description = \"tl2_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_THOR_SYM_TL2_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.ieh_1frag\",\n+\t\t.description = \"hrec_next\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.ieh_1frag\",\n+\t\t.description = \"hrec_next\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.df\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.df\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3.l3err\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3.l3err\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4.l4type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"metadata\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4.l4type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"metadata\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4.src\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4.src\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4.dst\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4.dst\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4.flags\",\n-\t\t.field_bit_size = 9,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4.flags\",\n-\t\t.field_bit_size = 9,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n \t\t}\n \t},\n+\t/* class_tid: 2, , table: profile_tcam_cache.f2_wr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4.seq\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4.seq\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4.pa\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4.pa\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4.opt\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4.opt\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 2, , table: wm.l3_l4.ipv4 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4.tcpts\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"wc_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4.tcpts\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"wc_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4.err\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4.err\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tuntype\",\n+\t\t.description = \"parif\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tuntype\",\n+\t\t.description = \"parif\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tflags\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"spif\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tflags\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"spif\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tids\",\n-\t\t.field_bit_size = 24,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tids\",\n-\t\t.field_bit_size = 24,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tid\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 11,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tid\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 11,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tctxts\",\n-\t\t.field_bit_size = 24,\n+\t\t.description = \"lcos\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tctxts\",\n-\t\t.field_bit_size = 24,\n+\t\t.description = \"lcos\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tctxt\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"meta\",\n+\t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tctxt\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"meta\",\n+\t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tqos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"rcyc_cnt\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tqos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"rcyc_cnt\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"terr\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"loopback\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"terr\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"loopback\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_l2type\",\n+\t\t.description = \"tl2_l2type\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_l2type\",\n+\t\t.description = \"tl2_l2type\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_dmac\",\n+\t\t.description = \"tl2_dmac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_dmac\",\n+\t\t.description = \"tl2_dmac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_smac\",\n+\t\t.description = \"tl2_smac\",\n \t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_smac\",\n+\t\t.description = \"tl2_smac\",\n \t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_dt\",\n+\t\t.description = \"tl2_dt\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_dt\",\n+\t\t.description = \"tl2_dt\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_sa\",\n+\t\t.description = \"tl2_sa\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_sa\",\n+\t\t.description = \"tl2_sa\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_nvt\",\n+\t\t.description = \"tl2_nvt\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_nvt\",\n+\t\t.description = \"tl2_nvt\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ovp\",\n+\t\t.description = \"tl2_ovp\",\n \t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ovp\",\n+\t\t.description = \"tl2_ovp\",\n \t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ovd\",\n+\t\t.description = \"tl2_ovd\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ovd\",\n+\t\t.description = \"tl2_ovd\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ovv\",\n+\t\t.description = \"tl2_ovv\",\n \t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ovv\",\n+\t\t.description = \"tl2_ovv\",\n \t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ovt\",\n+\t\t.description = \"tl2_ovt\",\n \t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ovt\",\n+\t\t.description = \"tl2_ovt\",\n \t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivp\",\n+\t\t.description = \"tl2_ivp\",\n \t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivp\",\n+\t\t.description = \"tl2_ivp\",\n \t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivd\",\n+\t\t.description = \"tl2_ivd\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivd\",\n+\t\t.description = \"tl2_ivd\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivv\",\n+\t\t.description = \"tl2_ivv\",\n \t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivv\",\n+\t\t.description = \"tl2_ivv\",\n \t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivt\",\n+\t\t.description = \"tl2_ivt\",\n \t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivt\",\n+\t\t.description = \"tl2_ivt\",\n \t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_etype\",\n+\t\t.description = \"tl2_etype\",\n \t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_etype\",\n+\t\t.description = \"tl2_etype\",\n \t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.l3type\",\n+\t\t.description = \"tl3.l3type\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.l3type\",\n+\t\t.description = \"tl3.l3type\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.sip.ipv4\",\n+\t\t.description = \"tl3.sip.ipv4\",\n \t\t.field_bit_size = 32,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.sip.ipv4\",\n+\t\t.description = \"tl3.sip.ipv4\",\n \t\t.field_bit_size = 32,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.sip.ipv6\",\n+\t\t.description = \"tl3.sip.ipv6\",\n \t\t.field_bit_size = 128,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.sip.ipv6\",\n+\t\t.description = \"tl3.sip.ipv6\",\n \t\t.field_bit_size = 128,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.sip_selcmp.ipv6\",\n+\t\t.description = \"tl3.sip_selcmp.ipv6\",\n \t\t.field_bit_size = 72,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.sip_selcmp.ipv6\",\n+\t\t.description = \"tl3.sip_selcmp.ipv6\",\n \t\t.field_bit_size = 72,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.dip.ipv4\",\n+\t\t.description = \"tl3.dip.ipv4\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.dip.ipv4\",\n+\t\t.description = \"tl3.dip.ipv4\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.dip.ipv6\",\n+\t\t.description = \"tl3.dip.ipv6\",\n \t\t.field_bit_size = 128,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.dip.ipv6\",\n+\t\t.description = \"tl3.dip.ipv6\",\n \t\t.field_bit_size = 128,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.dip_selcmp.ipv6\",\n+\t\t.description = \"tl3.dip_selcmp.ipv6\",\n \t\t.field_bit_size = 72,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.dip_selcmp.ipv6\",\n+\t\t.description = \"tl3.dip_selcmp.ipv6\",\n \t\t.field_bit_size = 72,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.ttl\",\n+\t\t.description = \"tl3.ttl\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.ttl\",\n+\t\t.description = \"tl3.ttl\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.prot\",\n+\t\t.description = \"tl3.prot\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.prot\",\n+\t\t.description = \"tl3.prot\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.fid.ipv4\",\n+\t\t.description = \"tl3.fid.ipv4\",\n \t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.fid.ipv4\",\n+\t\t.description = \"tl3.fid.ipv4\",\n \t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.fid.ipv6\",\n+\t\t.description = \"tl3.fid.ipv6\",\n \t\t.field_bit_size = 20,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.fid.ipv6\",\n+\t\t.description = \"tl3.fid.ipv6\",\n \t\t.field_bit_size = 20,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.qos\",\n+\t\t.description = \"tl3.qos\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.qos\",\n+\t\t.description = \"tl3.qos\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.ieh_nonext\",\n+\t\t.description = \"tl3.ieh_nonext\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.ieh_nonext\",\n+\t\t.description = \"tl3.ieh_nonext\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.ieh_esp\",\n+\t\t.description = \"tl3.ieh_esp\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.ieh_esp\",\n+\t\t.description = \"tl3.ieh_esp\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.ieh_auth\",\n+\t\t.description = \"tl3.ieh_auth\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.ieh_auth\",\n+\t\t.description = \"tl3.ieh_auth\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.ieh_dest\",\n+\t\t.description = \"tl3.ieh_dest\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.ieh_dest\",\n+\t\t.description = \"tl3.ieh_dest\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.ieh_frag\",\n+\t\t.description = \"tl3.ieh_frag\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.ieh_frag\",\n+\t\t.description = \"tl3.ieh_frag\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.ieh_rthdr\",\n+\t\t.description = \"tl3.ieh_rthdr\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.ieh_rthdr\",\n+\t\t.description = \"tl3.ieh_rthdr\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.ieh_hop\",\n+\t\t.description = \"tl3.ieh_hop\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.ieh_hop\",\n+\t\t.description = \"tl3.ieh_hop\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.ieh_1frag\",\n+\t\t.description = \"tl3.ieh_1frag\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.ieh_1frag\",\n+\t\t.description = \"tl3.ieh_1frag\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.df\",\n+\t\t.description = \"tl3.df\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.df\",\n+\t\t.description = \"tl3.df\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.l3err.ipv4\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3.l3err.ipv4\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3.l3err.ipv6\",\n+\t\t.description = \"tl3.l3err\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.l3err.ipv6\",\n+\t\t.description = \"tl3.l3err\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.l4type\",\n+\t\t.description = \"tl4.l4type\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.l4type\",\n+\t\t.description = \"tl4.l4type\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.src\",\n+\t\t.description = \"tl4.src\",\n \t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.src\",\n+\t\t.description = \"tl4.src\",\n \t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.dst\",\n+\t\t.description = \"tl4.dst\",\n \t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.dst\",\n+\t\t.description = \"tl4.dst\",\n \t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.flags\",\n+\t\t.description = \"tl4.flags\",\n \t\t.field_bit_size = 9,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.flags\",\n+\t\t.description = \"tl4.flags\",\n \t\t.field_bit_size = 9,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.seq\",\n+\t\t.description = \"tl4.seq\",\n \t\t.field_bit_size = 32,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.seq\",\n+\t\t.description = \"tl4.seq\",\n \t\t.field_bit_size = 32,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.ack\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"tl4.pa\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.ack\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"tl4.pa\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.win\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"tl4.opt\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.win\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"tl4.opt\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.pa\",\n+\t\t.description = \"tl4.tcpts\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.pa\",\n+\t\t.description = \"tl4.tcpts\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.opt\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl4.err\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.opt\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl4.err\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.tcpts\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tuntype\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.tcpts\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tuntype\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.tsval\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"tflags\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.tsval\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"tflags\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.txecr\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tids\",\n+\t\t.field_bit_size = 24,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.txecr\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.description = \"tids\",\n+\t\t.field_bit_size = 24,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.err\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"tid\",\n+\t\t.field_bit_size = 32,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.err\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"tid\",\n+\t\t.field_bit_size = 32,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t.description = \"tctxts\",\n+\t\t.field_bit_size = 24,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t.description = \"tctxts\",\n+\t\t.field_bit_size = 24,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: mac_addr_cache.rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t.description = \"tctxt\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t.description = \"tctxt\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\tULP_THOR_SYM_TUN_HDR_TYPE_NONE}\n+\t\t.description = \"tqos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\tULP_THOR_SYM_TUN_HDR_TYPE_NONE}\n+\t\t.description = \"tqos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"one_tag\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"terr\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"one_tag\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"terr\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_l2type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_l2type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac_addr\",\n+\t\t.description = \"l2_dmac\",\n \t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac_addr\",\n+\t\t.description = \"l2_dmac\",\n \t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: port_table.egr.rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"dev.port_id\",\n-\t\t.field_bit_size = 10,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.description = \"l2_smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"dev.port_id\",\n-\t\t.field_bit_size = 10,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.description = \"l2_smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"etype\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_dt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"etype\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_dt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_tpid_sel\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_sa\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_tpid_sel\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_sa\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_nvt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_nvt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_tpid_sel\",\n+\t\t.description = \"l2_ovp\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_tpid_sel\",\n+\t\t.description = \"l2_ovp\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_ovd\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_ovd\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_ovv\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_ovv\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_ovt\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_ovt\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_ivp\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_ivp\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t.description = \"l2_ivd\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t.description = \"l2_ivd\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tunnel_id\",\n-\t\t.field_bit_size = 24,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_ivv\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tunnel_id\",\n-\t\t.field_bit_size = 24,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_ivv\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\tULP_THOR_SYM_TUN_HDR_TYPE_NONE}\n+\t\t.description = \"l2_ivt\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\tULP_THOR_SYM_TUN_HDR_TYPE_NONE}\n+\t\t.description = \"l2_ivt\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"llc\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_etype\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"llc\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2_etype\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"roce\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.l3type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"roce\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"metadata\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"metadata\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.l3type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 11,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.description = \"l3.sip.ipv4\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 11,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.description = \"l3.sip.ipv4\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"parif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"parif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"spif\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.sip.ipv6\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"spif\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.sip.ipv6\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"loopback\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.sip_selcmp.ipv6\",\n+\t\t.field_bit_size = 72,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"loopback\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.sip_selcmp.ipv6\",\n+\t\t.field_bit_size = 72,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.dip.ipv4\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.dip.ipv4\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mpass_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.dip.ipv6\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mpass_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.dip.ipv6\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t1}\n+\t\t.description = \"l3.dip_selcmp.ipv6\",\n+\t\t.field_bit_size = 72,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t1}\n+\t\t.description = \"l3.dip_selcmp.ipv6\",\n+\t\t.field_bit_size = 72,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: mac_addr_cache.wr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n+\t\t.description = \"l3.ttl\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n+\t\t.description = \"l3.ttl\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.description = \"l3.prot\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\tULP_THOR_SYM_TUN_HDR_TYPE_NONE}\n+\t\t(BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.description = \"l3.prot\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\tULP_THOR_SYM_TUN_HDR_TYPE_NONE}\n+\t\t(BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"one_tag\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.fid.ipv4\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"one_tag\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.fid.ipv4\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.fid.ipv6\",\n+\t\t.field_bit_size = 20,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.fid.ipv6\",\n+\t\t.field_bit_size = 20,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t.description = \"l3.qos\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t.description = \"l3.qos\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.ieh_nonext\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.ieh_nonext\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.description = \"l3.ieh_esp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr3 = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t.description = \"l3.ieh_esp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.description = \"l3.ieh_auth\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n+\t\t.description = \"l3.ieh_auth\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.description = \"l3.ieh_dest\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.description = \"l3.ieh_dest\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.ieh_frag\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n-\t\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr2 = {\n-\t\t\tULP_THOR_SYM_L4_HDR_TYPE_TCP},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr3 = {\n-\t\tULP_THOR_SYM_L4_HDR_TYPE_UDP}\n+\t\t.description = \"l3.ieh_frag\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_error\",\n+\t\t.description = \"l3.ieh_rthdr\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_error\",\n+\t\t.description = \"l3.ieh_rthdr\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_valid\",\n+\t\t.description = \"l3.ieh_hop\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_valid\",\n+\t\t.description = \"l3.ieh_hop\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"ieh\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.ieh_1frag\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"ieh\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.ieh_1frag\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.description = \"l3.df\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.description = \"l3.df\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.l3err.ipv4\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.l3err.ipv4\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.l3err.ipv6\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.l3err.ipv6\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_type\",\n+\t\t.description = \"l4.l4type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_type\",\n+\t\t.description = \"l4.l4type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\tULP_THOR_SYM_L3_HDR_TYPE_IPV6}\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.description = \"l4.src\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t(BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l4.src\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.description = \"l4.dst\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t(BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.description = \"l4.dst\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\tULP_THOR_SYM_L3_HDR_VALID_YES}\n+\t\t(BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l4.flags\",\n+\t\t.field_bit_size = 9,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l4.flags\",\n+\t\t.field_bit_size = 9,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.description = \"l4.seq\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_vtag_present\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l4.seq\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.ack\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.ack\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.win\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.win\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.pa\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.pa\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.opt\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.opt\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.tcpts\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.tcpts\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.tsval\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.tsval\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.txecr\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.txecr\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.err\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.err\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_THOR_SYM_L4_HDR_TYPE_TCP},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr3 = {\n+\t\tULP_THOR_SYM_L4_HDR_TYPE_UDP}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"ieh\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"ieh\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_THOR_SYM_L3_HDR_TYPE_IPV6}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_THOR_SYM_L3_HDR_VALID_YES}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n \t\t.field_opr1 = {\n@@ -23114,17 +23608,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_spec = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr3 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n \t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t\t}\n@@ -23230,17 +23716,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_spec = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr3 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n \t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t\t}\n@@ -24082,12 +24560,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l2_smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t}\n \t},\n \t{\n@@ -24388,12 +24884,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_SKIP\n \t\t}\n \t},\n \t{\n@@ -24773,17 +25281,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_spec = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr3 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n \t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t\t}\n@@ -25425,17 +25925,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_spec = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr3 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n \t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t\t}\n@@ -26095,17 +26587,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_spec = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr3 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n \t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t\t}\n@@ -26211,17 +26695,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_spec = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr3 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n \t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t\t}\n@@ -27063,12 +27539,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l2_smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -27349,12 +27843,27 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -27542,47 +28051,29 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.description = \"l4.src\",\n \t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr3 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4.src\",\n \t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr3 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -27590,47 +28081,29 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.description = \"l4.dst\",\n \t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr3 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4.dst\",\n \t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr3 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -28571,12 +29044,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l2_smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -28857,12 +29348,27 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -30011,12 +30517,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l2_smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -30285,12 +30809,14 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -31393,227 +31919,11 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n-\t\t}\n-\t},\n-\t/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"etype\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"etype\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_tpid_sel\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_tpid_sel\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_tpid_sel\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_tpid_sel\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n+\t/* class_tid: 5, , table: port_table.egr_wr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tunnel_id\",\n-\t\t.field_bit_size = 24,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tunnel_id\",\n-\t\t.field_bit_size = 24,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"llc\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"llc\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"roce\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"roce\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"metadata\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"metadata\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 11,\n+\t\t.description = \"dev.port_id\",\n+\t\t.field_bit_size = 10,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n@@ -31621,104 +31931,16 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 11,\n+\t\t.description = \"dev.port_id\",\n+\t\t.field_bit_size = 10,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"parif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"parif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"spif\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"spif\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"loopback\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"loopback\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"mpass_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mpass_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t1}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t1}\n+\t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n@@ -31738,67 +31960,392 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n-\t\t}\n-\t},\n-\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n-\t\t}\n-\t},\n-\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n-\t\t}\n-\t},\n-\t/* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */\n+\t/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"etype\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"etype\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ivlan_tpid_sel\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ivlan_tpid_sel\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ovlan_tpid_sel\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ovlan_tpid_sel\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tunnel_id\",\n+\t\t.field_bit_size = 24,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tunnel_id\",\n+\t\t.field_bit_size = 24,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"llc\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"llc\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"roce\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"roce\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"metadata\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"metadata\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 11,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 11,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"parif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"parif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"spif\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"spif\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"loopback\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"loopback\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mpass_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mpass_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t}\n+\t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"etype\",\n@@ -33860,332 +34407,1091 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3.ieh_auth\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3.ieh_auth\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.field_info_mask = {\n+\t\t.description = \"l3.ieh_auth\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3.ieh_auth\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3.ieh_dest\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3.ieh_dest\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3.ieh_frag\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3.ieh_frag\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3.ieh_rthdr\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3.ieh_rthdr\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3.ieh_hop\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3.ieh_hop\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3.ieh_1frag\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3.ieh_1frag\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3.df\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3.df\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3.l3err.ipv4\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3.l3err.ipv4\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3.l3err.ipv6\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3.l3err.ipv6\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.l4type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.l4type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.src\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.src\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.dst\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.dst\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.flags\",\n+\t\t.field_bit_size = 9,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.flags\",\n+\t\t.field_bit_size = 9,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.seq\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.seq\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.ack\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.ack\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.win\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.win\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.pa\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.pa\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.opt\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.opt\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.tcpts\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.tcpts\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.tsval\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.tsval\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.txecr\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.txecr\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.err\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.err\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n+\t\t}\n+\t}\n+};\n+\n+struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n+\t/* class_tid: 1, , table: l2_cntxt_tcam.0 */\n+\t{\n+\t.description = \"prof_func_id\",\n+\t.field_bit_size = 7,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr2 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n+\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr3 = {\n+\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t},\n+\t{\n+\t.description = \"ctxt_meta_prof\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"def_ctxt_data\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}\n+\t},\n+\t{\n+\t.description = \"ctxt_opcode\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\tULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}\n+\t},\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"parif\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n+\t},\n+\t/* class_tid: 1, , table: mac_addr_cache.wr */\n+\t{\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_RID & 0xff}\n+\t},\n+\t{\n+\t.description = \"l2_cntxt_tcam_index\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"src_property_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */\n+\t{\n+\t.description = \"l2_cntxt_id.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"parif.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"spif.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"svif.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"lcos.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meta.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"rcyc_cnt.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"loopback.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_l2type.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_dmac.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_smac.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_dt.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_sa.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_nvt.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_ovp.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_ovd.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_ovv.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_ovt.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_ivp.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_ivd.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_ivv.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_ivt.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl2_etype.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_l3type.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_sip.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_sip_selcmp.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_dip.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_dip_selcmp.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_ttl.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_prot.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_fid.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_qos.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_ieh_nonext.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_ieh_esp.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_ieh_auth.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_ieh_dest.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_ieh_frag.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_ieh_rthdr.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_ieh_hop.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_ieh_1frag.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_df.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_l3err.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl4_l4type.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl4_src.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl4_dst.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl4_flags.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl4_seq.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl4_pa.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl4_opt.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl4_tcpts.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl4_err.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tuntype.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tflags.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tids.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tid.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tctxts.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tctxt.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tqos.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"terr.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_l2type.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_dmac.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_smac.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t},\n+\t{\n+\t.description = \"l2_dt.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_sa.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_nvt.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_ovp.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_ovd.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_ovv.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_ovt.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_ivp.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_ivd.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_ivv.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t.field_opr1 = {\n+\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,\n+\t(uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr2 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},\n+\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_ivt.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_etype.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_l3type.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_sip.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t},\n+\t{\n+\t.description = \"l3_sip_selcmp.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_dip.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t},\n+\t{\n+\t.description = \"l3_dip_selcmp.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ttl.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_prot.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}\n+\t},\n+\t{\n+\t.description = \"l3_fid.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_qos.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ieh_nonext.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ieh_esp.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ieh_auth.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ieh_dest.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ieh_frag.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3.ieh_dest\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3.ieh_dest\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l3_ieh_rthdr.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3.ieh_frag\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3.ieh_frag\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l3_ieh_hop.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3.ieh_rthdr\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3.ieh_rthdr\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l3_ieh_1frag.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3.ieh_hop\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3.ieh_hop\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l3_df.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3.ieh_1frag\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3.ieh_1frag\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l3_l3err.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3.df\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3.df\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l4_l4type.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3.l3err.ipv4\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3.l3err.ipv4\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l4_src.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3.l3err.ipv6\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3.l3err.ipv6\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l4_dst.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4.l4type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4.l4type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l4_flags.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4.src\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4.src\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l4_seq.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4.dst\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4.dst\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l4_ack.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4.flags\",\n-\t\t.field_bit_size = 9,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4.flags\",\n-\t\t.field_bit_size = 9,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l4_win.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4.seq\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4.seq\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l4_pa.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4.ack\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4.ack\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l4_opt.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4.win\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4.win\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l4_tcpts.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4.pa\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4.pa\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l4_tsval.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4.opt\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4.opt\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l4_txecr.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4.tcpts\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4.tcpts\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"l4_err.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4.tsval\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4.tsval\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 6,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4.txecr\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4.txecr\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4.err\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4.err\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n-\t\t}\n-\t}\n-};\n-\n-struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n-\t/* class_tid: 1, , table: l2_cntxt_tcam.0 */\n-\t{\n-\t.description = \"prof_func_id\",\n-\t.field_bit_size = 7,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t.field_opr2 = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n-\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t.field_opr3 = {\n-\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t.description = \"wc_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"ctxt_meta_prof\",\n-\t.field_bit_size = 3,\n+\t.description = \"em_key_type\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"def_ctxt_data\",\n-\t.field_bit_size = 16,\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 6,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}\n+\t(BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}\n \t},\n \t{\n-\t.description = \"ctxt_opcode\",\n-\t.field_bit_size = 3,\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\tULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}\n+\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t},\n \t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n+\t.description = \"em_search_en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t1}\n \t},\n \t{\n-\t.description = \"parif\",\n-\t.field_bit_size = 4,\n+\t.description = \"pl_byp_lkup_en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n-\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, , table: mac_addr_cache.wr */\n+\t/* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -34196,27 +35502,98 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n-\t.description = \"l2_cntxt_tcam_index\",\n+\t.description = \"profile_tcam_index\",\n \t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"flow_sig_id\",\n+\t.field_bit_size = 64,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n+\t},\n+\t/* class_tid: 1, , table: em.l2_l3_l4_v6.0 */\n+\t{\n+\t.description = \"valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t3}\n+\t},\n+\t{\n+\t.description = \"data\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.description = \"src_property_ptr\",\n-\t.field_bit_size = 10,\n+\t.description = \"opcode\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */\n+\t{\n+\t.description = \"meta_prof\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ctxt_data\",\n+\t.field_bit_size = 14,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* class_tid: 1, , table: fkb_select.l3_l4_wm */\n \t{\n \t.description = \"l2_cntxt_id.en\",\n \t.field_bit_size = 1,\n@@ -34589,10 +35966,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l2_smac.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t1}\n \t},\n \t{\n \t.description = \"l2_dt.en\",\n@@ -34651,22 +36027,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t{\n \t.description = \"l2_ivv.en\",\n \t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,\n-\t(uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr2 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},\n-\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t1}\n \t},\n \t{\n \t.description = \"l2_ivt.en\",\n@@ -34690,10 +36054,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l3_sip.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t1}\n \t},\n \t{\n \t.description = \"l3_sip_selcmp.en\",\n@@ -34705,10 +36068,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l3_dip.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t1}\n \t},\n \t{\n \t.description = \"l3_dip_selcmp.en\",\n@@ -34726,7 +36088,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l3_prot.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"l3_fid.en\",\n@@ -34810,19 +36174,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l4_src.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,\n-\tBNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}\n+\t1}\n \t},\n \t{\n \t.description = \"l4_dst.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,\n-\tBNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}\n+\t1}\n \t},\n \t{\n \t.description = \"l4_flags.en\",\n@@ -34884,166 +36246,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */\n-\t{\n-\t.description = \"wc_key_id\",\n-\t.field_bit_size = 6,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"wc_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"wc_search_en\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"em_key_type\",\n-\t.field_bit_size = 2,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"em_key_id\",\n-\t.field_bit_size = 6,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}\n-\t},\n-\t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n-\t},\n-\t{\n-\t.description = \"em_search_en\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n-\t},\n-\t{\n-\t.description = \"pl_byp_lkup_en\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t/* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */\n-\t{\n-\t.description = \"rid\",\n-\t.field_bit_size = 32,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_RID & 0xff}\n-\t},\n-\t{\n-\t.description = \"profile_tcam_index\",\n-\t.field_bit_size = 10,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}\n-\t},\n-\t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n-\t},\n-\t{\n-\t.description = \"em_key_id\",\n-\t.field_bit_size = 8,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}\n-\t},\n-\t{\n-\t.description = \"wc_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"wc_key_id\",\n-\t.field_bit_size = 8,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"flow_sig_id\",\n-\t.field_bit_size = 64,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n-\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n-\t},\n-\t/* class_tid: 1, , table: em.l2_l3_l4_v6.0 */\n-\t{\n-\t.description = \"valid\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n-\t},\n-\t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t3}\n-\t},\n-\t{\n-\t.description = \"data\",\n-\t.field_bit_size = 16,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n-\t},\n-\t{\n-\t.description = \"opcode\",\n-\t.field_bit_size = 3,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"meta_prof\",\n-\t.field_bit_size = 3,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"ctxt_data\",\n-\t.field_bit_size = 14,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t/* class_tid: 1, , table: fkb_select.l3_l4_wm */\n+\t/* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */\n \t{\n \t.description = \"l2_cntxt_id.en\",\n \t.field_bit_size = 1,\n@@ -35170,7 +36373,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"tl2_ivv.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"tl2_ivt.en\",\n@@ -35194,7 +36399,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"tl3_sip.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"tl3_sip_selcmp.en\",\n@@ -35206,7 +36413,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"tl3_dip.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"tl3_dip_selcmp.en\",\n@@ -35224,7 +36433,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"tl3_prot.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"tl3_fid.en\",\n@@ -35308,13 +36519,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"tl4_src.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"tl4_dst.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"tl4_flags.en\",\n@@ -35478,9 +36693,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l2_ivv.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l2_ivt.en\",\n@@ -35504,9 +36717,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l3_sip.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_sip_selcmp.en\",\n@@ -35518,9 +36729,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l3_dip.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_dip_selcmp.en\",\n@@ -35538,9 +36747,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l3_prot.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_fid.en\",\n@@ -35624,17 +36831,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l4_src.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l4_dst.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l4_flags.en\",\n@@ -35696,9 +36899,112 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */\n+\t/* class_tid: 1, , table: profile_tcam.l3_l4.ip */\n \t{\n-\t.description = \"l2_cntxt_id.en\",\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 6,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t.field_opr1 = {\n+\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,\n+\t(uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr2 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},\n+\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr3 = {\n+\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"wc_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"em_key_type\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 6,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"pl_byp_lkup_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */\n+\t{\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 6,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}\n+\t},\n+\t{\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t.field_opr1 = {\n+\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,\n+\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,\n+\t(uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr2 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},\n+\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr3 = {\n+\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}\n+\t},\n+\t{\n+\t.description = \"wc_search_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -35706,1131 +37012,1203 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t1}\n \t},\n \t{\n-\t.description = \"parif.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"em_key_type\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 6,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"spif.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"svif.en\",\n+\t.description = \"em_search_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"lcos.en\",\n+\t.description = \"pl_byp_lkup_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 1, , table: profile_tcam_cache.wr */\n \t{\n-\t.description = \"meta.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n-\t.description = \"rcyc_cnt.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"profile_tcam_index\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n-\t.description = \"loopback.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl2_l2type.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl2_dmac.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl2_smac.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl2_dt.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"flow_sig_id\",\n+\t.field_bit_size = 64,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n \t},\n+\t/* class_tid: 1, , table: wm.l3_l4.ipv4 */\n \t{\n-\t.description = \"tl2_sa.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"ctxt_data\",\n+\t.field_bit_size = 14,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl2_nvt.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"meta_prof\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl2_ovp.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"opcode\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl2_ovd.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"data\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.description = \"tl2_ovv.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n+\t/* class_tid: 1, , table: wm.l3_l4.ipv6 */\n \t{\n-\t.description = \"tl2_ovt.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"ctxt_data\",\n+\t.field_bit_size = 14,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl2_ivp.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"meta_prof\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl2_ivd.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"opcode\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl2_ivv.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"data\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t},\n+\t{\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n \t1}\n \t},\n+\t/* class_tid: 1, , table: wm.l3.ipv4 */\n \t{\n-\t.description = \"tl2_ivt.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"ctxt_data\",\n+\t.field_bit_size = 14,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl2_etype.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"meta_prof\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl3_l3type.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"opcode\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl3_sip.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"data\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t},\n+\t{\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n \t1}\n \t},\n+\t/* class_tid: 1, , table: wm.l3.ipv6 */\n \t{\n-\t.description = \"tl3_sip_selcmp.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"ctxt_data\",\n+\t.field_bit_size = 14,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl3_dip.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"meta_prof\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl3_dip_selcmp.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"opcode\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl3_ttl.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"data\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.description = \"tl3_prot.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n \t1}\n \t},\n+\t/* class_tid: 1, , table: wm.l2 */\n \t{\n-\t.description = \"tl3_fid.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"ctxt_data\",\n+\t.field_bit_size = 14,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl3_qos.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"meta_prof\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl3_ieh_nonext.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"opcode\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl3_ieh_esp.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"data\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.description = \"tl3_ieh_auth.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n+\t/* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */\n \t{\n-\t.description = \"tl3_ieh_dest.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"ctxt_data\",\n+\t.field_bit_size = 14,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl3_ieh_frag.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"meta_prof\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl3_ieh_rthdr.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"opcode\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl3_ieh_hop.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"data\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.description = \"tl3_ieh_1frag.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n+\t/* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */\n \t{\n-\t.description = \"tl3_df.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"ctxt_data\",\n+\t.field_bit_size = 14,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl3_l3err.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"meta_prof\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl4_l4type.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"opcode\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl4_src.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"data\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t1}\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.description = \"tl4_dst.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n \t1}\n \t},\n+\t/* class_tid: 2, , table: l2_cntxt_tcam.1 */\n \t{\n-\t.description = \"tl4_flags.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"prof_func_id\",\n+\t.field_bit_size = 7,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl4_seq.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"ctxt_meta_prof\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl4_pa.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"def_ctxt_data\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl4_opt.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"ctxt_opcode\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl4_tcpts.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl4_err.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"parif\",\n+\t.field_bit_size = 4,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 2, , table: tunnel_cache.wr */\n \t{\n-\t.description = \"tuntype.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n-\t.description = \"tflags.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"l2_cntxt_tcam_index\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tids.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n+\t/* class_tid: 2, , table: l2_cntxt_tcam.0 */\n \t{\n-\t.description = \"tid.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"prof_func_id\",\n+\t.field_bit_size = 7,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,\n+\tBNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}\n \t},\n \t{\n-\t.description = \"tctxts.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"ctxt_meta_prof\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tctxt.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"def_ctxt_data\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}\n \t},\n \t{\n-\t.description = \"tqos.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"ctxt_opcode\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\tULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}\n \t},\n \t{\n-\t.description = \"terr.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n-\t.description = \"l2_l2type.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"parif\",\n+\t.field_bit_size = 4,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n \t},\n+\t/* class_tid: 2, , table: mac_addr_cache.wr */\n \t{\n-\t.description = \"l2_dmac.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_RID & 0xff}\n+\t},\n+\t{\n+\t.description = \"l2_cntxt_tcam_index\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_smac.en\",\n-\t.field_bit_size = 1,\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"src_property_ptr\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */\n \t{\n-\t.description = \"l2_dt.en\",\n+\t.description = \"l2_cntxt_id.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n-\t.description = \"l2_sa.en\",\n+\t.description = \"parif.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_nvt.en\",\n+\t.description = \"spif.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_ovp.en\",\n+\t.description = \"svif.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_ovd.en\",\n+\t.description = \"lcos.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_ovv.en\",\n+\t.description = \"meta.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_ovt.en\",\n+\t.description = \"rcyc_cnt.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_ivp.en\",\n+\t.description = \"loopback.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_ivd.en\",\n+\t.description = \"tl2_l2type.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_ivv.en\",\n+\t.description = \"tl2_dmac.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_ivt.en\",\n+\t.description = \"tl2_smac.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_etype.en\",\n+\t.description = \"tl2_dt.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_l3type.en\",\n+\t.description = \"tl2_sa.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_sip.en\",\n+\t.description = \"tl2_nvt.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_sip_selcmp.en\",\n+\t.description = \"tl2_ovp.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_dip.en\",\n+\t.description = \"tl2_ovd.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_dip_selcmp.en\",\n+\t.description = \"tl2_ovv.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_ttl.en\",\n+\t.description = \"tl2_ovt.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_prot.en\",\n+\t.description = \"tl2_ivp.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_fid.en\",\n+\t.description = \"tl2_ivd.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_qos.en\",\n+\t.description = \"tl2_ivv.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_ieh_nonext.en\",\n+\t.description = \"tl2_ivt.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_ieh_esp.en\",\n+\t.description = \"tl2_etype.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_ieh_auth.en\",\n+\t.description = \"tl3_l3type.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_ieh_dest.en\",\n+\t.description = \"tl3_sip.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_ieh_frag.en\",\n+\t.description = \"tl3_sip_selcmp.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_ieh_rthdr.en\",\n+\t.description = \"tl3_dip.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_ieh_hop.en\",\n+\t.description = \"tl3_dip_selcmp.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_ieh_1frag.en\",\n+\t.description = \"tl3_ttl.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_df.en\",\n+\t.description = \"tl3_prot.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_l3err.en\",\n+\t.description = \"tl3_fid.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l4_l4type.en\",\n+\t.description = \"tl3_qos.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l4_src.en\",\n+\t.description = \"tl3_ieh_nonext.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l4_dst.en\",\n+\t.description = \"tl3_ieh_esp.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l4_flags.en\",\n+\t.description = \"tl3_ieh_auth.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l4_seq.en\",\n+\t.description = \"tl3_ieh_dest.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l4_ack.en\",\n+\t.description = \"tl3_ieh_frag.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l4_win.en\",\n+\t.description = \"tl3_ieh_rthdr.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l4_pa.en\",\n+\t.description = \"tl3_ieh_hop.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l4_opt.en\",\n+\t.description = \"tl3_ieh_1frag.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l4_tcpts.en\",\n+\t.description = \"tl3_df.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l4_tsval.en\",\n+\t.description = \"tl3_l3err.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l4_txecr.en\",\n+\t.description = \"tl4_l4type.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l4_err.en\",\n+\t.description = \"tl4_src.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, , table: profile_tcam.l3_l4.ip */\n \t{\n-\t.description = \"wc_key_id\",\n-\t.field_bit_size = 6,\n+\t.description = \"tl4_dst.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"wc_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n-\t.field_opr1 = {\n-\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,\n-\t(uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t.field_opr2 = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},\n-\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t.field_opr3 = {\n-\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}\n+\t.description = \"tl4_flags.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"wc_search_en\",\n+\t.description = \"tl4_seq.en\",\n \t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_type\",\n-\t.field_bit_size = 2,\n+\t.description = \"tl4_pa.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_id\",\n-\t.field_bit_size = 6,\n+\t.description = \"tl4_opt.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"tl4_tcpts.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_search_en\",\n+\t.description = \"tl4_err.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"pl_byp_lkup_en\",\n+\t.description = \"tuntype.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */\n \t{\n-\t.description = \"wc_key_id\",\n-\t.field_bit_size = 6,\n+\t.description = \"tflags.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,\n-\tBNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"wc_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t.description = \"tids.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n \t.field_opr1 = {\n-\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,\n-\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,\n-\t(uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t.field_opr2 = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},\n-\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t.field_opr3 = {\n-\t(BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,\n-\tBNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}\n+\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}\n \t},\n \t{\n-\t.description = \"wc_search_en\",\n+\t.description = \"tid.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_type\",\n-\t.field_bit_size = 2,\n+\t.description = \"tctxts.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_id\",\n-\t.field_bit_size = 6,\n+\t.description = \"tctxt.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"tqos.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_search_en\",\n+\t.description = \"terr.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"pl_byp_lkup_en\",\n+\t.description = \"l2_l2type.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, , table: profile_tcam_cache.wr */\n \t{\n-\t.description = \"rid\",\n-\t.field_bit_size = 32,\n+\t.description = \"l2_dmac.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_RID & 0xff}\n+\t1}\n \t},\n \t{\n-\t.description = \"profile_tcam_index\",\n-\t.field_bit_size = 10,\n+\t.description = \"l2_smac.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}\n+\t(BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}\n \t},\n \t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"l2_dt.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"l2_sa.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"wc_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"l2_nvt.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"wc_key_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"l2_ovp.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"flow_sig_id\",\n-\t.field_bit_size = 64,\n+\t.description = \"l2_ovd.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n-\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, , table: wm.l3_l4.ipv4 */\n \t{\n-\t.description = \"ctxt_data\",\n-\t.field_bit_size = 14,\n+\t.description = \"l2_ovv.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"meta_prof\",\n-\t.field_bit_size = 3,\n+\t.description = \"l2_ovt.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"opcode\",\n-\t.field_bit_size = 3,\n+\t.description = \"l2_ivp.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"data\",\n-\t.field_bit_size = 16,\n+\t.description = \"l2_ivd.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n+\t.description = \"l2_ivv.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, , table: wm.l3_l4.ipv6 */\n \t{\n-\t.description = \"ctxt_data\",\n-\t.field_bit_size = 14,\n+\t.description = \"l2_ivt.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"meta_prof\",\n-\t.field_bit_size = 3,\n+\t.description = \"l2_etype.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"opcode\",\n-\t.field_bit_size = 3,\n+\t.description = \"l3_l3type.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"data\",\n-\t.field_bit_size = 16,\n+\t.description = \"l3_sip.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t(BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}\n \t},\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n+\t.description = \"l3_sip_selcmp.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_dip.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n \t.field_opr1 = {\n-\t1}\n+\t(BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}\n \t},\n-\t/* class_tid: 1, , table: wm.l3.ipv4 */\n \t{\n-\t.description = \"ctxt_data\",\n-\t.field_bit_size = 14,\n+\t.description = \"l3_dip_selcmp.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"meta_prof\",\n-\t.field_bit_size = 3,\n+\t.description = \"l3_ttl.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"opcode\",\n-\t.field_bit_size = 3,\n+\t.description = \"l3_prot.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}\n+\t},\n+\t{\n+\t.description = \"l3_fid.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"data\",\n-\t.field_bit_size = 16,\n+\t.description = \"l3_qos.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n+\t.description = \"l3_ieh_nonext.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, , table: wm.l3.ipv6 */\n \t{\n-\t.description = \"ctxt_data\",\n-\t.field_bit_size = 14,\n+\t.description = \"l3_ieh_esp.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"meta_prof\",\n-\t.field_bit_size = 3,\n+\t.description = \"l3_ieh_auth.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"opcode\",\n-\t.field_bit_size = 3,\n+\t.description = \"l3_ieh_dest.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"data\",\n-\t.field_bit_size = 16,\n+\t.description = \"l3_ieh_frag.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n+\t.description = \"l3_ieh_rthdr.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, , table: wm.l2 */\n \t{\n-\t.description = \"ctxt_data\",\n-\t.field_bit_size = 14,\n+\t.description = \"l3_ieh_hop.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"meta_prof\",\n-\t.field_bit_size = 3,\n+\t.description = \"l3_ieh_1frag.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"opcode\",\n-\t.field_bit_size = 3,\n+\t.description = \"l3_df.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"data\",\n-\t.field_bit_size = 16,\n+\t.description = \"l3_l3err.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l4_l4type.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l4_src.en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t(BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}\n \t},\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n+\t.description = \"l4_dst.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t.field_opr1 = {\n-\t1}\n+\t(BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}\n \t},\n-\t/* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */\n \t{\n-\t.description = \"ctxt_data\",\n-\t.field_bit_size = 14,\n+\t.description = \"l4_flags.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"meta_prof\",\n-\t.field_bit_size = 3,\n+\t.description = \"l4_seq.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"opcode\",\n-\t.field_bit_size = 3,\n+\t.description = \"l4_ack.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"data\",\n-\t.field_bit_size = 16,\n+\t.description = \"l4_win.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n+\t.description = \"l4_pa.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */\n \t{\n-\t.description = \"ctxt_data\",\n-\t.field_bit_size = 14,\n+\t.description = \"l4_opt.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"meta_prof\",\n-\t.field_bit_size = 3,\n+\t.description = \"l4_tcpts.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"opcode\",\n-\t.field_bit_size = 3,\n+\t.description = \"l4_tsval.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"data\",\n-\t.field_bit_size = 16,\n+\t.description = \"l4_txecr.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n+\t.description = \"l4_err.en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 2, , table: l2_cntxt_tcam.1 */\n+\t/* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */\n \t{\n-\t.description = \"prof_func_id\",\n-\t.field_bit_size = 7,\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 6,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"ctxt_meta_prof\",\n-\t.field_bit_size = 3,\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"def_ctxt_data\",\n-\t.field_bit_size = 16,\n+\t.description = \"wc_search_en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"ctxt_opcode\",\n-\t.field_bit_size = 3,\n+\t.description = \"em_key_type\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 6,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}\n \t},\n \t{\n-\t.description = \"parif\",\n-\t.field_bit_size = 4,\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"pl_byp_lkup_en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 2, , table: tunnel_cache.wr */\n+\t/* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -36841,99 +38219,94 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n-\t.description = \"l2_cntxt_tcam_index\",\n+\t.description = \"profile_tcam_index\",\n \t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t},\n-\t/* class_tid: 2, , table: l2_cntxt_tcam.0 */\n \t{\n-\t.description = \"prof_func_id\",\n-\t.field_bit_size = 7,\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,\n-\tBNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}\n+\t(BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}\n \t},\n \t{\n-\t.description = \"ctxt_meta_prof\",\n-\t.field_bit_size = 3,\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"def_ctxt_data\",\n-\t.field_bit_size = 16,\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"ctxt_opcode\",\n-\t.field_bit_size = 3,\n+\t.description = \"flow_sig_id\",\n+\t.field_bit_size = 64,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t.field_opr1 = {\n-\tULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}\n+\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n \t},\n+\t/* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */\n \t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n+\t.description = \"valid\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t1}\n \t},\n \t{\n-\t.description = \"parif\",\n-\t.field_bit_size = 4,\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n-\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n+\t3}\n \t},\n-\t/* class_tid: 2, , table: mac_addr_cache.wr */\n \t{\n-\t.description = \"rid\",\n-\t.field_bit_size = 32,\n+\t.description = \"data\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_RID & 0xff}\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.description = \"l2_cntxt_tcam_index\",\n-\t.field_bit_size = 10,\n+\t.description = \"opcode\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n+\t.description = \"meta_prof\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"src_property_ptr\",\n-\t.field_bit_size = 10,\n+\t.description = \"ctxt_data\",\n+\t.field_bit_size = 14,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n@@ -37100,9 +38473,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"tl3_dip.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_dip_selcmp.en\",\n@@ -37316,7 +38687,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l2_smac.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"l2_dt.en\",\n@@ -37400,7 +38773,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l3_sip.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"l3_sip_selcmp.en\",\n@@ -37432,7 +38807,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l3_prot.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"l3_fid.en\",\n@@ -37516,13 +38893,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l4_src.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"l4_dst.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"l4_flags.en\",\n@@ -37743,127 +39124,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.field_opr1 = {\n \t1}\n \t},\n-\t/* class_tid: 2, , table: wm.l3_l4.ipv6 */\n-\t{\n-\t.description = \"ctxt_data\",\n-\t.field_bit_size = 14,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"meta_prof\",\n-\t.field_bit_size = 3,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"opcode\",\n-\t.field_bit_size = 3,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"data\",\n-\t.field_bit_size = 16,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n-\t},\n-\t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n-\t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.0 */\n-\t{\n-\t.description = \"prof_func_id\",\n-\t.field_bit_size = 7,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}\n-\t},\n-\t{\n-\t.description = \"ctxt_meta_prof\",\n-\t.field_bit_size = 3,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"def_ctxt_data\",\n-\t.field_bit_size = 16,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}\n-\t},\n-\t{\n-\t.description = \"ctxt_opcode\",\n-\t.field_bit_size = 3,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\tULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}\n-\t},\n-\t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n-\t},\n-\t{\n-\t.description = \"parif\",\n-\t.field_bit_size = 4,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n-\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n-\t},\n-\t/* class_tid: 3, , table: mac_addr_cache.wr */\n-\t{\n-\t.description = \"rid\",\n-\t.field_bit_size = 32,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_RID & 0xff}\n-\t},\n-\t{\n-\t.description = \"l2_cntxt_tcam_index\",\n-\t.field_bit_size = 10,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}\n-\t},\n-\t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n-\t},\n-\t{\n-\t.description = \"src_property_ptr\",\n-\t.field_bit_size = 10,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n \t/* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */\n \t{\n \t.description = \"l2_cntxt_id.en\",\n@@ -38240,7 +39500,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l2_smac.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n \t},\n \t{\n \t.description = \"l2_dt.en\",\n@@ -38374,7 +39637,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l3_prot.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}\n \t},\n \t{\n \t.description = \"l3_fid.en\",\n@@ -39066,7 +40332,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l2_smac.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"l2_dt.en\",\n@@ -39186,7 +40454,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"l3_prot.en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"l3_fid.en\",\n@@ -39663,7 +40933,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"stats_op\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"stats_ptr\",\n@@ -39910,7 +41182,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"stats_op\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"stats_ptr\",\n@@ -40050,7 +41324,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}\n \t},\n \t{\n \t.description = \"reserved\",\n@@ -40238,7 +41515,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"stats_op\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"stats_ptr\",\n@@ -40299,6 +41578,43 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.field_opr1 = {\n \t1}\n \t},\n+\t/* class_tid: 5, , table: port_table.egr_wr */\n+\t{\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"drv_func.mac\",\n+\t.field_bit_size = 48,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"drv_func.parent.mac\",\n+\t.field_bit_size = 48,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff}\n+\t},\n+\t{\n+\t.description = \"phy_port\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"default_arec_ptr\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n+\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n+\t},\n \t/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */\n \t{\n \t.description = \"prof_func_id\",\n@@ -40450,7 +41766,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"stats_op\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"stats_ptr\",\n@@ -40610,7 +41928,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}\n \t},\n \t{\n \t.description = \"reserved\",\n@@ -40970,7 +42291,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"stats_op\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"stats_ptr\",\n@@ -41772,6 +43095,34 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */\n+\t{\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_RID & 0xff}\n+\t},\n+\t{\n+\t.description = \"l2_cntxt_tcam_index\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"src_property_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n \t/* class_tid: 5, , table: int_full_act_record.vfr_ing0 */\n \t{\n \t.description = \"sp_rec_ptr\",\n@@ -41819,7 +43170,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.description = \"stats_op\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n \t.description = \"stats_ptr\",\n@@ -42058,7 +43411,13 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 42\n \t},\n-\t/* class_tid: 2, , table: profile_tcam_cache.f2_rd */\n+\t/* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */\n+\t{\n+\t.description = \"em_key_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0,\n+\t.ident_bit_size = 8,\n+\t.ident_bit_pos = 50\n+\t},\n \t{\n \t.description = \"em_profile_id\",\n \t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n@@ -42077,47 +43436,40 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 32\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */\n+\t/* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */\n \t{\n-\t.description = \"l2_cntxt_id\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n-\t.ident_bit_size = 10,\n-\t.ident_bit_pos = 42\n+\t.description = \"em_profile_id\",\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.ident_type = TF_IDENT_TYPE_EM_PROF,\n+\t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n+\t.ident_bit_size = 8,\n+\t.ident_bit_pos = 23\n \t},\n-\t/* class_tid: 3, , table: mac_addr_cache.rd */\n+\t/* class_tid: 2, , table: profile_tcam_cache.f2_rd */\n \t{\n-\t.description = \"l2_cntxt_id\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n-\t.ident_bit_size = 10,\n+\t.description = \"em_profile_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n+\t.ident_bit_size = 8,\n \t.ident_bit_pos = 42\n \t},\n-\t/* class_tid: 3, , table: port_table.egr.rd */\n-\t{\n-\t.description = \"default_arec_ptr\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,\n-\t.ident_bit_size = 16,\n-\t.ident_bit_pos = 136\n-\t},\n \t{\n-\t.description = \"drv_func.parent.mac\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC,\n-\t.ident_bit_size = 48,\n-\t.ident_bit_pos = 80\n+\t.description = \"flow_sig_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,\n+\t.ident_bit_size = 64,\n+\t.ident_bit_pos = 74\n \t},\n \t{\n-\t.description = \"phy_port\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT,\n-\t.ident_bit_size = 8,\n-\t.ident_bit_pos = 128\n+\t.description = \"profile_tcam_index\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n+\t.ident_bit_size = 10,\n+\t.ident_bit_pos = 32\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */\n \t{\n \t.description = \"l2_cntxt_id\",\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,\n \t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n \t.ident_bit_size = 10,\n-\t.ident_bit_pos = 29\n+\t.ident_bit_pos = 42\n \t},\n \t/* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */\n \t{\n@@ -42168,36 +43520,29 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {\n \t},\n \t/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */\n \t{\n-\t.description = \"l2_cntxt_id\",\n+\t.description = \"l2_cntxt_id_low\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,\n+\t.ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,\n \t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 29\n \t},\n \t/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */\n \t{\n-\t.description = \"l2_cntxt_id\",\n+\t.description = \"l2_cntxt_id_low\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,\n+\t.ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,\n \t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 29\n \t},\n \t/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */\n \t{\n-\t.description = \"l2_cntxt_id\",\n+\t.description = \"l2_cntxt_id_low\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,\n+\t.ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,\n \t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 29\n-\t},\n-\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */\n-\t{\n-\t.description = \"rid\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_RID,\n-\t.ident_bit_size = 32,\n-\t.ident_bit_pos = 0\n \t}\n };\ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c\nindex 2870a0615a..4b9cb7fd5b 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Wed Jun 30 14:36:16 2021 */\n+/* date: Wed Aug 11 16:00:16 2021 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -16741,27 +16741,27 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t},\n \t/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */\n \t{\n-\t.description = \"l2_cntxt_id\",\n+\t.description = \"l2_cntxt_id_low\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,\n+\t.ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,\n \t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 0\n \t},\n \t/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */\n \t{\n-\t.description = \"l2_cntxt_id\",\n+\t.description = \"l2_cntxt_id_low\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,\n+\t.ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,\n \t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 0\n \t},\n \t/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */\n \t{\n-\t.description = \"l2_cntxt_id\",\n+\t.description = \"l2_cntxt_id_low\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,\n+\t.ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,\n \t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 0\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c\nindex c6b2b1675d..7b6db7a0f8 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c\n@@ -75,9 +75,9 @@ ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data)\n \t\t\tentry->container.byte_data = &entry->mem_data[size];\n \t\t\tentry->container.byte_order = tbl->result_byte_order;\n \t\t} else {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s:Invalid gen table num of ent %d\\n\",\n+\t\t\tBNXT_TF_DBG(DEBUG, \"%s: Unused Gen tbl entry is %d\\n\",\n \t\t\t\t    tbl->name, idx);\n-\t\t\treturn -EINVAL;\n+\t\t\t/* return -EINVAL; */\n \t\t}\n \t\tif (tbl->hash_tbl_entries) {\n \t\t\tcparams.key_size = tbl->key_num_bytes;\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c\nindex 234f7ea2fa..059ee99837 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c\n@@ -438,6 +438,77 @@ ulp_mapper_ident_fields_get(struct bnxt_ulp_mapper_parms *mparms,\n \treturn &dev_tbls->ident_list[idx];\n }\n \n+static enum tf_tbl_type\n+ulp_mapper_dyn_tbl_type_get(struct bnxt_ulp_mapper_parms *mparms,\n+\t\t\t    struct bnxt_ulp_mapper_tbl_info *tbl,\n+\t\t\t    struct ulp_blob *bdata,\n+\t\t\t    uint16_t *out_len)\n+{\n+\tstruct bnxt_ulp_device_params *d_params = mparms->device_params;\n+\tuint16_t blob_len = ulp_blob_data_len_get(bdata);\n+\tstruct bnxt_ulp_dyn_size_map *size_map;\n+\tuint32_t i;\n+\n+\tif (d_params->dynamic_sram_en) {\n+\t\tswitch (tbl->resource_type) {\n+\t\tcase TF_TBL_TYPE_ACT_ENCAP_8B:\n+\t\tcase TF_TBL_TYPE_ACT_ENCAP_16B:\n+\t\tcase TF_TBL_TYPE_ACT_ENCAP_32B:\n+\t\tcase TF_TBL_TYPE_ACT_ENCAP_64B:\n+\t\t\tsize_map = d_params->dyn_encap_sizes;\n+\t\t\tfor (i = 0; i < d_params->dyn_encap_list_size; i++) {\n+\t\t\t\tif (blob_len <= size_map[i].slab_size) {\n+\t\t\t\t\t*out_len = size_map[i].slab_size;\n+\t\t\t\t\treturn size_map[i].tbl_type;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase TF_TBL_TYPE_ACT_MODIFY_8B:\n+\t\tcase TF_TBL_TYPE_ACT_MODIFY_16B:\n+\t\tcase TF_TBL_TYPE_ACT_MODIFY_32B:\n+\t\tcase TF_TBL_TYPE_ACT_MODIFY_64B:\n+\t\t\tsize_map = d_params->dyn_modify_sizes;\n+\t\t\tfor (i = 0; i < d_params->dyn_modify_list_size; i++) {\n+\t\t\t\tif (blob_len <= size_map[i].slab_size) {\n+\t\t\t\t\t*out_len = size_map[i].slab_size;\n+\t\t\t\t\treturn size_map[i].tbl_type;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\treturn tbl->resource_type;\n+}\n+\n+static uint16_t\n+ulp_mapper_dyn_blob_size_get(struct bnxt_ulp_mapper_parms *mparms,\n+\t\t\t     struct bnxt_ulp_mapper_tbl_info *tbl)\n+{\n+\tstruct bnxt_ulp_device_params *d_params = mparms->device_params;\n+\n+\tif (d_params->dynamic_sram_en) {\n+\t\tswitch (tbl->resource_type) {\n+\t\tcase TF_TBL_TYPE_ACT_ENCAP_8B:\n+\t\tcase TF_TBL_TYPE_ACT_ENCAP_16B:\n+\t\tcase TF_TBL_TYPE_ACT_ENCAP_32B:\n+\t\tcase TF_TBL_TYPE_ACT_ENCAP_64B:\n+\t\tcase TF_TBL_TYPE_ACT_MODIFY_8B:\n+\t\tcase TF_TBL_TYPE_ACT_MODIFY_16B:\n+\t\tcase TF_TBL_TYPE_ACT_MODIFY_32B:\n+\t\tcase TF_TBL_TYPE_ACT_MODIFY_64B:\n+\t\t\t/* return max size */\n+\t\t\treturn BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t} else if (tbl->encap_num_fields) {\n+\t\treturn BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;\n+\t}\n+\treturn tbl->result_bit_size;\n+}\n+\n static inline int32_t\n ulp_mapper_tcam_entry_free(struct bnxt_ulp_context *ulp,\n \t\t\t   struct tf *tfp,\n@@ -1562,7 +1633,8 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,\n \tif (encap_flds) {\n \t\tuint32_t pad = 0;\n \t\t/* Initialize the encap blob */\n-\t\tif (!tbl->record_size) {\n+\t\tif (!tbl->record_size &&\n+\t\t    !parms->device_params->dynamic_sram_en) {\n \t\t\tBNXT_TF_DBG(ERR, \"Encap tbl record size incorrect\\n\");\n \t\t\treturn -EINVAL;\n \t\t}\n@@ -1583,9 +1655,21 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,\n \t\t\t}\n \t\t}\n \t\t/* add the dynamic pad push */\n-\t\tpad = ULP_BYTE_2_BITS(tbl->record_size) -\n-\t\t\tulp_blob_data_len_get(&encap_blob);\n-\t\tulp_blob_pad_push(&encap_blob, pad);\n+\t\tif (parms->device_params->dynamic_sram_en) {\n+\t\t\tuint16_t rec_s = ULP_BYTE_2_BITS(tbl->record_size);\n+\n+\t\t\t(void)ulp_mapper_dyn_tbl_type_get(parms, tbl,\n+\t\t\t\t\t\t\t  &encap_blob, &rec_s);\n+\t\t\tpad = rec_s - ulp_blob_data_len_get(&encap_blob);\n+\t\t} else {\n+\t\t\tpad = ULP_BYTE_2_BITS(tbl->record_size) -\n+\t\t\t\tulp_blob_data_len_get(&encap_blob);\n+\t\t}\n+\t\tif (ulp_blob_pad_push(&encap_blob, pad) < 0) {\n+\t\t\tBNXT_TF_DBG(ERR, \"encap buffer padding failed\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n \n \t\t/* perform the 64 bit byte swap */\n \t\tulp_blob_perform_64B_byte_swap(&encap_blob);\n@@ -2411,13 +2495,11 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,\n \tbool global = false;\n \tuint64_t act_rec_size;\n \tbool shared = false;\n+\tenum tf_tbl_type tbl_type = tbl->resource_type;\n \n \ttfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);\n-\t/* use the max size if encap is enabled */\n-\tif (tbl->encap_num_fields)\n-\t\tbit_size = BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;\n-\telse\n-\t\tbit_size = tbl->result_bit_size;\n+\t/* compute the blob size */\n+\tbit_size = ulp_mapper_dyn_blob_size_get(parms, tbl);\n \n \t/* Initialize the blob data */\n \tif (!ulp_blob_init(&data, bit_size,\n@@ -2526,7 +2608,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,\n \t\tgparms.dir = tbl->direction;\n \t\tgparms.type = tbl->resource_type;\n \t\tgparms.data = ulp_blob_data_get(&data, &tmplen);\n-\t\tgparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tbl->result_bit_size);\n+\t\tgparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);\n \t\tgparms.idx = index;\n \t\trc = tf_get_tbl_entry(tfp, &gparms);\n \t\tif (rc) {\n@@ -2568,14 +2650,16 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,\n \n \tif (alloc) {\n \t\taparms.dir\t\t= tbl->direction;\n-\t\taparms.type\t\t= tbl->resource_type;\n+\t\ttbl_type = ulp_mapper_dyn_tbl_type_get(parms, tbl,\n+\t\t\t\t\t\t       &data, &tmplen);\n+\t\taparms.type = tbl_type;\n \t\taparms.tbl_scope_id\t= tbl_scope_id;\n \n \t\t/* All failures after the alloc succeeds require a free */\n \t\trc = tf_alloc_tbl_entry(tfp, &aparms);\n \t\tif (rc) {\n \t\t\tBNXT_TF_DBG(ERR, \"Alloc table[%s][%s] failed rc=%d\\n\",\n-\t\t\t\t    tf_tbl_type_2_str(tbl->resource_type),\n+\t\t\t\t    tf_tbl_type_2_str(aparms.type),\n \t\t\t\t    tf_dir_2_str(tbl->direction), rc);\n \t\t\treturn rc;\n \t\t}\n@@ -2619,8 +2703,10 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,\n \n \tif (write) {\n \t\tsparms.dir = tbl->direction;\n-\t\tsparms.type = tbl->resource_type;\n \t\tsparms.data = ulp_blob_data_get(&data, &tmplen);\n+\t\ttbl_type = ulp_mapper_dyn_tbl_type_get(parms, tbl, &data,\n+\t\t\t\t\t\t       &tmplen);\n+\t\tsparms.type = tbl_type;\n \t\tsparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);\n \t\tsparms.idx = index;\n \t\tsparms.tbl_scope_id = tbl_scope_id;\n@@ -2655,7 +2741,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,\n \tmemset(&fid_parms, 0, sizeof(fid_parms));\n \tfid_parms.direction\t= tbl->direction;\n \tfid_parms.resource_func\t= tbl->resource_func;\n-\tfid_parms.resource_type\t= tbl->resource_type;\n+\tfid_parms.resource_type\t= tbl_type;\n \tfid_parms.resource_sub_type = tbl->resource_sub_type;\n \tfid_parms.resource_hndl\t= index;\n \tfid_parms.critical_resource = tbl->critical_resource;\n@@ -2684,7 +2770,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,\n \t * write to the entry or link the flow\n \t */\n \tfree_parms.dir\t= tbl->direction;\n-\tfree_parms.type\t= tbl->resource_type;\n+\tfree_parms.type\t= tbl_type;\n \tfree_parms.idx\t= index;\n \tfree_parms.tbl_scope_id = tbl_scope_id;\n \n@@ -2862,8 +2948,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,\n \tcache_key = ulp_blob_data_get(&key, &tmplen);\n #ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG\n #ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER\n-\tBNXT_TF_DBG(DEBUG, \"The gen_tbl[%u] key\\n\", tbl_idx);\n-\tulp_mapper_blob_dump(&key);\n+\tulp_mapper_gen_tbl_dump(tbl->resource_sub_type, tbl->direction, &key);\n #endif\n #endif\n \t/* get the generic table  */\n@@ -3310,18 +3395,10 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,\n \t\t*res = regval == 0;\n \t\tbreak;\n \tcase BNXT_ULP_COND_OPC_FLOW_PAT_MATCH:\n-\t\tif (parms->flow_pattern_id == operand) {\n-\t\t\tBNXT_TF_DBG(ERR, \"field pattern match failed %x\\n\",\n-\t\t\t\t    parms->flow_pattern_id);\n-\t\t\treturn -EINVAL;\n-\t\t}\n+\t\t*res = parms->flow_pattern_id == operand;\n \t\tbreak;\n \tcase BNXT_ULP_COND_OPC_ACT_PAT_MATCH:\n-\t\tif (parms->act_pattern_id == operand) {\n-\t\t\tBNXT_TF_DBG(ERR, \"act pattern match failed %x\\n\",\n-\t\t\t\t    parms->act_pattern_id);\n-\t\t\treturn -EINVAL;\n-\t\t}\n+\t\t*res = parms->act_pattern_id == operand;\n \t\tbreak;\n \tcase BNXT_ULP_COND_OPC_EXT_MEM_IS_SET:\n \t\tif (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) {\n@@ -3507,7 +3584,6 @@ ulp_mapper_func_info_process(struct bnxt_ulp_mapper_parms *parms,\n \treturn rc;\n }\n \n-\n /*\n  * Processes a list of conditions and returns both a status and result of the\n  * list.  The status must be checked prior to verifying the result.\n@@ -3863,8 +3939,7 @@ ulp_mapper_resources_free(struct bnxt_ulp_context *ulp_ctx,\n \t * Set the critical resource on the first resource del, then iterate\n \t * while status is good\n \t */\n-\tif (flow_type != BNXT_ULP_FDB_TYPE_RID)\n-\t\tres_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;\n+\tres_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;\n \n \trc = ulp_flow_db_resource_del(ulp_ctx, flow_type, fid, &res_parms);\n \ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c\nindex dce95de05c..3a9c9bba27 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c\n@@ -1226,20 +1226,66 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,\n \n /* Function to handle the update of proto header based on field values */\n static void\n-ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param,\n-\t\t\t     uint16_t dst_port)\n-{\n-\tif (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {\n-\t\tULP_BITMAP_SET(param->hdr_fp_bit.bits,\n-\t\t\t       BNXT_ULP_HDR_BIT_T_VXLAN);\n-\t\tULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);\n+ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *params,\n+\t\t\t     uint16_t src_port, uint16_t src_mask,\n+\t\t\t     uint16_t dst_port, uint16_t dst_mask,\n+\t\t\t     enum bnxt_ulp_hdr_bit hdr_bit)\n+{\n+\tswitch (hdr_bit) {\n+\tcase BNXT_ULP_HDR_BIT_I_UDP:\n+\tcase BNXT_ULP_HDR_BIT_I_TCP:\n+\t\tULP_BITMAP_SET(params->hdr_bitmap.bits, hdr_bit);\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,\n+\t\t\t\t    (uint64_t)rte_be_to_cpu_16(src_port));\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,\n+\t\t\t\t    (uint64_t)rte_be_to_cpu_16(dst_port));\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK,\n+\t\t\t\t    (uint64_t)rte_be_to_cpu_16(src_mask));\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK,\n+\t\t\t\t    (uint64_t)rte_be_to_cpu_16(dst_mask));\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,\n+\t\t\t\t    1);\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,\n+\t\t\t\t    !!(src_port & src_mask));\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,\n+\t\t\t\t    !!(dst_port & dst_mask));\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,\n+\t\t\t\t    (hdr_bit == BNXT_ULP_HDR_BIT_I_UDP) ?\n+\t\t\t\t    IPPROTO_UDP : IPPROTO_TCP);\n+\t\tbreak;\n+\tcase BNXT_ULP_HDR_BIT_O_UDP:\n+\tcase BNXT_ULP_HDR_BIT_O_TCP:\n+\t\tULP_BITMAP_SET(params->hdr_bitmap.bits, hdr_bit);\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,\n+\t\t\t\t    (uint64_t)rte_be_to_cpu_16(src_port));\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,\n+\t\t\t\t    (uint64_t)rte_be_to_cpu_16(dst_port));\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK,\n+\t\t\t\t    (uint64_t)rte_be_to_cpu_16(src_mask));\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK,\n+\t\t\t\t    (uint64_t)rte_be_to_cpu_16(dst_mask));\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,\n+\t\t\t\t    1);\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,\n+\t\t\t\t    !!(src_port & src_mask));\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,\n+\t\t\t\t    !!(dst_port & dst_mask));\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,\n+\t\t\t\t    (hdr_bit == BNXT_ULP_HDR_BIT_O_UDP) ?\n+\t\t\t\t    IPPROTO_UDP : IPPROTO_TCP);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n \t}\n \n-\tif (ULP_BITMAP_ISSET(param->hdr_bitmap.bits,\n-\t\t\t     BNXT_ULP_HDR_BIT_T_VXLAN) ||\n-\t    ULP_BITMAP_ISSET(param->hdr_bitmap.bits,\n-\t\t\t     BNXT_ULP_HDR_BIT_T_GRE))\n-\t\tULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);\n+\tif (hdr_bit == BNXT_ULP_HDR_BIT_O_UDP && dst_port ==\n+\t    tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {\n+\t\tULP_BITMAP_SET(params->hdr_fp_bit.bits,\n+\t\t\t       BNXT_ULP_HDR_BIT_T_VXLAN);\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);\n+\t}\n }\n \n /* Function to handle the parsing of RTE Flow item UDP Header. */\n@@ -1253,7 +1299,9 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,\n \tuint32_t idx = 0;\n \tuint32_t size;\n \tuint16_t dport = 0, sport = 0;\n+\tuint16_t dport_mask = 0, sport_mask = 0;\n \tuint32_t cnt;\n+\tenum bnxt_ulp_hdr_bit out_l4 = BNXT_ULP_HDR_BIT_O_UDP;\n \n \tcnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT);\n \tif (cnt == 2) {\n@@ -1265,6 +1313,10 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,\n \t\tsport = udp_spec->hdr.src_port;\n \t\tdport = udp_spec->hdr.dst_port;\n \t}\n+\tif (udp_mask) {\n+\t\tsport_mask = udp_mask->hdr.src_port;\n+\t\tdport_mask = udp_mask->hdr.dst_port;\n+\t}\n \n \tif (ulp_rte_prsr_fld_size_validate(params, &idx,\n \t\t\t\t\t   BNXT_ULP_PROTO_HDR_UDP_NUM)) {\n@@ -1302,48 +1354,11 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,\n \n \t/* Set the udp header bitmap and computed l4 header bitmaps */\n \tif (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||\n-\t    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_UDP);\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,\n-\t\t\t\t    (uint32_t)rte_be_to_cpu_16(sport));\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,\n-\t\t\t\t    (uint32_t)rte_be_to_cpu_16(dport));\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,\n-\t\t\t\t    1);\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,\n-\t\t\t\t    IPPROTO_UDP);\n-\t\tif (udp_mask && udp_mask->hdr.src_port)\n-\t\t\tULP_COMP_FLD_IDX_WR(params,\n-\t\t\t\t\t    BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,\n-\t\t\t\t\t    1);\n-\t\tif (udp_mask && udp_mask->hdr.dst_port)\n-\t\t\tULP_COMP_FLD_IDX_WR(params,\n-\t\t\t\t\t    BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,\n-\t\t\t\t\t    1);\n-\t} else {\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP);\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,\n-\t\t\t\t    (uint32_t)rte_be_to_cpu_16(sport));\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,\n-\t\t\t\t    (uint32_t)rte_be_to_cpu_16(dport));\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,\n-\t\t\t\t    1);\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,\n-\t\t\t\t    IPPROTO_UDP);\n-\t\tif (udp_mask && udp_mask->hdr.src_port)\n-\t\t\tULP_COMP_FLD_IDX_WR(params,\n-\t\t\t\t\t    BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,\n-\t\t\t\t\t    1);\n-\t\tif (udp_mask && udp_mask->hdr.dst_port)\n-\t\t\tULP_COMP_FLD_IDX_WR(params,\n-\t\t\t\t\t    BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,\n-\t\t\t\t\t    1);\n+\t    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP))\n+\t\tout_l4 = BNXT_ULP_HDR_BIT_I_UDP;\n \n-\t\t/* Update the field protocol hdr bitmap */\n-\t\tulp_rte_l4_proto_type_update(params, dport);\n-\t}\n+\tulp_rte_l4_proto_type_update(params, sport, sport_mask, dport,\n+\t\t\t\t     dport_mask, out_l4);\n \tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt);\n \treturn BNXT_TF_RC_SUCCESS;\n }\n@@ -1358,8 +1373,10 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,\n \tstruct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;\n \tuint32_t idx = 0;\n \tuint16_t dport = 0, sport = 0;\n+\tuint16_t dport_mask = 0, sport_mask = 0;\n \tuint32_t size;\n \tuint32_t cnt;\n+\tenum bnxt_ulp_hdr_bit out_l4 = BNXT_ULP_HDR_BIT_O_TCP;\n \n \tcnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT);\n \tif (cnt == 2) {\n@@ -1371,6 +1388,10 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,\n \t\tsport = tcp_spec->hdr.src_port;\n \t\tdport = tcp_spec->hdr.dst_port;\n \t}\n+\tif (tcp_mask) {\n+\t\tsport_mask = tcp_mask->hdr.src_port;\n+\t\tdport_mask = tcp_mask->hdr.dst_port;\n+\t}\n \n \tif (ulp_rte_prsr_fld_size_validate(params, &idx,\n \t\t\t\t\t   BNXT_ULP_PROTO_HDR_TCP_NUM)) {\n@@ -1438,45 +1459,11 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,\n \n \t/* Set the udp header bitmap and computed l4 header bitmaps */\n \tif (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||\n-\t    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_TCP);\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,\n-\t\t\t\t    (uint32_t)rte_be_to_cpu_16(sport));\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,\n-\t\t\t\t    (uint32_t)rte_be_to_cpu_16(dport));\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,\n-\t\t\t\t    1);\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,\n-\t\t\t\t    IPPROTO_TCP);\n-\t\tif (tcp_mask && tcp_mask->hdr.src_port)\n-\t\t\tULP_COMP_FLD_IDX_WR(params,\n-\t\t\t\t\t    BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,\n-\t\t\t\t\t    1);\n-\t\tif (tcp_mask && tcp_mask->hdr.dst_port)\n-\t\t\tULP_COMP_FLD_IDX_WR(params,\n-\t\t\t\t\t    BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,\n-\t\t\t\t\t    1);\n-\t} else {\n-\t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP);\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,\n-\t\t\t\t    (uint32_t)rte_be_to_cpu_16(sport));\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,\n-\t\t\t\t    (uint32_t)rte_be_to_cpu_16(dport));\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,\n-\t\t\t\t    1);\n-\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,\n-\t\t\t\t    IPPROTO_TCP);\n-\t\tif (tcp_mask && tcp_mask->hdr.src_port)\n-\t\t\tULP_COMP_FLD_IDX_WR(params,\n-\t\t\t\t\t    BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,\n-\t\t\t\t\t    1);\n-\t\tif (tcp_mask && tcp_mask->hdr.dst_port)\n-\t\t\tULP_COMP_FLD_IDX_WR(params,\n-\t\t\t\t\t    BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,\n-\t\t\t\t\t    1);\n-\t}\n+\t    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP))\n+\t\tout_l4 = BNXT_ULP_HDR_BIT_I_TCP;\n+\n+\tulp_rte_l4_proto_type_update(params, sport, sport_mask, dport,\n+\t\t\t\t     dport_mask, out_l4);\n \tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt);\n \treturn BNXT_TF_RC_SUCCESS;\n }\n@@ -1528,7 +1515,7 @@ ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item,\n \n \t/* Update the hdr_bitmap with vxlan */\n \tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_VXLAN);\n-\tulp_rte_l4_proto_type_update(params, 0);\n+\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);\n \treturn BNXT_TF_RC_SUCCESS;\n }\n \n@@ -1563,7 +1550,7 @@ ulp_rte_gre_hdr_handler(const struct rte_flow_item *item,\n \n \t/* Update the hdr_bitmap with GRE */\n \tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE);\n-\tulp_rte_l4_proto_type_update(params, 0);\n+\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);\n \treturn BNXT_TF_RC_SUCCESS;\n }\n \ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\nindex 1683cd7ec4..d3bfb8c12d 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\n@@ -206,6 +206,11 @@ struct bnxt_ulp_template_device_tbls {\n \tuint32_t cond_list_size;\n };\n \n+struct bnxt_ulp_dyn_size_map {\n+\tuint32_t\t\tslab_size;\n+\tenum tf_tbl_type\ttbl_type;\n+};\n+\n /* Device specific parameters */\n struct bnxt_ulp_device_params {\n \tuint8_t\t\t\t\tdescription[16];\n@@ -229,6 +234,11 @@ struct bnxt_ulp_device_params {\n \tuint32_t\t\t\tbyte_count_shift;\n \tuint32_t\t\t\tpacket_count_shift;\n \tuint32_t\t\t\tdynamic_pad_en;\n+\tuint32_t\t\t\tdynamic_sram_en;\n+\tuint32_t\t\t\tdyn_encap_list_size;\n+\tstruct bnxt_ulp_dyn_size_map\tdyn_encap_sizes[4];\n+\tuint32_t\t\t\tdyn_modify_list_size;\n+\tstruct bnxt_ulp_dyn_size_map\tdyn_modify_sizes[4];\n \tuint16_t\t\t\tem_blk_size_bits;\n \tuint16_t\t\t\tem_blk_align_bits;\n \tuint16_t\t\t\tem_key_align_bytes;\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c\nindex 686b80e456..df3afaa6fd 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c\n@@ -882,7 +882,8 @@ ulp_blob_msb_block_merge(struct ulp_blob *dst, struct ulp_blob *src,\n \n \tfor (i = 0; i < num;) {\n \t\tif (((dst->write_idx % block_size)  + (num - i)) > block_size)\n-\t\t\twrite_bytes = block_size - dst->write_idx;\n+\t\t\twrite_bytes = block_size -\n+\t\t\t\t(dst->write_idx % block_size);\n \t\telse\n \t\t\twrite_bytes = num - i;\n \t\tfor (k = 0; k < ULP_BITS_2_BYTE_NR(write_bytes); k++) {\n",
    "prefixes": [
        "v3",
        "13/13"
    ]
}