Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/98038/?format=api
{ "id": 98038, "url": "http://patches.dpdk.org/api/patches/98038/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210906075450.1452123-1-skori@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210906075450.1452123-1-skori@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210906075450.1452123-1-skori@marvell.com", "date": "2021-09-06T07:54:24", "name": "[01/27] common/cnxk: update policer MBOX APIs and HW definitions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1869b6219b6b078642bcc93a0d5a7bde4e54fcdd", "submitter": { "id": 1318, "url": "http://patches.dpdk.org/api/people/1318/?format=api", "name": "Sunil Kumar Kori", "email": "skori@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210906075450.1452123-1-skori@marvell.com/mbox/", "series": [ { "id": 18696, "url": "http://patches.dpdk.org/api/series/18696/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18696", "date": "2021-09-06T07:54:24", "name": "[01/27] common/cnxk: update policer MBOX APIs and HW definitions", "version": 1, "mbox": "http://patches.dpdk.org/series/18696/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/98038/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/98038/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A4ED5A0C4D;\n\tMon, 6 Sep 2021 09:55:03 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1C64F40E32;\n\tMon, 6 Sep 2021 09:55:03 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id EF72640C35\n for <dev@dpdk.org>; Mon, 6 Sep 2021 09:55:00 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 185Mv83V015512\n for <dev@dpdk.org>; Mon, 6 Sep 2021 00:55:00 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 3aw2sp1sjm-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 06 Sep 2021 00:55:00 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 6 Sep 2021 00:54:58 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 6 Sep 2021 00:54:58 -0700", "from localhost.localdomain (unknown [10.28.34.25])\n by maili.marvell.com (Postfix) with ESMTP id 7EDB13F7089;\n Mon, 6 Sep 2021 00:54:56 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=woktWaqvib2uBvSOTOEkXa9K0hpQGfkJ56IZMrb8E3o=;\n b=NBtHS/XjTjbkTZ0Fi0Ln8oNYKl7cWbP+GPFmu7V6za+U2RJk88fKQ0zlpA6ckvE2tSND\n JxZQHeGlYCzUrNCwqRZEwzGY9XxqReXNCDSC3dAU/il11RKxhgfShcKogKae/hXR3FX1\n 84HWTQ5aPvv6QL8Y9MqI1M2RVwjWVIc8W6xYisZr17qYoZHrvFuf/DwkAzPcRC2S7jl7\n u5yoeaAWfHhMpyvOArtISgJsHKv93uL1ZgEdE8fQ1E+ahruipgv+MIMDC42gK934wCI7\n 9Z92kh8SXuBkkONT2zHkUlH/zTEqplGr/yhHn9kiixgJLZNU8PFGxMHUEGq+KHq8SzH0 GQ==", "From": "<skori@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 6 Sep 2021 13:24:24 +0530", "Message-ID": "<20210906075450.1452123-1-skori@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "Jz0ADOaUm4PY6qsbjtXGOZq0pESj_fXJ", "X-Proofpoint-ORIG-GUID": "Jz0ADOaUm4PY6qsbjtXGOZq0pESj_fXJ", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-09-06_02,2021-09-03_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH 01/27] common/cnxk: update policer MBOX APIs and\n HW definitions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nTo support ingress policer on CN10K, MBOX interfaces and HW\ndefinitions are synced.\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n drivers/common/cnxk/hw/nix.h | 13 ++++++++++---\n drivers/common/cnxk/roc_mbox.h | 34 +++++++++++++++++++++++++++++++++-\n 2 files changed, 43 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h\nindex 6b86002ead..53cdfbb142 100644\n--- a/drivers/common/cnxk/hw/nix.h\n+++ b/drivers/common/cnxk/hw/nix.h\n@@ -692,9 +692,16 @@\n #define NIX_RX_BAND_PROF_ACTIONRESULT_DROP (0x1ull) /* [CN10K, .) */\n #define NIX_RX_BAND_PROF_ACTIONRESULT_RED (0x2ull) /* [CN10K, .) */\n \n-#define NIX_RX_BAND_PROF_LAYER_LEAF (0x0ull) /* [CN10K, .) */\n-#define NIX_RX_BAND_PROF_LAYER_MIDDLE (0x1ull) /* [CN10K, .) */\n-#define NIX_RX_BAND_PROF_LAYER_TOP (0x2ull) /* [CN10K, .) */\n+#define NIX_RX_BAND_PROF_LAYER_LEAF (0x0ull) /* [CN10K, .) */\n+#define NIX_RX_BAND_PROF_LAYER_INVALID (0x1ull) /* [CN10K, .) */\n+#define NIX_RX_BAND_PROF_LAYER_MIDDLE (0x2ull) /* [CN10K, .) */\n+#define NIX_RX_BAND_PROF_LAYER_TOP (0x3ull) /* [CN10K, .) */\n+#define NIX_RX_BAND_PROF_LAYER_MAX (0x4ull) /* [CN10K, .) */\n+\n+#define NIX_RX_BAND_PROF_PC_MODE_VLAN (0x0ull) /* [CN10K, .) */\n+#define NIX_RX_BAND_PROF_PC_MODE_DSCP (0x1ull) /* [CN10K, .) */\n+#define NIX_RX_BAND_PROF_PC_MODE_GEN (0x2ull) /* [CN10K, .) */\n+#define NIX_RX_BAND_PROF_PC_MODE_RSVD (0x3ull) /* [CN10K, .) */\n \n #define NIX_RX_COLORRESULT_GREEN (0x0ull) /* [CN10K, .) */\n #define NIX_RX_COLORRESULT_YELLOW (0x1ull) /* [CN10K, .) */\ndiff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex b5da931b81..c8b97e9aee 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -234,7 +234,11 @@ struct mbox_msghdr {\n \t nix_inline_ipsec_lf_cfg, msg_rsp) \\\n \tM(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \\\n \t nix_cn10k_aq_enq_rsp) \\\n-\tM(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info)\n+\tM(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \\\n+\tM(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, \\\n+\t nix_bandprof_alloc_req, nix_bandprof_alloc_rsp) \\\n+\tM(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \\\n+\t msg_rsp)\n \n /* Messages initiated by AF (range 0xC00 - 0xDFF) */\n #define MBOX_UP_CGX_MESSAGES \\\n@@ -771,6 +775,10 @@ struct nix_cn10k_aq_enq_req {\n \t\t__io struct nix_rsse_s rss;\n \t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */\n \t\t__io struct nix_rx_mce_s mce;\n+\t\t/* Valid when op == WRITE/INIT and\n+\t\t * ctype == NIX_AQ_CTYPE_BAND_PROF\n+\t\t */\n+\t\t__io struct nix_band_prof_s prof;\n \t};\n \t/* Mask data when op == WRITE (1=write, 0=don't write) */\n \tunion {\n@@ -784,6 +792,8 @@ struct nix_cn10k_aq_enq_req {\n \t\t__io struct nix_rsse_s rss_mask;\n \t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */\n \t\t__io struct nix_rx_mce_s mce_mask;\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_BAND_PROF */\n+\t\t__io struct nix_band_prof_s prof_mask;\n \t};\n };\n \n@@ -795,6 +805,7 @@ struct nix_cn10k_aq_enq_rsp {\n \t\tstruct nix_cq_ctx_s cq;\n \t\tstruct nix_rsse_s rss;\n \t\tstruct nix_rx_mce_s mce;\n+\t\tstruct nix_band_prof_s prof;\n \t};\n };\n \n@@ -1129,6 +1140,27 @@ struct nix_hw_info {\n \tuint16_t __io rsvd[15];\n };\n \n+struct nix_bandprof_alloc_req {\n+\tstruct mbox_msghdr hdr;\n+\t/* Count of profiles needed per layer */\n+\tuint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];\n+};\n+\n+struct nix_bandprof_alloc_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];\n+\n+#define BANDPROF_PER_PFFUNC 64\n+\tuint16_t __io prof_idx[NIX_RX_BAND_PROF_LAYER_MAX][BANDPROF_PER_PFFUNC];\n+};\n+\n+struct nix_bandprof_free_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io free_all;\n+\tuint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];\n+\tuint16_t __io prof_idx[NIX_RX_BAND_PROF_LAYER_MAX][BANDPROF_PER_PFFUNC];\n+};\n+\n /* SSO mailbox error codes\n * Range 501 - 600.\n */\n", "prefixes": [ "01/27" ] }