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GET /api/patches/97733/?format=api
{ "id": 97733, "url": "http://patches.dpdk.org/api/patches/97733/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210902021505.17607-9-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210902021505.17607-9-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210902021505.17607-9-ndabilpuram@marvell.com", "date": "2021-09-02T02:14:46", "name": "[08/27] common/cnxk: dump cpt lf registers on error intr", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "dbf8ac13325a41e701ed9bf552ac31ba534c2f64", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210902021505.17607-9-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 18612, "url": "http://patches.dpdk.org/api/series/18612/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18612", "date": "2021-09-02T02:14:38", "name": "net/cnxk: support for inline ipsec", "version": 1, "mbox": "http://patches.dpdk.org/series/18612/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/97733/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/97733/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AF54EA0C4C;\n\tThu, 2 Sep 2021 04:17:33 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BF8FD410EA;\n\tThu, 2 Sep 2021 04:17:11 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id C342D410EA\n for <dev@dpdk.org>; Thu, 2 Sep 2021 04:17:09 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 181K5SYj027320\n for <dev@dpdk.org>; Wed, 1 Sep 2021 19:17:09 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 3atg8a91h4-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 01 Sep 2021 19:17:08 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Wed, 1 Sep 2021 19:17:07 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Wed, 1 Sep 2021 19:17:07 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 4DE4B3F704D;\n Wed, 1 Sep 2021 19:17:05 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=eHZsMW8bkw1WaiP4DG9B9rVEcb6KEgERNiS8rMahLsY=;\n b=KO5aX+32/cjl7I1GEAapNr5DReJjgBJTdIEwDS8ll6addgamcUn1uNLPVz8duMxxj6dZ\n xALIdiPSfSuLTjKEApbpAQkv8gQB53FUZVHuUlkwMcyeuOA59hoEkJfaTpTM0tcCN6MC\n hsTGuMGiCe4idojgq9mBcuSbcUr1Qu8xFcMgNn0OPQLvq+hCkMLXemDht/VPlBJX5yZe\n dc7GPwQCAHI7iECmF7eFYvegpZ7RWTvLxsSHC4ydCiFRcrbHzAggo4R+CWYwRGInTnZX\n fFHhIM2GdNskPne0oSgg8TA2+c9r6MhzZK6mjnrC3vU15Do91DTsld5CGwRBH35BKWzj GA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <schalla@marvell.com>, <dev@dpdk.org>", "Date": "Thu, 2 Sep 2021 07:44:46 +0530", "Message-ID": "<20210902021505.17607-9-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210902021505.17607-1-ndabilpuram@marvell.com>", "References": "<20210902021505.17607-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "10pWd-VwpXagIGlrmlv9dmU1R3hKo9u-", "X-Proofpoint-ORIG-GUID": "10pWd-VwpXagIGlrmlv9dmU1R3hKo9u-", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-09-01_05,2021-09-01_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH 08/27] common/cnxk: dump cpt lf registers on\n error intr", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Dump CPT LF registers on error interrupt.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_cpt.c | 5 ++++-\n drivers/common/cnxk/roc_cpt_debug.c | 32 ++++++++++++++++++++++++++++++--\n drivers/common/cnxk/roc_cpt_priv.h | 1 +\n 3 files changed, 35 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c\nindex 3222b3e..f08b5d0 100644\n--- a/drivers/common/cnxk/roc_cpt.c\n+++ b/drivers/common/cnxk/roc_cpt.c\n@@ -51,6 +51,9 @@ cpt_lf_misc_irq(void *param)\n \n \tplt_err(\"Err_irq=0x%\" PRIx64 \" pf=%d, vf=%d\", intr, dev->pf, dev->vf);\n \n+\t/* Dump lf registers */\n+\tcpt_lf_print(lf);\n+\n \t/* Clear interrupt */\n \tplt_write64(intr, lf->rbase + CPT_LF_MISC_INT);\n }\n@@ -203,7 +206,7 @@ cpt_lf_dump(struct roc_cpt_lf *lf)\n \tplt_cpt_dbg(\"CPT LF REG:\");\n \tplt_cpt_dbg(\"LF_CTL[0x%016llx]: 0x%016\" PRIx64, CPT_LF_CTL,\n \t\t plt_read64(lf->rbase + CPT_LF_CTL));\n-\tplt_cpt_dbg(\"Q_SIZE[0x%016llx]: 0x%016\" PRIx64, CPT_LF_INPROG,\n+\tplt_cpt_dbg(\"LF_INPROG[0x%016llx]: 0x%016\" PRIx64, CPT_LF_INPROG,\n \t\t plt_read64(lf->rbase + CPT_LF_INPROG));\n \n \tplt_cpt_dbg(\"Q_BASE[0x%016llx]: 0x%016\" PRIx64, CPT_LF_Q_BASE,\ndiff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c\nindex a6c9004..847d969 100644\n--- a/drivers/common/cnxk/roc_cpt_debug.c\n+++ b/drivers/common/cnxk/roc_cpt_debug.c\n@@ -157,11 +157,40 @@ roc_cpt_afs_print(struct roc_cpt *roc_cpt)\n \treturn 0;\n }\n \n-static void\n+void\n cpt_lf_print(struct roc_cpt_lf *lf)\n {\n \tuint64_t reg_val;\n \n+\treg_val = plt_read64(lf->rbase + CPT_LF_Q_BASE);\n+\tplt_print(\" CPT_LF_Q_BASE:\\t%016lx\", reg_val);\n+\n+\treg_val = plt_read64(lf->rbase + CPT_LF_Q_SIZE);\n+\tplt_print(\" CPT_LF_Q_SIZE:\\t%016lx\", reg_val);\n+\n+\treg_val = plt_read64(lf->rbase + CPT_LF_Q_INST_PTR);\n+\tplt_print(\" CPT_LF_Q_INST_PTR:\\t%016lx\", reg_val);\n+\n+\treg_val = plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR);\n+\tplt_print(\" CPT_LF_Q_GRP_PTR:\\t%016lx\", reg_val);\n+\n+\treg_val = plt_read64(lf->rbase + CPT_LF_CTL);\n+\tplt_print(\" CPT_LF_CTL:\\t%016lx\", reg_val);\n+\n+\treg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT_ENA_W1S);\n+\tplt_print(\" CPT_LF_MISC_INT_ENA_W1S:\\t%016lx\", reg_val);\n+\n+\treg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT);\n+\tplt_print(\" CPT_LF_MISC_INT:\\t%016lx\", reg_val);\n+\n+\treg_val = plt_read64(lf->rbase + CPT_LF_INPROG);\n+\tplt_print(\" CPT_LF_INPROG:\\t%016lx\", reg_val);\n+\n+\tif (roc_model_is_cn9k())\n+\t\treturn;\n+\n+\tplt_print(\"Count registers for CPT LF%d:\", lf->lf_id);\n+\n \treg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT);\n \tplt_print(\" Encrypted byte count:\\t%\" PRIu64, reg_val);\n \n@@ -190,7 +219,6 @@ roc_cpt_lfs_print(struct roc_cpt *roc_cpt)\n \t\tif (lf == NULL)\n \t\t\tcontinue;\n \n-\t\tplt_print(\"Count registers for CPT LF%d:\", lf_id);\n \t\tcpt_lf_print(lf);\n \t}\n \ndiff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h\nindex 21911e5..61dec9a 100644\n--- a/drivers/common/cnxk/roc_cpt_priv.h\n+++ b/drivers/common/cnxk/roc_cpt_priv.h\n@@ -31,5 +31,6 @@ int cpt_lf_outb_cfg(struct dev *dev, uint16_t sso_pf_func, uint16_t nix_pf_func,\n \t\t uint8_t lf_id, bool ena);\n int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp);\n uint64_t cpt_get_blkaddr(struct dev *dev);\n+void cpt_lf_print(struct roc_cpt_lf *lf);\n \n #endif /* _ROC_CPT_PRIV_H_ */\n", "prefixes": [ "08/27" ] }