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GET /api/patches/97561/?format=api
{ "id": 97561, "url": "http://patches.dpdk.org/api/patches/97561/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210830162903.2736191-1-asekhar@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210830162903.2736191-1-asekhar@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210830162903.2736191-1-asekhar@marvell.com", "date": "2021-08-30T16:29:02", "name": "[1/2] common/cnxk: update roc models", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5ef2a1a7ce22c5f160813a60debcef143d6d1cff", "submitter": { "id": 2125, "url": "http://patches.dpdk.org/api/people/2125/?format=api", "name": "Ashwin Sekhar T K", "email": "asekhar@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210830162903.2736191-1-asekhar@marvell.com/mbox/", "series": [ { "id": 18535, "url": "http://patches.dpdk.org/api/series/18535/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18535", "date": "2021-08-30T16:29:02", "name": "[1/2] common/cnxk: update roc models", "version": 1, "mbox": "http://patches.dpdk.org/series/18535/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/97561/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/97561/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5A066A0547;\n\tMon, 30 Aug 2021 18:30:32 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 14EAB410F2;\n\tMon, 30 Aug 2021 18:30:32 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 8DA3E410EA\n for <dev@dpdk.org>; Mon, 30 Aug 2021 18:30:30 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 17U9uWtA009916\n for <dev@dpdk.org>; Mon, 30 Aug 2021 09:30:29 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 3arj9m31rg-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 30 Aug 2021 09:30:29 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 30 Aug 2021 09:30:27 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 30 Aug 2021 09:30:27 -0700", "from lab-ci-142.marvell.com (unknown [10.28.36.142])\n by maili.marvell.com (Postfix) with ESMTP id 9EA263F707C;\n Mon, 30 Aug 2021 09:30:24 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=rDOZmieWwr+n1rRAr7SWH4SJanhkJ7aspDr83wdUS3Y=;\n b=dk/jiMFvszfoWt7AS5cpjYagjoj3aseqm80yM0dWPLd9zcjIJGKvJSCDI+0odgM17bWp\n vb+fUDow9rZkvsMFPYEVVWBHV9Btc5NjR37KoYans3tQLJss3PwxwFb35y9KMskrke+D\n Huu1HF2eYz8I66PMb+SRDP4RADXaMWs2OFCO5A8cqOw611S00id9UqXIkdqMjw/yP/UT\n 5JW9yBhrYlEDUFN8RP+19PpQ47TQQe872P7vdxwUhcJme4Qyhsw4Mt2Dra1ZNDxFoUm5\n fvPXnZ5rkWs475giotPynOafHVxrdmaHShEOcqpY+sPgT+esJUQ6aK8YZ/kgKvJoMJR8 zQ==", "From": "Ashwin Sekhar T K <asekhar@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>,\n <ndabilpuram@marvell.com>, <gakhil@marvell.com>", "Date": "Mon, 30 Aug 2021 21:59:02 +0530", "Message-ID": "<20210830162903.2736191-1-asekhar@marvell.com>", "X-Mailer": "git-send-email 2.32.0", "In-Reply-To": "<20210830140819.2610366-1-asekhar@marvell.com>", "References": "<20210830140819.2610366-1-asekhar@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "9G72PhhctkOoNgHqcT3Vva08rHaKSlvb", "X-Proofpoint-ORIG-GUID": "9G72PhhctkOoNgHqcT3Vva08rHaKSlvb", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-08-30_05,2021-08-30_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH 1/2] common/cnxk: update roc models", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update roc models.\n\nSigned-off-by: Ashwin Sekhar T K <asekhar@marvell.com>\n---\n drivers/common/cnxk/roc_model.c | 51 +++++++++++++++----------------\n drivers/common/cnxk/roc_model.h | 53 +++++++++++++++++++++++++--------\n 2 files changed, 67 insertions(+), 37 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c\nindex bc255b53cc..e5aeabe2e2 100644\n--- a/drivers/common/cnxk/roc_model.c\n+++ b/drivers/common/cnxk/roc_model.c\n@@ -13,14 +13,14 @@ struct roc_model *roc_model;\n \n #define SOC_PART_CN10K 0xD49\n \n-#define PART_106XX 0xB9\n-#define PART_105XX 0xBA\n-#define PART_105XXN 0xBC\n-#define PART_98XX 0xB1\n-#define PART_96XX 0xB2\n-#define PART_95XX 0xB3\n-#define PART_95XXN 0xB4\n-#define PART_95XXMM 0xB5\n+#define PART_106xx 0xB9\n+#define PART_105xx 0xBA\n+#define PART_105xxN 0xBC\n+#define PART_98xx 0xB1\n+#define PART_96xx 0xB2\n+#define PART_95xx 0xB3\n+#define PART_95xxN 0xB4\n+#define PART_95xxMM 0xB5\n #define PART_95O 0xB6\n \n #define MODEL_IMPL_BITS\t 8\n@@ -44,20 +44,21 @@ static const struct model_db {\n \tuint64_t flag;\n \tchar name[ROC_MODEL_STR_LEN_MAX];\n } model_db[] = {\n-\t{VENDOR_ARM, PART_106XX, 0, 0, ROC_MODEL_CN106XX, \"cn10ka\"},\n-\t{VENDOR_ARM, PART_105XX, 0, 0, ROC_MODEL_CNF105XX, \"cnf10ka\"},\n-\t{VENDOR_ARM, PART_105XXN, 0, 0, ROC_MODEL_CNF105XXN, \"cnf10kb\"},\n-\t{VENDOR_CAVIUM, PART_98XX, 0, 0, ROC_MODEL_CN98xx_A0, \"cn98xx_a0\"},\n-\t{VENDOR_CAVIUM, PART_96XX, 0, 0, ROC_MODEL_CN96xx_A0, \"cn96xx_a0\"},\n-\t{VENDOR_CAVIUM, PART_96XX, 0, 1, ROC_MODEL_CN96xx_B0, \"cn96xx_b0\"},\n-\t{VENDOR_CAVIUM, PART_96XX, 2, 0, ROC_MODEL_CN96xx_C0, \"cn96xx_c0\"},\n-\t{VENDOR_CAVIUM, PART_95XX, 0, 0, ROC_MODEL_CNF95xx_A0, \"cnf95xx_a0\"},\n-\t{VENDOR_CAVIUM, PART_95XX, 1, 0, ROC_MODEL_CNF95xx_B0, \"cnf95xx_b0\"},\n-\t{VENDOR_CAVIUM, PART_95XXN, 0, 0, ROC_MODEL_CNF95XXN_A0, \"cnf95xxn_a0\"},\n-\t{VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95XXO_A0, \"cnf95O_a0\"},\n-\t{VENDOR_CAVIUM, PART_95XXMM, 0, 0, ROC_MODEL_CNF95XXMM_A0,\n-\t \"cnf95xxmm_a0\"}\n-};\n+\t{VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, \"cn10ka_a0\"},\n+\t{VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, \"cnf10ka_a0\"},\n+\t{VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, \"cnf10kb_a0\"},\n+\t{VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, \"cn98xx_a0\"},\n+\t{VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, \"cn96xx_a0\"},\n+\t{VENDOR_CAVIUM, PART_96xx, 0, 1, ROC_MODEL_CN96xx_B0, \"cn96xx_b0\"},\n+\t{VENDOR_CAVIUM, PART_96xx, 2, 0, ROC_MODEL_CN96xx_C0, \"cn96xx_c0\"},\n+\t{VENDOR_CAVIUM, PART_96xx, 2, 1, ROC_MODEL_CN96xx_C0, \"cn96xx_c1\"},\n+\t{VENDOR_CAVIUM, PART_95xx, 0, 0, ROC_MODEL_CNF95xx_A0, \"cnf95xx_a0\"},\n+\t{VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, \"cnf95xx_b0\"},\n+\t{VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, \"cnf95xxn_a0\"},\n+\t{VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, \"cnf95xxn_a1\"},\n+\t{VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, \"cnf95O_a0\"},\n+\t{VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,\n+\t \"cnf95xxmm_a0\"}};\n \n static uint32_t\n cn10k_part_get(void)\n@@ -85,11 +86,11 @@ cn10k_part_get(void)\n \t}\n \tptr++;\n \tif (strcmp(\"cn10ka\", ptr) == 0) {\n-\t\tsoc = PART_106XX;\n+\t\tsoc = PART_106xx;\n \t} else if (strcmp(\"cnf10ka\", ptr) == 0) {\n-\t\tsoc = PART_105XX;\n+\t\tsoc = PART_105xx;\n \t} else if (strcmp(\"cnf10kb\", ptr) == 0) {\n-\t\tsoc = PART_105XXN;\n+\t\tsoc = PART_105xxN;\n \t} else {\n \t\tplt_err(\"Unidentified 'CPU compatible': <%s>\", ptr);\n \t\tgoto fclose;\ndiff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h\nindex c1d11b77c6..a54f435b46 100644\n--- a/drivers/common/cnxk/roc_model.h\n+++ b/drivers/common/cnxk/roc_model.h\n@@ -15,13 +15,14 @@ struct roc_model {\n #define ROC_MODEL_CN96xx_C0 BIT_ULL(2)\n #define ROC_MODEL_CNF95xx_A0 BIT_ULL(4)\n #define ROC_MODEL_CNF95xx_B0 BIT_ULL(6)\n-#define ROC_MODEL_CNF95XXMM_A0 BIT_ULL(8)\n-#define ROC_MODEL_CNF95XXN_A0 BIT_ULL(12)\n-#define ROC_MODEL_CNF95XXO_A0 BIT_ULL(13)\n+#define ROC_MODEL_CNF95xxMM_A0 BIT_ULL(8)\n+#define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12)\n+#define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13)\n+#define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14)\n #define ROC_MODEL_CN98xx_A0 BIT_ULL(16)\n-#define ROC_MODEL_CN106XX BIT_ULL(20)\n-#define ROC_MODEL_CNF105XX BIT_ULL(21)\n-#define ROC_MODEL_CNF105XXN BIT_ULL(22)\n+#define ROC_MODEL_CN106xx_A0 BIT_ULL(20)\n+#define ROC_MODEL_CNF105xx_A0 BIT_ULL(21)\n+#define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22)\n \n \tuint64_t flag;\n #define ROC_MODEL_STR_LEN_MAX 128\n@@ -31,11 +32,15 @@ struct roc_model {\n #define ROC_MODEL_CN96xx_Ax (ROC_MODEL_CN96xx_A0 | ROC_MODEL_CN96xx_B0)\n #define ROC_MODEL_CN9K \\\n \t(ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \\\n-\t ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95XXMM_A0 | \\\n-\t ROC_MODEL_CNF95XXO_A0 | ROC_MODEL_CNF95XXN_A0 | ROC_MODEL_CN98xx_A0)\n+\t ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \\\n+\t ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \\\n+\t ROC_MODEL_CNF95xxN_A1)\n \n+#define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0)\n+#define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0)\n+#define ROC_MODEL_CNF105xxN (ROC_MODEL_CNF105xxN_A0)\n #define ROC_MODEL_CN10K \\\n-\t(ROC_MODEL_CN106XX | ROC_MODEL_CNF105XX | ROC_MODEL_CNF105XXN)\n+\t(ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN)\n \n /* Runtime variants */\n static inline uint64_t\n@@ -105,6 +110,12 @@ roc_model_is_cn96_ax(void)\n \treturn (roc_model->flag & ROC_MODEL_CN96xx_Ax);\n }\n \n+static inline uint64_t\n+roc_model_is_cn96_cx(void)\n+{\n+\treturn (roc_model->flag & ROC_MODEL_CN96xx_C0);\n+}\n+\n static inline uint64_t\n roc_model_is_cn95_a0(void)\n {\n@@ -114,19 +125,37 @@ roc_model_is_cn95_a0(void)\n static inline uint64_t\n roc_model_is_cn10ka(void)\n {\n-\treturn roc_model->flag & ROC_MODEL_CN106XX;\n+\treturn roc_model->flag & ROC_MODEL_CN106xx;\n }\n \n static inline uint64_t\n roc_model_is_cnf10ka(void)\n {\n-\treturn roc_model->flag & ROC_MODEL_CNF105XX;\n+\treturn roc_model->flag & ROC_MODEL_CNF105xx;\n }\n \n static inline uint64_t\n roc_model_is_cnf10kb(void)\n {\n-\treturn roc_model->flag & ROC_MODEL_CNF105XXN;\n+\treturn roc_model->flag & ROC_MODEL_CNF105xxN;\n+}\n+\n+static inline uint64_t\n+roc_model_is_cn10ka_a0(void)\n+{\n+\treturn roc_model->flag & ROC_MODEL_CN106xx_A0;\n+}\n+\n+static inline uint64_t\n+roc_model_is_cnf10ka_a0(void)\n+{\n+\treturn roc_model->flag & ROC_MODEL_CNF105xx_A0;\n+}\n+\n+static inline uint64_t\n+roc_model_is_cnf10kb_a0(void)\n+{\n+\treturn roc_model->flag & ROC_MODEL_CNF105xxN_A0;\n }\n \n int roc_model_init(struct roc_model *model);\n", "prefixes": [ "1/2" ] }