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GET /api/patches/97420/?format=api
{ "id": 97420, "url": "http://patches.dpdk.org/api/patches/97420/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210827065717.1838258-3-andrew.rybchenko@oktetlabs.ru/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210827065717.1838258-3-andrew.rybchenko@oktetlabs.ru>", "list_archive_url": "https://inbox.dpdk.org/dev/20210827065717.1838258-3-andrew.rybchenko@oktetlabs.ru", "date": "2021-08-27T06:56:41", "name": "[02/38] common/sfc_efx/base: update EF100 registers definitions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "990fcfe21de43411d472768ef3b322331c1a77db", "submitter": { "id": 2013, "url": "http://patches.dpdk.org/api/people/2013/?format=api", "name": "Andrew Rybchenko", "email": "Andrew.Rybchenko@oktetlabs.ru" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210827065717.1838258-3-andrew.rybchenko@oktetlabs.ru/mbox/", "series": [ { "id": 18492, "url": "http://patches.dpdk.org/api/series/18492/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18492", "date": "2021-08-27T06:56:39", "name": "net/sfc: support port representors", "version": 1, "mbox": "http://patches.dpdk.org/series/18492/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/97420/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/97420/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 78C61A0C43;\n\tFri, 27 Aug 2021 08:57:55 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 434CA41251;\n\tFri, 27 Aug 2021 08:57:45 +0200 (CEST)", "from shelob.oktetlabs.ru (shelob.oktetlabs.ru [91.220.146.113])\n by mails.dpdk.org (Postfix) with ESMTP id AB3EB41250\n for <dev@dpdk.org>; Fri, 27 Aug 2021 08:57:44 +0200 (CEST)", "by shelob.oktetlabs.ru (Postfix, from userid 122)\n id 755787F6FE; Fri, 27 Aug 2021 09:57:44 +0300 (MSK)", "from aros.oktetlabs.ru (aros.oktetlabs.ru [192.168.38.17])\n by shelob.oktetlabs.ru (Postfix) with ESMTP id E5C707F6CB\n for <dev@dpdk.org>; Fri, 27 Aug 2021 09:57:32 +0300 (MSK)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on shelob.oktetlabs.ru", "X-Spam-Level": "*", "X-Spam-Status": "No, score=1.6 required=5.0 tests=ALL_TRUSTED,\n DKIM_ADSP_DISCARD,\n UPPERCASE_50_75,URIBL_BLOCKED autolearn=no autolearn_force=no\n version=3.4.2", "DKIM-Filter": "OpenDKIM Filter v2.11.0 shelob.oktetlabs.ru E5C707F6CB", "Authentication-Results": "shelob.oktetlabs.ru/E5C707F6CB; dkim=none;\n dkim-atps=neutral", "From": "Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>", "To": "dev@dpdk.org", "Date": "Fri, 27 Aug 2021 09:56:41 +0300", "Message-Id": "<20210827065717.1838258-3-andrew.rybchenko@oktetlabs.ru>", "X-Mailer": "git-send-email 2.30.2", "In-Reply-To": "<20210827065717.1838258-1-andrew.rybchenko@oktetlabs.ru>", "References": "<20210827065717.1838258-1-andrew.rybchenko@oktetlabs.ru>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 02/38] common/sfc_efx/base: update EF100\n registers definitions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Pick up all changes and extra definitions.\n\nSigned-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>\n---\n drivers/common/sfc_efx/base/efx_regs_ef100.h | 106 +++++++++++++++----\n drivers/common/sfc_efx/base/rhead_rx.c | 2 +-\n 2 files changed, 85 insertions(+), 23 deletions(-)", "diff": "diff --git a/drivers/common/sfc_efx/base/efx_regs_ef100.h b/drivers/common/sfc_efx/base/efx_regs_ef100.h\nindex 2b766aabdd..0446377f64 100644\n--- a/drivers/common/sfc_efx/base/efx_regs_ef100.h\n+++ b/drivers/common/sfc_efx/base/efx_regs_ef100.h\n@@ -323,12 +323,6 @@ extern \"C\" {\n /* ES_RHEAD_BASE_EVENT */\n #define\tESF_GZ_E_TYPE_LBN 60\n #define\tESF_GZ_E_TYPE_WIDTH 4\n-#define\tESE_GZ_EF100_EV_DRIVER 5\n-#define\tESE_GZ_EF100_EV_MCDI 4\n-#define\tESE_GZ_EF100_EV_CONTROL 3\n-#define\tESE_GZ_EF100_EV_TX_TIMESTAMP 2\n-#define\tESE_GZ_EF100_EV_TX_COMPLETION 1\n-#define\tESE_GZ_EF100_EV_RX_PKTS 0\n #define\tESF_GZ_EV_EVQ_PHASE_LBN 59\n #define\tESF_GZ_EV_EVQ_PHASE_WIDTH 1\n #define\tESE_GZ_RHEAD_BASE_EVENT_STRUCT_SIZE 64\n@@ -467,6 +461,23 @@ extern \"C\" {\n #define\tESE_GZ_XIL_CFGBAR_VSEC_STRUCT_SIZE 96\n \n \n+/* ES_addr_spc */\n+#define\tESF_GZ_ADDR_SPC_FORMAT_1_FUNCTION_LBN 28\n+#define\tESF_GZ_ADDR_SPC_FORMAT_1_FUNCTION_WIDTH 8\n+#define\tESF_GZ_ADDR_SPC_FORMAT_2_FUNCTION_LBN 24\n+#define\tESF_GZ_ADDR_SPC_FORMAT_2_FUNCTION_WIDTH 12\n+#define\tESF_GZ_ADDR_SPC_FORMAT_1_PROFILE_ID_LBN 24\n+#define\tESF_GZ_ADDR_SPC_FORMAT_1_PROFILE_ID_WIDTH 4\n+#define\tESF_GZ_ADDR_SPC_PASID_LBN 2\n+#define\tESF_GZ_ADDR_SPC_PASID_WIDTH 22\n+#define\tESF_GZ_ADDR_SPC_FORMAT_LBN 0\n+#define\tESF_GZ_ADDR_SPC_FORMAT_WIDTH 2\n+#define\tESE_GZ_ADDR_SPC_FORMAT_1 3\n+#define\tESF_GZ_ADDR_SPC_FORMAT_2_PROFILE_ID_IDX_LBN 0\n+#define\tESF_GZ_ADDR_SPC_FORMAT_2_PROFILE_ID_IDX_WIDTH 2\n+#define\tESE_GZ_ADDR_SPC_STRUCT_SIZE 36\n+\n+\n /* ES_rh_egres_hclass */\n #define\tESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_LBN 15\n #define\tESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_WIDTH 1\n@@ -560,14 +571,18 @@ extern \"C\" {\n #define\tESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_WIDTH 16\n #define\tESF_GZ_RX_PREFIX_CSUM_FRAME_LBN 144\n #define\tESF_GZ_RX_PREFIX_CSUM_FRAME_WIDTH 16\n-#define\tESF_GZ_RX_PREFIX_INGRESS_VPORT_LBN 128\n-#define\tESF_GZ_RX_PREFIX_INGRESS_VPORT_WIDTH 16\n+#define\tESF_GZ_RX_PREFIX_INGRESS_MPORT_LBN 128\n+#define\tESF_GZ_RX_PREFIX_INGRESS_MPORT_WIDTH 16\n #define\tESF_GZ_RX_PREFIX_USER_MARK_LBN 96\n #define\tESF_GZ_RX_PREFIX_USER_MARK_WIDTH 32\n #define\tESF_GZ_RX_PREFIX_RSS_HASH_LBN 64\n #define\tESF_GZ_RX_PREFIX_RSS_HASH_WIDTH 32\n-#define\tESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN 32\n-#define\tESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_WIDTH 32\n+#define\tESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN 34\n+#define\tESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_WIDTH 30\n+#define\tESF_GZ_RX_PREFIX_VSWITCH_STATUS_LBN 33\n+#define\tESF_GZ_RX_PREFIX_VSWITCH_STATUS_WIDTH 1\n+#define\tESF_GZ_RX_PREFIX_VLAN_STRIPPED_LBN 32\n+#define\tESF_GZ_RX_PREFIX_VLAN_STRIPPED_WIDTH 1\n #define\tESF_GZ_RX_PREFIX_CLASS_LBN 16\n #define\tESF_GZ_RX_PREFIX_CLASS_WIDTH 16\n #define\tESF_GZ_RX_PREFIX_USER_FLAG_LBN 15\n@@ -674,12 +689,12 @@ extern \"C\" {\n #define\tESF_GZ_M2M_TRANSLATE_ADDR_WIDTH 1\n #define\tESF_GZ_M2M_RSVD_LBN 120\n #define\tESF_GZ_M2M_RSVD_WIDTH 2\n-#define\tESF_GZ_M2M_ADDR_SPC_LBN 108\n-#define\tESF_GZ_M2M_ADDR_SPC_WIDTH 12\n-#define\tESF_GZ_M2M_ADDR_SPC_PASID_LBN 86\n-#define\tESF_GZ_M2M_ADDR_SPC_PASID_WIDTH 22\n-#define\tESF_GZ_M2M_ADDR_SPC_MODE_LBN 84\n-#define\tESF_GZ_M2M_ADDR_SPC_MODE_WIDTH 2\n+#define\tESF_GZ_M2M_ADDR_SPC_ID_DW0_LBN 84\n+#define\tESF_GZ_M2M_ADDR_SPC_ID_DW0_WIDTH 32\n+#define\tESF_GZ_M2M_ADDR_SPC_ID_DW1_LBN 116\n+#define\tESF_GZ_M2M_ADDR_SPC_ID_DW1_WIDTH 4\n+#define\tESF_GZ_M2M_ADDR_SPC_ID_LBN 84\n+#define\tESF_GZ_M2M_ADDR_SPC_ID_WIDTH 36\n #define\tESF_GZ_M2M_LEN_MINUS_1_LBN 64\n #define\tESF_GZ_M2M_LEN_MINUS_1_WIDTH 20\n #define\tESF_GZ_M2M_ADDR_DW0_LBN 0\n@@ -722,12 +737,12 @@ extern \"C\" {\n #define\tESF_GZ_TX_SEG_TRANSLATE_ADDR_WIDTH 1\n #define\tESF_GZ_TX_SEG_RSVD2_LBN 120\n #define\tESF_GZ_TX_SEG_RSVD2_WIDTH 2\n-#define\tESF_GZ_TX_SEG_ADDR_SPC_LBN 108\n-#define\tESF_GZ_TX_SEG_ADDR_SPC_WIDTH 12\n-#define\tESF_GZ_TX_SEG_ADDR_SPC_PASID_LBN 86\n-#define\tESF_GZ_TX_SEG_ADDR_SPC_PASID_WIDTH 22\n-#define\tESF_GZ_TX_SEG_ADDR_SPC_MODE_LBN 84\n-#define\tESF_GZ_TX_SEG_ADDR_SPC_MODE_WIDTH 2\n+#define\tESF_GZ_TX_SEG_ADDR_SPC_ID_DW0_LBN 84\n+#define\tESF_GZ_TX_SEG_ADDR_SPC_ID_DW0_WIDTH 32\n+#define\tESF_GZ_TX_SEG_ADDR_SPC_ID_DW1_LBN 116\n+#define\tESF_GZ_TX_SEG_ADDR_SPC_ID_DW1_WIDTH 4\n+#define\tESF_GZ_TX_SEG_ADDR_SPC_ID_LBN 84\n+#define\tESF_GZ_TX_SEG_ADDR_SPC_ID_WIDTH 36\n #define\tESF_GZ_TX_SEG_RSVD_LBN 80\n #define\tESF_GZ_TX_SEG_RSVD_WIDTH 4\n #define\tESF_GZ_TX_SEG_LEN_LBN 64\n@@ -824,6 +839,12 @@ extern \"C\" {\n \n \n \n+/* Enum D2VIO_MSG_OP */\n+#define\tESE_GZ_QUE_JBDNE 3\n+#define\tESE_GZ_QUE_EVICT 2\n+#define\tESE_GZ_QUE_EMPTY 1\n+#define\tESE_GZ_NOP 0\n+\n /* Enum DESIGN_PARAMS */\n #define\tESE_EF100_DP_GZ_RX_MAX_RUNT 17\n #define\tESE_EF100_DP_GZ_VI_STRIDES 16\n@@ -871,6 +892,19 @@ extern \"C\" {\n #define\tESE_GZ_PCI_BASE_CONFIG_SPACE_SIZE 256\n #define\tESE_GZ_PCI_EXPRESS_XCAP_HDR_SIZE 4\n \n+/* Enum RH_DSC_TYPE */\n+#define\tESE_GZ_TX_TOMB 0xF\n+#define\tESE_GZ_TX_VIO 0xE\n+#define\tESE_GZ_TX_TSO_OVRRD 0x8\n+#define\tESE_GZ_TX_D2CMP 0x7\n+#define\tESE_GZ_TX_DATA 0x6\n+#define\tESE_GZ_TX_D2M 0x5\n+#define\tESE_GZ_TX_M2M 0x4\n+#define\tESE_GZ_TX_SEG 0x3\n+#define\tESE_GZ_TX_TSO 0x2\n+#define\tESE_GZ_TX_OVRRD 0x1\n+#define\tESE_GZ_TX_SEND 0x0\n+\n /* Enum RH_HCLASS_L2_CLASS */\n #define\tESE_GZ_RH_HCLASS_L2_CLASS_E2_0123VLAN 1\n #define\tESE_GZ_RH_HCLASS_L2_CLASS_OTHER 0\n@@ -907,6 +941,25 @@ extern \"C\" {\n #define\tESE_GZ_RH_HCLASS_TUNNEL_CLASS_VXLAN 1\n #define\tESE_GZ_RH_HCLASS_TUNNEL_CLASS_NONE 0\n \n+/* Enum SF_CTL_EVENT_SUBTYPE */\n+#define\tESE_GZ_EF100_CTL_EV_EVQ_TIMEOUT 0x3\n+#define\tESE_GZ_EF100_CTL_EV_FLUSH 0x2\n+#define\tESE_GZ_EF100_CTL_EV_TIME_SYNC 0x1\n+#define\tESE_GZ_EF100_CTL_EV_UNSOL_OVERFLOW 0x0\n+\n+/* Enum SF_EVENT_TYPE */\n+#define\tESE_GZ_EF100_EV_DRIVER 0x5\n+#define\tESE_GZ_EF100_EV_MCDI 0x4\n+#define\tESE_GZ_EF100_EV_CONTROL 0x3\n+#define\tESE_GZ_EF100_EV_TX_TIMESTAMP 0x2\n+#define\tESE_GZ_EF100_EV_TX_COMPLETION 0x1\n+#define\tESE_GZ_EF100_EV_RX_PKTS 0x0\n+\n+/* Enum SF_EW_EVENT_TYPE */\n+#define\tESE_GZ_EF100_EWEV_VIRTQ_DESC 0x2\n+#define\tESE_GZ_EF100_EWEV_TXQ_DESC 0x1\n+#define\tESE_GZ_EF100_EWEV_64BIT 0x0\n+\n /* Enum TX_DESC_CSO_PARTIAL_EN */\n #define\tESE_GZ_TX_DESC_CSO_PARTIAL_EN_TCP 2\n #define\tESE_GZ_TX_DESC_CSO_PARTIAL_EN_UDP 1\n@@ -922,6 +975,15 @@ extern \"C\" {\n #define\tESE_GZ_TX_DESC_IP4_ID_INC_MOD16 2\n #define\tESE_GZ_TX_DESC_IP4_ID_INC_MOD15 1\n #define\tESE_GZ_TX_DESC_IP4_ID_NO_OP 0\n+\n+/* Enum VIRTIO_NET_HDR_F */\n+#define\tESE_GZ_NEEDS_CSUM 0x1\n+\n+/* Enum VIRTIO_NET_HDR_GSO */\n+#define\tESE_GZ_TCPV6 0x4\n+#define\tESE_GZ_UDP 0x3\n+#define\tESE_GZ_TCPV4 0x1\n+#define\tESE_GZ_NONE 0x0\n /*************************************************************************\n * NOTE: the comment line above marks the end of the autogenerated section\n */\ndiff --git a/drivers/common/sfc_efx/base/rhead_rx.c b/drivers/common/sfc_efx/base/rhead_rx.c\nindex 76b8ce302a..692c3e1d49 100644\n--- a/drivers/common/sfc_efx/base/rhead_rx.c\n+++ b/drivers/common/sfc_efx/base/rhead_rx.c\n@@ -37,7 +37,7 @@ static const efx_rx_prefix_layout_t rhead_default_rx_prefix_layout = {\n \t\tRHEAD_RX_PREFIX_FIELD(PARTIAL_TSTAMP, B_FALSE),\n \t\tRHEAD_RX_PREFIX_FIELD(RSS_HASH, B_FALSE),\n \t\tRHEAD_RX_PREFIX_FIELD(USER_MARK, B_FALSE),\n-\t\tRHEAD_RX_PREFIX_FIELD(INGRESS_VPORT, B_FALSE),\n+\t\tRHEAD_RX_PREFIX_FIELD(INGRESS_MPORT, B_FALSE),\n \t\tRHEAD_RX_PREFIX_FIELD(CSUM_FRAME, B_TRUE),\n \t\tRHEAD_RX_PREFIX_FIELD(VLAN_STRIP_TCI, B_TRUE),\n \n", "prefixes": [ "02/38" ] }