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GET /api/patches/96104/?format=api
{ "id": 96104, "url": "http://patches.dpdk.org/api/patches/96104/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210720130944.5407-11-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210720130944.5407-11-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210720130944.5407-11-suanmingm@nvidia.com", "date": "2021-07-20T13:09:39", "name": "[v9,10/15] crypto/mlx5: add WQE set initialization", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d02c0359dabe51070535f1c15372a99d2d633639", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210720130944.5407-11-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17912, "url": "http://patches.dpdk.org/api/series/17912/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17912", "date": "2021-07-20T13:09:29", "name": "drivers: introduce mlx5 crypto PMD", "version": 9, "mbox": "http://patches.dpdk.org/series/17912/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/96104/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/96104/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 014C4A0C48;\n\tTue, 20 Jul 2021 15:11:26 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B7C774111E;\n\tTue, 20 Jul 2021 15:10:26 +0200 (CEST)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2089.outbound.protection.outlook.com [40.107.94.89])\n by mails.dpdk.org (Postfix) with ESMTP id D9A3B41190\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<shirik@nvidia.com>, <gakhil@marvell.com>", "CC": "<matan@nvidia.com>, <david.marchand@redhat.com>, <dev@dpdk.org>", "Date": "Tue, 20 Jul 2021 16:09:39 +0300", "Message-ID": "<20210720130944.5407-11-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20210720130944.5407-1-suanmingm@nvidia.com>", "References": "<20210408204849.9543-1-shirik@nvidia.com>\n <20210720130944.5407-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "4d7fcf7f-67b0-47ea-df45-08d94b7fbbd9", "X-MS-TrafficTypeDiagnostic": "DM4PR12MB5056:", "X-Microsoft-Antispam-PRVS": "\n <DM4PR12MB5056BB7A1B4829D1C40E3488C1E29@DM4PR12MB5056.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:295;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n yR0EfWu0rBO+oknoZ2tZxApywECxZk/lJ2jBevSMmwyY7/WvSncWiLQsileHDNIfADchDyxfqbiwrO3VI3iXE9xuoWZVxkUlUTH+B2XZRfq9vDiPFf5t4TeJFtkwzKpLypgfsdzqBTjDYfmitSb1z/4eaCTsadtPqUjLEczQVbZKB5kPSTSo6aXM4l/4hGWZVbq7m4bUzQ818xEH2T41BXQjxve4yIbL/yccsR8qgn1dxYl1BXyPcWqSTLz7tcyelhQdN+4I+j8CHL/FU/k7B5cyfKByalP/LKkIMszcyYQd1uBLqRLHgrDpHRrpjW4If0jQmXBLeThCwa2bH/IVnbjzCkXZJVFDj8khPQDeoYwLNGg/IDs0xCJsrEtTft4rLIWneQxAdE8ozEWcTHG6ya9kbeG0j5zJKF5UE83bGfnvjv0NVu3hLlczwm3HvpzLZBiIJAIbhIXo2lgdIc3gHhd1NAycNzH7TuDvHSID7cgpj/x1vmhGN0ywoQ876MkTl+W/tVeaBxZeUQIPHVR8WyLvYsv5aFg1S1xV1XZGtA+CLsdfiqggK6fW0SOnvYR4U3i2JabFbOQfOv7PLjMKlgUJVZ9v7LeVveL9IHqJpyX00LUQ57XudcuZuknHrVT4hXryS0pPzTt8AgDSgx0VOn6J6yVk8LreKp1+vt1rm9bdJo/o2LxFNeKMcOrHM5qE3pbPx/6G0nB3yHqgBtSycQ==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(376002)(136003)(396003)(39860400002)(36840700001)(46966006)(70206006)(70586007)(36756003)(336012)(7696005)(6286002)(5660300002)(82310400003)(55016002)(426003)(36860700001)(4326008)(54906003)(186003)(8936002)(86362001)(2616005)(83380400001)(2906002)(47076005)(16526019)(7636003)(36906005)(1076003)(82740400003)(478600001)(316002)(6666004)(8676002)(26005)(356005)(110136005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Jul 2021 13:10:23.3094 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4d7fcf7f-67b0-47ea-df45-08d94b7fbbd9", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT036.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB5056", "Subject": "[dpdk-dev] [PATCH v9 10/15] crypto/mlx5: add WQE set initialization", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Currently, HW handles the WQEs much faster than the software,\nUsing the constant WQE set layout can initialize most of the WQE\nsegments in advanced, and software only needs to configure very\nlimited segments in datapath. This accelerates the software WQE\norganize in datapath.\n\nThis commit initializes the fixed WQE set segments.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nSigned-off-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 83 +++++++++++++++++++++++++++++--\n drivers/crypto/mlx5/mlx5_crypto.h | 10 +++-\n 2 files changed, 87 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex f7e23d16e9..caad94d2f5 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -295,6 +295,69 @@ mlx5_crypto_qp2rts(struct mlx5_crypto_qp *qp)\n \treturn 0;\n }\n \n+static void\n+mlx5_crypto_qp_init(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp)\n+{\n+\tuint32_t i;\n+\n+\tfor (i = 0 ; i < qp->entries_n; i++) {\n+\t\tstruct mlx5_wqe_cseg *cseg = RTE_PTR_ADD(qp->umem_buf, i *\n+\t\t\t\t\t\t\t priv->wqe_set_size);\n+\t\tstruct mlx5_wqe_umr_cseg *ucseg = (struct mlx5_wqe_umr_cseg *)\n+\t\t\t\t\t\t\t\t (cseg + 1);\n+\t\tstruct mlx5_wqe_umr_bsf_seg *bsf =\n+\t\t\t(struct mlx5_wqe_umr_bsf_seg *)(RTE_PTR_ADD(cseg,\n+\t\t\t\t\t\t priv->umr_wqe_size)) - 1;\n+\t\tstruct mlx5_wqe_rseg *rseg;\n+\n+\t\t/* Init UMR WQE. */\n+\t\tcseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj->id << 8) |\n+\t\t\t\t\t (priv->umr_wqe_size / MLX5_WSEG_SIZE));\n+\t\tcseg->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<\n+\t\t\t\t MLX5_COMP_MODE_OFFSET);\n+\t\tcseg->misc = rte_cpu_to_be_32(qp->mkey[i]->id);\n+\t\tucseg->if_cf_toe_cq_res = RTE_BE32(1u << MLX5_UMRC_IF_OFFSET);\n+\t\tucseg->mkey_mask = RTE_BE64(1u << 0); /* Mkey length bit. */\n+\t\tucseg->ko_to_bs = rte_cpu_to_be_32\n+\t\t\t((RTE_ALIGN(priv->max_segs_num, 4u) <<\n+\t\t\t MLX5_UMRC_KO_OFFSET) | (4 << MLX5_UMRC_TO_BS_OFFSET));\n+\t\tbsf->keytag = priv->keytag;\n+\t\t/* Init RDMA WRITE WQE. */\n+\t\tcseg = RTE_PTR_ADD(cseg, priv->umr_wqe_size);\n+\t\tcseg->flags = RTE_BE32((MLX5_COMP_ALWAYS <<\n+\t\t\t\t MLX5_COMP_MODE_OFFSET) |\n+\t\t\t\t MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE);\n+\t\trseg = (struct mlx5_wqe_rseg *)(cseg + 1);\n+\t\trseg->rkey = rte_cpu_to_be_32(qp->mkey[i]->id);\n+\t}\n+}\n+\n+static int\n+mlx5_crypto_indirect_mkeys_prepare(struct mlx5_crypto_priv *priv,\n+\t\t\t\t struct mlx5_crypto_qp *qp)\n+{\n+\tstruct mlx5_umr_wqe *umr;\n+\tuint32_t i;\n+\tstruct mlx5_devx_mkey_attr attr = {\n+\t\t.pd = priv->pdn,\n+\t\t.umr_en = 1,\n+\t\t.crypto_en = 1,\n+\t\t.set_remote_rw = 1,\n+\t\t.klm_num = RTE_ALIGN(priv->max_segs_num, 4),\n+\t};\n+\n+\tfor (umr = (struct mlx5_umr_wqe *)qp->umem_buf, i = 0;\n+\t i < qp->entries_n; i++, umr = RTE_PTR_ADD(umr, priv->wqe_set_size)) {\n+\t\tattr.klm_array = (struct mlx5_klm *)&umr->kseg[0];\n+\t\tqp->mkey[i] = mlx5_devx_cmd_mkey_create(priv->ctx, &attr);\n+\t\tif (!qp->mkey[i]) {\n+\t\t\tDRV_LOG(ERR, \"Failed to allocate indirect mkey.\");\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n static int\n mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\t\t const struct rte_cryptodev_qp_conf *qp_conf,\n@@ -305,7 +368,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \tstruct mlx5_crypto_qp *qp;\n \tuint16_t log_nb_desc = rte_log2_u32(qp_conf->nb_descriptors);\n \tuint32_t umem_size = RTE_BIT32(log_nb_desc) *\n-\t\t\t MLX5_CRYPTO_WQE_SET_SIZE +\n+\t\t\t priv->wqe_set_size +\n \t\t\t sizeof(*qp->db_rec) * 2;\n \tuint32_t alloc_size = sizeof(*qp);\n \tstruct mlx5_devx_cq_attr cq_attr = {\n@@ -315,7 +378,9 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \tif (dev->data->queue_pairs[qp_id] != NULL)\n \t\tmlx5_crypto_queue_pair_release(dev, qp_id);\n \talloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);\n-\talloc_size += sizeof(struct rte_crypto_op *) * RTE_BIT32(log_nb_desc);\n+\talloc_size += (sizeof(struct rte_crypto_op *) +\n+\t\t sizeof(struct mlx5_devx_obj *)) *\n+\t\t RTE_BIT32(log_nb_desc);\n \tqp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,\n \t\t\t\tsocket_id);\n \tif (qp == NULL) {\n@@ -360,8 +425,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \tattr.wq_umem_id = qp->umem_obj->umem_id;\n \tattr.wq_umem_offset = 0;\n \tattr.dbr_umem_id = qp->umem_obj->umem_id;\n-\tattr.dbr_address = RTE_BIT64(log_nb_desc) *\n-\t\t\t MLX5_CRYPTO_WQE_SET_SIZE;\n+\tattr.dbr_address = RTE_BIT64(log_nb_desc) * priv->wqe_set_size;\n \tqp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr);\n \tif (qp->qp_obj == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to create QP(%u).\", rte_errno);\n@@ -370,8 +434,17 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \tqp->db_rec = RTE_PTR_ADD(qp->umem_buf, (uintptr_t)attr.dbr_address);\n \tif (mlx5_crypto_qp2rts(qp))\n \t\tgoto error;\n-\tqp->ops = (struct rte_crypto_op **)RTE_ALIGN((uintptr_t)(qp + 1),\n+\tqp->mkey = (struct mlx5_devx_obj **)RTE_ALIGN((uintptr_t)(qp + 1),\n \t\t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tqp->ops = (struct rte_crypto_op **)(qp->mkey + RTE_BIT32(log_nb_desc));\n+\tqp->entries_n = 1 << log_nb_desc;\n+\tif (mlx5_crypto_indirect_mkeys_prepare(priv, qp)) {\n+\t\tDRV_LOG(ERR, \"Cannot allocate indirect memory regions.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tmlx5_crypto_qp_init(priv, qp);\n+\tqp->priv = priv;\n \tdev->data->queue_pairs[qp_id] = qp;\n \treturn 0;\n error:\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex c0fa8ad4d4..235a43a72a 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -16,7 +16,6 @@\n \n #define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11)\n #define MLX5_CRYPTO_KEY_LENGTH 80\n-#define MLX5_CRYPTO_WQE_SET_SIZE 1024\n \n struct mlx5_crypto_priv {\n \tTAILQ_ENTRY(mlx5_crypto_priv) next;\n@@ -24,6 +23,7 @@ struct mlx5_crypto_priv {\n \tstruct rte_pci_device *pci_dev;\n \tstruct rte_cryptodev *crypto_dev;\n \tvoid *uar; /* User Access Region. */\n+\tvolatile uint64_t *uar_addr;\n \tuint32_t pdn; /* Protection Domain number. */\n \tuint32_t max_segs_num; /* Maximum supported data segs. */\n \tstruct ibv_pd *pd;\n@@ -39,13 +39,21 @@ struct mlx5_crypto_priv {\n };\n \n struct mlx5_crypto_qp {\n+\tstruct mlx5_crypto_priv *priv;\n \tstruct mlx5_devx_cq cq_obj;\n \tstruct mlx5_devx_obj *qp_obj;\n+\tstruct rte_cryptodev_stats stats;\n \tstruct mlx5dv_devx_umem *umem_obj;\n \tvoid *umem_buf;\n \tvolatile uint32_t *db_rec;\n \tstruct rte_crypto_op **ops;\n+\tstruct mlx5_devx_obj **mkey; /* WQE's indirect mekys. */\n \tstruct mlx5_mr_ctrl mr_ctrl;\n+\tuint8_t *wqe;\n+\tuint16_t entries_n;\n+\tuint16_t pi;\n+\tuint16_t ci;\n+\tuint16_t db_pi;\n };\n \n struct mlx5_crypto_dek {\n", "prefixes": [ "v9", "10/15" ] }