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GET /api/patches/96099/?format=api
{ "id": 96099, "url": "http://patches.dpdk.org/api/patches/96099/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210720130944.5407-6-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210720130944.5407-6-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210720130944.5407-6-suanmingm@nvidia.com", "date": "2021-07-20T13:09:34", "name": "[v9,05/15] crypto/mlx5: add session operations", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "afab632d6f9a3ea0da492d1c6bd4e6706b8853ca", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210720130944.5407-6-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17912, "url": "http://patches.dpdk.org/api/series/17912/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17912", "date": "2021-07-20T13:09:29", "name": "drivers: introduce mlx5 crypto PMD", "version": 9, "mbox": "http://patches.dpdk.org/series/17912/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/96099/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/96099/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 82F8EA0C48;\n\tTue, 20 Jul 2021 15:10:49 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7875B4113D;\n\tTue, 20 Jul 2021 15:10:18 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2077.outbound.protection.outlook.com [40.107.236.77])\n by mails.dpdk.org (Postfix) with ESMTP id D8A2941123\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<shirik@nvidia.com>, <gakhil@marvell.com>", "CC": "<matan@nvidia.com>, <david.marchand@redhat.com>, <dev@dpdk.org>", "Date": "Tue, 20 Jul 2021 16:09:34 +0300", "Message-ID": "<20210720130944.5407-6-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20210720130944.5407-1-suanmingm@nvidia.com>", "References": "<20210408204849.9543-1-shirik@nvidia.com>\n <20210720130944.5407-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "919b5fea-bdff-4f6b-bf3e-08d94b7fb6d4", "X-MS-TrafficTypeDiagnostic": "BL0PR12MB4756:", "X-Microsoft-Antispam-PRVS": "\n <BL0PR12MB47562EA9E15A7CA7C786B231C1E29@BL0PR12MB4756.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:8273;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n rBbhl0KrGH4/oiNVAfPHgUt4MNYA8e7Z5hngwWs7DbXorbQIik0xSc4JW4+dC/M5g/5PnWm2vWyQyThhd73N/tqD6ZCWquKuSmHv4ZOS8rSOt3RzvMbOJq7QfU8s+FtFn3wJW2PWz6W84/Nk8MaqAbUQJ6E+QRpx9naerTAxjAm/g24VIp05AV8hJvd6hbk27F+oL0mSFS9tRTgM8z+3ho9UH+PySzmcxy6+5RzeQELf0pxrmBoquj7Jz4fvUOOiLIewTdfxmzAbKADBGHbZ7XwmqxVtJhHT/xbvzXFyyr/ZCEaUX8WutCQuHafBNUJRZz7vfRNKjNnMCP4XBSQMfiyjCRQjSgE0rZ/dnRejiGLNw1YCdn1hNDJe2ULVCdSh1K5owruqA+E0CVg+AXubQtaBSx+bjhwsvEHs7K3Jn/MbMaymow7mLFypTzak2p1KDYhvH+Ms+up1kSAwjdo0f1uDprPe0S1unZwVMd3tbBWP7TWrMEGfUs5KozCLjCDqiNwuF9YwoFWsPK4jVhl+1dTUTil9FhsGo8OXipMHfR+J4u9Q0go3hpHKVzBG4+jsg3f8Fu3mHPEsPodUh4h2IVDXVLoD3k3Q46bcudzwTz00gXMeXy0LZ0ysMbI2Hp118H4Mj+RKE/y7jAhgm6avwx+a5M/GXsPhNiAviaiJrQH1lOyn0Z8U+kmYUHh/kN9MCbWBeTDy6MpVAh3noNk8aA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(376002)(396003)(39860400002)(136003)(46966006)(36840700001)(426003)(5660300002)(26005)(336012)(16526019)(2616005)(356005)(55016002)(1076003)(82310400003)(186003)(36906005)(316002)(2906002)(7696005)(110136005)(54906003)(36756003)(4326008)(70586007)(6666004)(478600001)(82740400003)(83380400001)(47076005)(86362001)(6286002)(36860700001)(7636003)(8676002)(8936002)(70206006);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Jul 2021 13:10:14.9002 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 919b5fea-bdff-4f6b-bf3e-08d94b7fb6d4", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT036.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL0PR12MB4756", "Subject": "[dpdk-dev] [PATCH v9 05/15] crypto/mlx5: add session operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shiri Kuzin <shirik@nvidia.com>\n\nSessions are used in symmetric transformations in order to prepare\nobjects and data for packet processing stage.\n\nA mlx5 session includes iv_offset, pointer to mlx5_crypto_dek struct,\nbsf_size, bsf_p_type, block size index, encryption_order and encryption\nstandard.\n\nImplement the next session operations:\n mlx5_crypto_sym_session_get_size- returns the size of the mlx5\n\tsession struct.\n\tmlx5_crypto_sym_session_configure- prepares the DEK hash-list\n\tand saves all the session data.\n\tmlx5_crypto_sym_session_clear - destroys the DEK hash-list.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n doc/guides/cryptodevs/features/mlx5.ini | 5 +\n doc/guides/cryptodevs/mlx5.rst | 10 ++\n drivers/crypto/mlx5/mlx5_crypto.c | 122 +++++++++++++++++++++++-\n 3 files changed, 133 insertions(+), 4 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/features/mlx5.ini b/doc/guides/cryptodevs/features/mlx5.ini\nindex ceadd967b6..bd757b5211 100644\n--- a/doc/guides/cryptodevs/features/mlx5.ini\n+++ b/doc/guides/cryptodevs/features/mlx5.ini\n@@ -4,12 +4,17 @@\n ; Refer to default.ini for the full list of available PMD features.\n ;\n [Features]\n+Symmetric crypto = Y\n HW Accelerated = Y\n+Cipher multiple data units = Y\n+Cipher wrapped key = Y\n \n ;\n ; Supported crypto algorithms of a mlx5 crypto driver.\n ;\n [Cipher]\n+AES XTS (128) = Y\n+AES XTS (256) = Y\n \n ;\n ; Supported authentication algorithms of a mlx5 crypto driver.\ndiff --git a/doc/guides/cryptodevs/mlx5.rst b/doc/guides/cryptodevs/mlx5.rst\nindex 05a0a449e2..ecab385c0d 100644\n--- a/doc/guides/cryptodevs/mlx5.rst\n+++ b/doc/guides/cryptodevs/mlx5.rst\n@@ -53,6 +53,16 @@ Supported NICs\n \n * Mellanox\\ |reg| ConnectX\\ |reg|-6 200G MCX654106A-HCAT (2x200G)\n \n+\n+Limitations\n+-----------\n+\n+- AES-XTS keys provided in xform must include keytag and should be wrapped.\n+- The supported data-unit lengths are 512B and 1KB. In case the `dataunit_len`\n+ is not provided in the cipher xform, the OP length is limited to the above\n+ values and 1MB.\n+\n+\n Prerequisites\n -------------\n \ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex ad1d7b65aa..2fe2e8b871 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -3,6 +3,7 @@\n */\n \n #include <rte_malloc.h>\n+#include <rte_mempool.h>\n #include <rte_errno.h>\n #include <rte_log.h>\n #include <rte_pci.h>\n@@ -22,7 +23,9 @@\n #define MLX5_CRYPTO_MAX_QPS 1024\n \n #define MLX5_CRYPTO_FEATURE_FLAGS \\\n-\tRTE_CRYPTODEV_FF_HW_ACCELERATED\n+\t(RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | \\\n+\t RTE_CRYPTODEV_FF_CIPHER_WRAPPED_KEY | \\\n+\t RTE_CRYPTODEV_FF_CIPHER_MULTIPLE_DATA_UNITS)\n \n TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list =\n \t\t\t\tTAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list);\n@@ -67,6 +70,21 @@ static const struct rte_driver mlx5_drv = {\n \n static struct cryptodev_driver mlx5_cryptodev_driver;\n \n+struct mlx5_crypto_session {\n+\tuint32_t bs_bpt_eo_es;\n+\t/**< bsf_size, bsf_p_type, encryption_order and encryption standard,\n+\t * saved in big endian format.\n+\t */\n+\tuint32_t bsp_res;\n+\t/**< crypto_block_size_pointer and reserved 24 bits saved in big\n+\t * endian format.\n+\t */\n+\tuint32_t iv_offset:16;\n+\t/**< Starting point for Initialisation Vector. */\n+\tstruct mlx5_crypto_dek *dek; /**< Pointer to dek struct. */\n+\tuint32_t dek_id; /**< DEK ID */\n+} __rte_packed;\n+\n static void\n mlx5_crypto_dev_infos_get(struct rte_cryptodev *dev,\n \t\t\t struct rte_cryptodev_info *dev_info)\n@@ -134,6 +152,102 @@ mlx5_crypto_dev_close(struct rte_cryptodev *dev)\n \treturn 0;\n }\n \n+static unsigned int\n+mlx5_crypto_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)\n+{\n+\treturn sizeof(struct mlx5_crypto_session);\n+}\n+\n+static int\n+mlx5_crypto_sym_session_configure(struct rte_cryptodev *dev,\n+\t\t\t\t struct rte_crypto_sym_xform *xform,\n+\t\t\t\t struct rte_cryptodev_sym_session *session,\n+\t\t\t\t struct rte_mempool *mp)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_crypto_session *sess_private_data;\n+\tstruct rte_crypto_cipher_xform *cipher;\n+\tuint8_t encryption_order;\n+\tint ret;\n+\n+\tif (unlikely(xform->next != NULL)) {\n+\t\tDRV_LOG(ERR, \"Xform next is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tif (unlikely((xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER) ||\n+\t\t (xform->cipher.algo != RTE_CRYPTO_CIPHER_AES_XTS))) {\n+\t\tDRV_LOG(ERR, \"Only AES-XTS algorithm is supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tret = rte_mempool_get(mp, (void *)&sess_private_data);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"Failed to get session %p private data from mempool.\",\n+\t\t\tsess_private_data);\n+\t\treturn -ENOMEM;\n+\t}\n+\tcipher = &xform->cipher;\n+\tsess_private_data->dek = mlx5_crypto_dek_prepare(priv, cipher);\n+\tif (sess_private_data->dek == NULL) {\n+\t\trte_mempool_put(mp, sess_private_data);\n+\t\tDRV_LOG(ERR, \"Failed to prepare dek.\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tif (cipher->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)\n+\t\tencryption_order = MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY;\n+\telse\n+\t\tencryption_order = MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE;\n+\tsess_private_data->bs_bpt_eo_es = rte_cpu_to_be_32\n+\t\t\t(MLX5_BSF_SIZE_64B << MLX5_BSF_SIZE_OFFSET |\n+\t\t\t MLX5_BSF_P_TYPE_CRYPTO << MLX5_BSF_P_TYPE_OFFSET |\n+\t\t\t encryption_order << MLX5_ENCRYPTION_ORDER_OFFSET |\n+\t\t\t MLX5_ENCRYPTION_STANDARD_AES_XTS);\n+\tswitch (xform->cipher.dataunit_len) {\n+\tcase 0:\n+\t\tsess_private_data->bsp_res = 0;\n+\t\tbreak;\n+\tcase 512:\n+\t\tsess_private_data->bsp_res = rte_cpu_to_be_32\n+\t\t\t\t\t ((uint32_t)MLX5_BLOCK_SIZE_512B <<\n+\t\t\t\t\t MLX5_BLOCK_SIZE_OFFSET);\n+\t\tbreak;\n+\tcase 4096:\n+\t\tsess_private_data->bsp_res = rte_cpu_to_be_32\n+\t\t\t\t\t ((uint32_t)MLX5_BLOCK_SIZE_4096B <<\n+\t\t\t\t\t MLX5_BLOCK_SIZE_OFFSET);\n+\t\tbreak;\n+\tdefault:\n+\t\tDRV_LOG(ERR, \"Cipher data unit length is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tsess_private_data->iv_offset = cipher->iv.offset;\n+\tsess_private_data->dek_id =\n+\t\t\trte_cpu_to_be_32(sess_private_data->dek->obj->id &\n+\t\t\t\t\t 0xffffff);\n+\tset_sym_session_private_data(session, dev->driver_id,\n+\t\t\t\t sess_private_data);\n+\tDRV_LOG(DEBUG, \"Session %p was configured.\", sess_private_data);\n+\treturn 0;\n+}\n+\n+static void\n+mlx5_crypto_sym_session_clear(struct rte_cryptodev *dev,\n+\t\t\t struct rte_cryptodev_sym_session *sess)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_crypto_session *spriv = get_sym_session_private_data(sess,\n+\t\t\t\t\t\t\t\tdev->driver_id);\n+\n+\tif (unlikely(spriv == NULL)) {\n+\t\tDRV_LOG(ERR, \"Failed to get session %p private data.\", spriv);\n+\t\treturn;\n+\t}\n+\tmlx5_crypto_dek_destroy(priv, spriv->dek);\n+\tset_sym_session_private_data(sess, dev->driver_id, NULL);\n+\trte_mempool_put(rte_mempool_from_obj(spriv), spriv);\n+\tDRV_LOG(DEBUG, \"Session %p was cleared.\", spriv);\n+}\n+\n static int\n mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)\n {\n@@ -265,9 +379,9 @@ static struct rte_cryptodev_ops mlx5_crypto_ops = {\n \t.stats_reset\t\t\t= NULL,\n \t.queue_pair_setup\t\t= mlx5_crypto_queue_pair_setup,\n \t.queue_pair_release\t\t= mlx5_crypto_queue_pair_release,\n-\t.sym_session_get_size\t\t= NULL,\n-\t.sym_session_configure\t\t= NULL,\n-\t.sym_session_clear\t\t= NULL,\n+\t.sym_session_get_size\t\t= mlx5_crypto_sym_session_get_size,\n+\t.sym_session_configure\t\t= mlx5_crypto_sym_session_configure,\n+\t.sym_session_clear\t\t= mlx5_crypto_sym_session_clear,\n \t.sym_get_raw_dp_ctx_size\t= NULL,\n \t.sym_configure_raw_dp_ctx\t= NULL,\n };\n", "prefixes": [ "v9", "05/15" ] }