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GET /api/patches/95911/?format=api
{ "id": 95911, "url": "http://patches.dpdk.org/api/patches/95911/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210715164126.54073-6-shirik@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210715164126.54073-6-shirik@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210715164126.54073-6-shirik@nvidia.com", "date": "2021-07-15T16:41:15", "name": "[v8,05/16] crypto/mlx5: add queue pairs operations", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "6e32d26f3c38e319885de4f6fbc138a7014dc56f", "submitter": { "id": 1894, "url": "http://patches.dpdk.org/api/people/1894/?format=api", "name": "Shiri Kuzin", "email": "shirik@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210715164126.54073-6-shirik@nvidia.com/mbox/", "series": [ { "id": 17843, "url": "http://patches.dpdk.org/api/series/17843/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17843", "date": "2021-07-15T16:41:10", "name": "drivers: introduce mlx5 crypto PMD", "version": 8, "mbox": "http://patches.dpdk.org/series/17843/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/95911/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/95911/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", 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header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Shiri Kuzin <shirik@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>,\n <david.marchand@redhat.com>", "Date": "Thu, 15 Jul 2021 19:41:15 +0300", "Message-ID": "<20210715164126.54073-6-shirik@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210715164126.54073-1-shirik@nvidia.com>", "References": "<20210715150817.51485-1-shirik@nvidia.com>\n <20210715164126.54073-1-shirik@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL105.nvidia.com (172.20.187.12) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": 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D1/49Xn4EHrPfURjhSv6eIRW2zct/gjuN+LeYZOjNOfabA4JcBuwlXEFXGkJcsY2jCjXlbAWA44L6zK04GX5eNN0lLzYnuLMxMUatHhDqHbPkXr//hrs3OMC+hjAVCDjD+mL8lGGmzF50Ic+mkp/HP6b0TKFe1i9ruv5IdT91flwDIl7AhhVrZQZXcyv1hmm2kRauqtIZG0ztVPs6mc+BVBqrfiE3AVfMLjLEU2POY3kVE4vpAMT82OZXV8AOCbmxFEn6g/p+Spf50RzLPZhprV7jDFkrQQE1NH5fZCGJPFhJ5GXB/79vD6oVvDibOUQFa5o8A8I4s43d/SE9XaC/p1Ia4DX+Zgj9v51JTkhcVnKqizCbO9kFLZBgnHmuFLpPH0oj1eU/KiOUT5TEHMyaR/U1yL0o11nP311AXSV8qaypG5/K2276vsETSUnLCuIQQv7MuXsH/obxEbGlyLldWFU77PjcHRVky2tH5ksiNtQZGw2KTNl11b5sIytnvKV/8c2AQsi49GkjFy0xYANenetBbtYIxQQTJ27NQtqEXtT3fj7D8bFgdyTXf7MDBkxApYxgyjGmNA9W2oBt7OkJPnsTZfLzHbCqbcVjzuCW+Xm45w6hqAcZM2oyHxIXgTEYdeDHHW2kESATfBL95qdYzuZt7mHxm18iIXdelz8rQ9K1Ew0tnFYQNqQvtt0A3vOajj6mJuV7eJSM2sd3qgNkH8/PWIGkPu37U9XQg87Ri8=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(39860400002)(346002)(136003)(396003)(376002)(36840700001)(46966006)(82310400003)(55016002)(8676002)(36860700001)(70586007)(8936002)(47076005)(316002)(4326008)(5660300002)(426003)(82740400003)(336012)(36906005)(86362001)(356005)(34020700004)(2616005)(54906003)(6916009)(186003)(2906002)(7636003)(83380400001)(478600001)(16526019)(36756003)(6286002)(26005)(6666004)(7696005)(70206006)(1076003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Jul 2021 16:42:09.6940 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n aac4000f-14d7-42a5-6a59-08d947af7d5f", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT066.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR1201MB0169", "Subject": "[dpdk-dev] [PATCH v8 05/16] crypto/mlx5: add queue pairs operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The HW queue pairs are a pair of send queue and receive queue of\nindependent work queues packed together in one object for the purpose\nof transferring data between nodes of a network.\n\nCompletion Queue is a FIFO queue of completed work requests.\n\nIn crypto driver we use one QP in loopback in order to encrypt and\ndecrypt data locally without sending it to the wire.\nIn the configured QP we only use the SQ to perform the encryption and\ndecryption operations.\n\nAdded implementation for the QP setup function which creates the CQ,\ncreates the QP and changes its state to RTS (ready to send).\n\nAdded implementation for the release QP function to release all the QP\nresources.\n\nAdded the ops structure that contains any operation which is supported\nby the cryptodev.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 129 +++++++++++++++++++++++++++++-\n drivers/crypto/mlx5/mlx5_crypto.h | 11 +++\n 2 files changed, 137 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex a7e44deb9e..ebaa65c7a9 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -7,6 +7,7 @@\n #include <rte_errno.h>\n #include <rte_log.h>\n #include <rte_pci.h>\n+#include <rte_memory.h>\n \n #include <mlx5_glue.h>\n #include <mlx5_common.h>\n@@ -19,6 +20,7 @@\n \n #define MLX5_CRYPTO_DRIVER_NAME mlx5_crypto\n #define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5\n+#define MLX5_CRYPTO_MAX_QPS 1024\n \n #define MLX5_CRYPTO_FEATURE_FLAGS \\\n \t(RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | \\\n@@ -94,7 +96,7 @@ mlx5_crypto_dev_infos_get(struct rte_cryptodev *dev,\n \t\tdev_info->driver_id = mlx5_crypto_driver_id;\n \t\tdev_info->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS;\n \t\tdev_info->capabilities = mlx5_crypto_caps;\n-\t\tdev_info->max_nb_queue_pairs = 0;\n+\t\tdev_info->max_nb_queue_pairs = MLX5_CRYPTO_MAX_QPS;\n \t\tdev_info->min_mbuf_headroom_req = 0;\n \t\tdev_info->min_mbuf_tailroom_req = 0;\n \t\tdev_info->sym.max_nb_sessions = 0;\n@@ -235,6 +237,127 @@ mlx5_crypto_sym_session_clear(struct rte_cryptodev *dev,\n \tDRV_LOG(DEBUG, \"Session %p was cleared.\", spriv);\n }\n \n+static int\n+mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)\n+{\n+\tstruct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id];\n+\n+\tif (qp->qp_obj != NULL)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(qp->qp_obj));\n+\tif (qp->umem_obj != NULL)\n+\t\tclaim_zero(mlx5_glue->devx_umem_dereg(qp->umem_obj));\n+\tif (qp->umem_buf != NULL)\n+\t\trte_free(qp->umem_buf);\n+\tmlx5_devx_cq_destroy(&qp->cq_obj);\n+\trte_free(qp);\n+\tdev->data->queue_pairs[qp_id] = NULL;\n+\treturn 0;\n+}\n+\n+static int\n+mlx5_crypto_qp2rts(struct mlx5_crypto_qp *qp)\n+{\n+\t/*\n+\t * In Order to configure self loopback, when calling these functions the\n+\t * remote QP id that is used is the id of the same QP.\n+\t */\n+\tif (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_RST2INIT_QP,\n+\t\t\t\t\t qp->qp_obj->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify QP to INIT state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\tif (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_INIT2RTR_QP,\n+\t\t\t\t\t qp->qp_obj->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify QP to RTR state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\tif (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_RTR2RTS_QP,\n+\t\t\t\t\t qp->qp_obj->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify QP to RTS state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n+\t\t\t const struct rte_cryptodev_qp_conf *qp_conf,\n+\t\t\t int socket_id)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_devx_qp_attr attr = {0};\n+\tstruct mlx5_crypto_qp *qp;\n+\tuint16_t log_nb_desc = rte_log2_u32(qp_conf->nb_descriptors);\n+\tuint32_t umem_size = RTE_BIT32(log_nb_desc) *\n+\t\t\t MLX5_CRYPTO_WQE_SET_SIZE +\n+\t\t\t sizeof(*qp->db_rec) * 2;\n+\tuint32_t alloc_size = sizeof(*qp);\n+\tstruct mlx5_devx_cq_attr cq_attr = {\n+\t\t.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),\n+\t};\n+\n+\tif (dev->data->queue_pairs[qp_id] != NULL)\n+\t\tmlx5_crypto_queue_pair_release(dev, qp_id);\n+\talloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);\n+\talloc_size += sizeof(struct rte_crypto_op *) * RTE_BIT32(log_nb_desc);\n+\tqp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,\n+\t\t\t\tsocket_id);\n+\tif (qp == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate QP memory.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\tif (mlx5_devx_cq_create(priv->ctx, &qp->cq_obj, log_nb_desc,\n+\t\t\t\t&cq_attr, socket_id) != 0) {\n+\t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n+\t\tgoto error;\n+\t}\n+\tqp->umem_buf = rte_zmalloc_socket(__func__, umem_size, 4096, socket_id);\n+\tif (qp->umem_buf == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate QP umem.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,\n+\t\t\t\t\t (void *)(uintptr_t)qp->umem_buf,\n+\t\t\t\t\t umem_size,\n+\t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n+\tif (qp->umem_obj == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to register QP umem.\");\n+\t\tgoto error;\n+\t}\n+\tattr.pd = priv->pdn;\n+\tattr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar);\n+\tattr.cqn = qp->cq_obj.cq->id;\n+\tattr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));\n+\tattr.rq_size = 0;\n+\tattr.sq_size = RTE_BIT32(log_nb_desc);\n+\tattr.dbr_umem_valid = 1;\n+\tattr.wq_umem_id = qp->umem_obj->umem_id;\n+\tattr.wq_umem_offset = 0;\n+\tattr.dbr_umem_id = qp->umem_obj->umem_id;\n+\tattr.dbr_address = RTE_BIT64(log_nb_desc) *\n+\t\t\t MLX5_CRYPTO_WQE_SET_SIZE;\n+\tqp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr);\n+\tif (qp->qp_obj == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to create QP(%u).\", rte_errno);\n+\t\tgoto error;\n+\t}\n+\tqp->db_rec = RTE_PTR_ADD(qp->umem_buf, (uintptr_t)attr.dbr_address);\n+\tif (mlx5_crypto_qp2rts(qp))\n+\t\tgoto error;\n+\tqp->ops = (struct rte_crypto_op **)RTE_ALIGN((uintptr_t)(qp + 1),\n+\t\t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tdev->data->queue_pairs[qp_id] = qp;\n+\treturn 0;\n+error:\n+\tmlx5_crypto_queue_pair_release(dev, qp_id);\n+\treturn -1;\n+}\n+\n static struct rte_cryptodev_ops mlx5_crypto_ops = {\n \t.dev_configure\t\t\t= mlx5_crypto_dev_configure,\n \t.dev_start\t\t\t= NULL,\n@@ -243,8 +366,8 @@ static struct rte_cryptodev_ops mlx5_crypto_ops = {\n \t.dev_infos_get\t\t\t= mlx5_crypto_dev_infos_get,\n \t.stats_get\t\t\t= NULL,\n \t.stats_reset\t\t\t= NULL,\n-\t.queue_pair_setup\t\t= NULL,\n-\t.queue_pair_release\t\t= NULL,\n+\t.queue_pair_setup\t\t= mlx5_crypto_queue_pair_setup,\n+\t.queue_pair_release\t\t= mlx5_crypto_queue_pair_release,\n \t.sym_session_get_size\t\t= mlx5_crypto_sym_session_get_size,\n \t.sym_session_configure\t\t= mlx5_crypto_sym_session_configure,\n \t.sym_session_clear\t\t= mlx5_crypto_sym_session_clear,\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex a0df775407..1c3c4855ec 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -11,9 +11,11 @@\n #include <rte_cryptodev_pmd.h>\n \n #include <mlx5_common_utils.h>\n+#include <mlx5_common_devx.h>\n \n #define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11)\n #define MLX5_CRYPTO_KEY_LENGTH 80\n+#define MLX5_CRYPTO_WQE_SET_SIZE 1024\n \n struct mlx5_crypto_priv {\n \tTAILQ_ENTRY(mlx5_crypto_priv) next;\n@@ -27,6 +29,15 @@ struct mlx5_crypto_priv {\n \tstruct rte_cryptodev_config dev_config;\n };\n \n+struct mlx5_crypto_qp {\n+\tstruct mlx5_devx_cq cq_obj;\n+\tstruct mlx5_devx_obj *qp_obj;\n+\tstruct mlx5dv_devx_umem *umem_obj;\n+\tvoid *umem_buf;\n+\tvolatile uint32_t *db_rec;\n+\tstruct rte_crypto_op **ops;\n+};\n+\n struct mlx5_crypto_dek {\n \tstruct mlx5_list_entry entry; /* Pointer to DEK hash list entry. */\n \tstruct mlx5_devx_obj *obj; /* Pointer to DEK DevX object. */\n", "prefixes": [ "v8", "05/16" ] }