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GET /api/patches/95668/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 95668,
    "url": "http://patches.dpdk.org/api/patches/95668/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210712014654.32428-12-suanmingm@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210712014654.32428-12-suanmingm@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210712014654.32428-12-suanmingm@nvidia.com",
    "date": "2021-07-12T01:46:39",
    "name": "[v5,11/26] net/mlx5: relax the list utility atomic operations",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "dbf1037688c37fdc5b69994a2787c399307446ca",
    "submitter": {
        "id": 1887,
        "url": "http://patches.dpdk.org/api/people/1887/?format=api",
        "name": "Suanming Mou",
        "email": "suanmingm@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "http://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210712014654.32428-12-suanmingm@nvidia.com/mbox/",
    "series": [
        {
            "id": 17759,
            "url": "http://patches.dpdk.org/api/series/17759/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17759",
            "date": "2021-07-12T01:46:29",
            "name": "net/mlx5: insertion rate optimization",
            "version": 5,
            "mbox": "http://patches.dpdk.org/series/17759/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/95668/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/95668/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Suanming Mou <suanmingm@nvidia.com>",
        "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>",
        "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>",
        "Date": "Mon, 12 Jul 2021 04:46:39 +0300",
        "Message-ID": "<20210712014654.32428-12-suanmingm@nvidia.com>",
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        "References": "<20210527093403.1153127-1-suanmingm@nvidia.com>\n <20210712014654.32428-1-suanmingm@nvidia.com>",
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        "Subject": "[dpdk-dev] [PATCH v5 11/26] net/mlx5: relax the list utility atomic\n operations",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Matan Azrad <matan@nvidia.com>\n\nThe atomic operation in the list utility no need a barriers because the\ncritical part are managed by RW lock.\n\nRelax them.\n\nSigned-off-by: Matan Azrad <matan@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5_utils.c | 12 ++++++------\n 1 file changed, 6 insertions(+), 6 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5_utils.c b/drivers/net/mlx5/mlx5_utils.c\nindex 13c7dbe1c2..daecf37575 100644\n--- a/drivers/net/mlx5/mlx5_utils.c\n+++ b/drivers/net/mlx5/mlx5_utils.c\n@@ -50,13 +50,13 @@ __list_lookup(struct mlx5_list *list, int lcore_index, void *ctx, bool reuse)\n \t\tif (list->cb_match(list, entry, ctx) == 0) {\n \t\t\tif (reuse) {\n \t\t\t\tret = __atomic_add_fetch(&entry->ref_cnt, 1,\n-\t\t\t\t\t\t\t __ATOMIC_ACQUIRE) - 1;\n+\t\t\t\t\t\t\t __ATOMIC_RELAXED) - 1;\n \t\t\t\tDRV_LOG(DEBUG, \"mlx5 list %s entry %p ref: %u.\",\n \t\t\t\t\tlist->name, (void *)entry,\n \t\t\t\t\tentry->ref_cnt);\n \t\t\t} else if (lcore_index < RTE_MAX_LCORE) {\n \t\t\t\tret = __atomic_load_n(&entry->ref_cnt,\n-\t\t\t\t\t\t      __ATOMIC_ACQUIRE);\n+\t\t\t\t\t\t      __ATOMIC_RELAXED);\n \t\t\t}\n \t\t\tif (likely(ret != 0 || lcore_index == RTE_MAX_LCORE))\n \t\t\t\treturn entry;\n@@ -181,7 +181,7 @@ mlx5_list_register(struct mlx5_list *list, void *ctx)\n \tlist->gen_cnt++;\n \trte_rwlock_write_unlock(&list->lock);\n \tLIST_INSERT_HEAD(&list->cache[lcore_index].h, local_entry, next);\n-\t__atomic_add_fetch(&list->count, 1, __ATOMIC_ACQUIRE);\n+\t__atomic_add_fetch(&list->count, 1, __ATOMIC_RELAXED);\n \tDRV_LOG(DEBUG, \"mlx5 list %s entry %p new: %u.\", list->name,\n \t\t(void *)entry, entry->ref_cnt);\n \treturn local_entry;\n@@ -194,7 +194,7 @@ mlx5_list_unregister(struct mlx5_list *list,\n \tstruct mlx5_list_entry *gentry = entry->gentry;\n \tint lcore_idx;\n \n-\tif (__atomic_sub_fetch(&entry->ref_cnt, 1, __ATOMIC_ACQUIRE) != 0)\n+\tif (__atomic_sub_fetch(&entry->ref_cnt, 1, __ATOMIC_RELAXED) != 0)\n \t\treturn 1;\n \tlcore_idx = rte_lcore_index(rte_lcore_id());\n \tMLX5_ASSERT(lcore_idx < RTE_MAX_LCORE);\n@@ -207,14 +207,14 @@ mlx5_list_unregister(struct mlx5_list *list,\n \t} else {\n \t\treturn 0;\n \t}\n-\tif (__atomic_sub_fetch(&gentry->ref_cnt, 1, __ATOMIC_ACQUIRE) != 0)\n+\tif (__atomic_sub_fetch(&gentry->ref_cnt, 1, __ATOMIC_RELAXED) != 0)\n \t\treturn 1;\n \trte_rwlock_write_lock(&list->lock);\n \tif (likely(gentry->ref_cnt == 0)) {\n \t\tLIST_REMOVE(gentry, next);\n \t\trte_rwlock_write_unlock(&list->lock);\n \t\tlist->cb_remove(list, gentry);\n-\t\t__atomic_sub_fetch(&list->count, 1, __ATOMIC_ACQUIRE);\n+\t\t__atomic_sub_fetch(&list->count, 1, __ATOMIC_RELAXED);\n \t\tDRV_LOG(DEBUG, \"mlx5 list %s entry %p removed.\",\n \t\t\tlist->name, (void *)gentry);\n \t\treturn 0;\n",
    "prefixes": [
        "v5",
        "11/26"
    ]
}