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GET /api/patches/95663/?format=api
{ "id": 95663, "url": "http://patches.dpdk.org/api/patches/95663/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210712014654.32428-7-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210712014654.32428-7-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210712014654.32428-7-suanmingm@nvidia.com", "date": "2021-07-12T01:46:34", "name": "[v5,06/26] net/mlx5: optimize modify header action memory", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "7a38ba8aa91f5e1d91811184a09cbdecb73785c0", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210712014654.32428-7-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17759, "url": "http://patches.dpdk.org/api/series/17759/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17759", "date": "2021-07-12T01:46:29", "name": "net/mlx5: insertion rate optimization", "version": 5, "mbox": "http://patches.dpdk.org/series/17759/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/95663/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/95663/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 95D59A0C4B;\n\tMon, 12 Jul 2021 03:48:11 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C6CFF41177;\n\tMon, 12 Jul 2021 03:47:42 +0200 (CEST)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2083.outbound.protection.outlook.com [40.107.237.83])\n by mails.dpdk.org (Postfix) with ESMTP id 0B1C240E50\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Date": "Mon, 12 Jul 2021 04:46:34 +0300", "Message-ID": "<20210712014654.32428-7-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20210712014654.32428-1-suanmingm@nvidia.com>", "References": "<20210527093403.1153127-1-suanmingm@nvidia.com>\n <20210712014654.32428-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "6251a901-c4bf-44da-fa29-08d944d70766", "X-MS-TrafficTypeDiagnostic": "MWHPR12MB1375:", "X-Microsoft-Antispam-PRVS": "\n <MWHPR12MB13759C9C63EEA1A4C175E19EC1159@MWHPR12MB1375.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:7691;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n j9mfl8s/MT7n7iqtvEKZg+ogColgjTvridS7FF4jUC3nHy2/3IGEBu9h8LSDkhIesUDxVxIAnRS5nrm0Apg3ZuPpz132wbE3XvM3if2OrrJWHV+RKygglDqopdedOF3fPdHSIzMH6QHZIIXbooxnx0tjxEWUZ/K/G7fhtj+Yp8Aird9TfrAn8pamLdmVXUCG3mgCNcFk/cUPx1rLnFcm2ugWp3m01GZFmqgMsJ7nPoiLrNiltag1ekOTnY9ZTGJDc9YWUh1kLAWBBRKUMbT1593rmGM3qcyTZwNQmniTCJU84mhOjIWnezkqNfSd8ud8Nc852dbUIVVNykr0dtF71VMhVOdpXsa4HLwCFKpNFGrORKEnOefcL102nNVhro49P927CQoM7lQ2xXb3IlzCROSJWSPi9KaZ9Lp0Y426gY1n69lRJlNJazMCnS3xGXTMoQt5w1Tgr7j7BNNDrEEz2DDwyQaKDLxzixRxME23yJP5h3BkW2M/FYRyFPxLjg858GsBN6w6VmH9cgdh3l3nnPlXGtAvotNGuFh31ol0Pjgc/myuhm7CmTAlAZF9Q1VyUa4Cww7eIhx2gckpk1G7H2W6ZgTyyG/RBOjZjATUaOaw5cRifrU562UiCAuxGacDRgdc824bqrbFyQMcxmaj3KFzqNw39D/8n+wds3l+4Qo8f2GtvW1We6k2hz0IwJrnqXFl5LDXxIVsOwFMrfBoabqxQ2W1uy88LwGiOroQkpQ=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(396003)(136003)(376002)(346002)(39860400002)(46966006)(36840700001)(5660300002)(47076005)(7696005)(356005)(82740400003)(70206006)(7636003)(83380400001)(4326008)(86362001)(6636002)(426003)(6666004)(36860700001)(70586007)(2616005)(8676002)(54906003)(478600001)(8936002)(36756003)(336012)(82310400003)(26005)(16526019)(110136005)(34020700004)(36906005)(1076003)(316002)(186003)(2906002)(55016002)(6286002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "12 Jul 2021 01:47:38.0663 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6251a901-c4bf-44da-fa29-08d944d70766", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT013.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR12MB1375", "Subject": "[dpdk-dev] [PATCH v5 06/26] net/mlx5: optimize modify header action\n memory", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Matan Azrad <matan@nvidia.com>\n\nDefine the types of the modify header action fields to be with the\nminimum size needed for the optional values range.\n\nSigned-off-by: Matan Azrad <matan@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/common/mlx5/linux/mlx5_glue.h | 1 +\n drivers/net/mlx5/linux/mlx5_flow_os.h | 3 ++-\n drivers/net/mlx5/mlx5_flow.h | 6 +++---\n drivers/net/mlx5/mlx5_flow_dv.c | 13 ++++++-------\n 4 files changed, 12 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/linux/mlx5_glue.h b/drivers/common/mlx5/linux/mlx5_glue.h\nindex 61f40d5478..f39ef2dac7 100644\n--- a/drivers/common/mlx5/linux/mlx5_glue.h\n+++ b/drivers/common/mlx5/linux/mlx5_glue.h\n@@ -78,6 +78,7 @@ struct mlx5dv_devx_async_cmd_hdr;\n enum mlx5dv_dr_domain_type { unused, };\n struct mlx5dv_dr_domain;\n struct mlx5dv_dr_action;\n+#define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1\n #endif\n \n #ifndef HAVE_MLX5DV_DR_DEVX_PORT\ndiff --git a/drivers/net/mlx5/linux/mlx5_flow_os.h b/drivers/net/mlx5/linux/mlx5_flow_os.h\nindex cee685015b..1926d26410 100644\n--- a/drivers/net/mlx5/linux/mlx5_flow_os.h\n+++ b/drivers/net/mlx5/linux/mlx5_flow_os.h\n@@ -225,7 +225,8 @@ mlx5_flow_os_create_flow_action_modify_header(void *ctx, void *domain,\n \t\t\t(struct mlx5_flow_dv_modify_hdr_resource *)resource;\n \n \t*action = mlx5_glue->dv_create_flow_action_modify_header\n-\t\t\t\t\t(ctx, res->ft_type, domain, res->flags,\n+\t\t\t\t\t(ctx, res->ft_type, domain, res->root ?\n+\t\t\t\t\t MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL : 0,\n \t\t\t\t\t actions_len, (uint64_t *)res->actions);\n \treturn (*action) ? 0 : -1;\n }\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex adadcfa425..f1ebc153f2 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -524,11 +524,11 @@ struct mlx5_flow_dv_modify_hdr_resource {\n \tvoid *action; /**< Modify header action object. */\n \t/* Key area for hash list matching: */\n \tuint8_t ft_type; /**< Flow table type, Rx or Tx. */\n-\tuint32_t actions_num; /**< Number of modification actions. */\n-\tuint64_t flags; /**< Flags for RDMA API. */\n+\tuint8_t actions_num; /**< Number of modification actions. */\n+\tbool root; /**< Whether action is in root table. */\n \tstruct mlx5_modification_cmd actions[];\n \t/**< Modification actions. */\n-};\n+} __rte_packed;\n \n /* Modify resource key of the hash organization. */\n union mlx5_flow_modify_hdr_key {\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 49bc85f7b3..0f8b916991 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -5006,21 +5006,21 @@ flow_dv_validate_action_port_id(struct rte_eth_dev *dev,\n *\n * @param dev\n * Pointer to rte_eth_dev structure.\n- * @param flags\n- * Flags bits to check if root level.\n+ * @param root\n+ * Whether action is on root table.\n *\n * @return\n * Max number of modify header actions device can support.\n */\n static inline unsigned int\n flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,\n-\t\t\t uint64_t flags)\n+\t\t\t bool root)\n {\n \t/*\n \t * There's no way to directly query the max capacity from FW.\n \t * The maximal value on root table should be assumed to be supported.\n \t */\n-\tif (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))\n+\tif (!root)\n \t\treturn MLX5_MAX_MODIFY_NUM;\n \telse\n \t\treturn MLX5_ROOT_TBL_MODIFY_NUM;\n@@ -5622,10 +5622,9 @@ flow_dv_modify_hdr_resource_register\n \t};\n \tuint64_t key64;\n \n-\tresource->flags = dev_flow->dv.group ? 0 :\n-\t\t\t MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;\n+\tresource->root = !dev_flow->dv.group;\n \tif (resource->actions_num > flow_dv_modify_hdr_action_max(dev,\n-\t\t\t\t resource->flags))\n+\t\t\t\t\t\t\t\tresource->root))\n \t\treturn rte_flow_error_set(error, EOVERFLOW,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, NULL,\n \t\t\t\t\t \"too many modify header items\");\n", "prefixes": [ "v5", "06/26" ] }