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GET /api/patches/95661/?format=api
{ "id": 95661, "url": "http://patches.dpdk.org/api/patches/95661/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210712014654.32428-5-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210712014654.32428-5-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210712014654.32428-5-suanmingm@nvidia.com", "date": "2021-07-12T01:46:32", "name": "[v5,04/26] net/mlx5: support index pool non-lcore operations", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "c2340bc01e71a03dc8ebd05f727c4ad4bce17a83", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210712014654.32428-5-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17759, "url": "http://patches.dpdk.org/api/series/17759/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17759", "date": "2021-07-12T01:46:29", "name": "net/mlx5: insertion rate optimization", "version": 5, "mbox": "http://patches.dpdk.org/series/17759/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/95661/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/95661/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E34BBA0C4B;\n\tMon, 12 Jul 2021 03:47:55 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0553A4118A;\n\tMon, 12 Jul 2021 03:47:36 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2050.outbound.protection.outlook.com [40.107.236.50])\n by mails.dpdk.org (Postfix) with ESMTP id E356441180\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Date": "Mon, 12 Jul 2021 04:46:32 +0300", "Message-ID": "<20210712014654.32428-5-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20210712014654.32428-1-suanmingm@nvidia.com>", "References": "<20210527093403.1153127-1-suanmingm@nvidia.com>\n <20210712014654.32428-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "dadae785-0119-4ee4-55a9-08d944d703e2", "X-MS-TrafficTypeDiagnostic": "BN8PR12MB3587:", "X-Microsoft-Antispam-PRVS": "\n <BN8PR12MB3587B24D830D78D9ABC2FD2BC1159@BN8PR12MB3587.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:72;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n OBdoDRN3ivlWZiLl2yktv9Ii6HVF/aGRSpIT7K6J7OvdsnY5zMkFFsuL3j9d54XvLjmDJFHYdfu2EdKmqPhHAHWFUBr9SX83xWfEVxRG0yWShB1sZawp9RYwhhi7wXCr/eGSKGDfyXBqSI+w1OLVybG9IBGmFj1dVXIFuzbAiWopnlLMt/CClXHUL/azy5SMSw2lrMC65rDIXzGkk0/Qgc2CJSHJIkaGyFZPr6C8ZqabPSaVp+2Iu8DpdT/k1bJ17jXwgavDycxK91b3bGCmSb4TwaxVZJK1Q9bDEKeSYO3nkgVyqG6Il22opAwHiToXMP3opXqGdnV4seCpgAgMe5I2+iVF4d2aBcG5sqo4HA2eoBSJOuc6fEQlnkYREMe8TI9Wuf6v3l3XzwiEBZUEuGmZxq7hQW2p4dlI/8oJK9fkL6hInXehoReQAe0TfECC8XjuitB6Imk5S3FnLx66rbtD7jbPixCwRW24oO5ikEFQ32X/i0yDOTzPzPYTwvLhhk7sG+8lA6LnaxOcsIUXtj93sKP570Fqqq2h6XBzcty6HqkXDj0/P4hkQTsEgjHyYlsyWUXnSyWfBH4Edf3sp5eAgthZQBn71J77KBjNXlXl9/KzLUB3IqjfXdg6LxGtvMQ/9YUByspBIQZMliEwhy62bh5D3cuA3egHmUwIrbGZDTMWaOzbuPHXmXsAwZqF4hiaymBTnDJ/Wvg1NPiDGcMOvUAqyfjn2hrKHZNAFnU=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(396003)(376002)(39860400002)(136003)(346002)(36840700001)(46966006)(6286002)(36860700001)(426003)(478600001)(2616005)(6666004)(6636002)(7636003)(47076005)(336012)(1076003)(186003)(34020700004)(110136005)(8936002)(83380400001)(356005)(82740400003)(7696005)(82310400003)(5660300002)(16526019)(86362001)(36906005)(70206006)(54906003)(26005)(4326008)(70586007)(55016002)(316002)(2906002)(8676002)(36756003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "12 Jul 2021 01:47:32.1609 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n dadae785-0119-4ee4-55a9-08d944d703e2", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT009.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN8PR12MB3587", "Subject": "[dpdk-dev] [PATCH v5 04/26] net/mlx5: support index pool non-lcore\n operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit supports the index pool non-lcore operations with\nan extra cache and lcore lock.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_utils.c | 75 +++++++++++++++++++++++++----------\n drivers/net/mlx5/mlx5_utils.h | 3 +-\n 2 files changed, 56 insertions(+), 22 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_utils.c b/drivers/net/mlx5/mlx5_utils.c\nindex 32f8d65073..f9557c09ff 100644\n--- a/drivers/net/mlx5/mlx5_utils.c\n+++ b/drivers/net/mlx5/mlx5_utils.c\n@@ -275,6 +275,7 @@ mlx5_ipool_create(struct mlx5_indexed_pool_config *cfg)\n \t\t\tmlx5_trunk_idx_offset_get(pool, TRUNK_MAX_IDX + 1);\n \tif (!cfg->per_core_cache)\n \t\tpool->free_list = TRUNK_INVALID;\n+\trte_spinlock_init(&pool->lcore_lock);\n \treturn pool;\n }\n \n@@ -515,20 +516,14 @@ mlx5_ipool_allocate_from_global(struct mlx5_indexed_pool *pool, int cidx)\n }\n \n static void *\n-mlx5_ipool_get_cache(struct mlx5_indexed_pool *pool, uint32_t idx)\n+_mlx5_ipool_get_cache(struct mlx5_indexed_pool *pool, int cidx, uint32_t idx)\n {\n \tstruct mlx5_indexed_trunk *trunk;\n \tstruct mlx5_indexed_cache *lc;\n \tuint32_t trunk_idx;\n \tuint32_t entry_idx;\n-\tint cidx;\n \n \tMLX5_ASSERT(idx);\n-\tcidx = rte_lcore_index(rte_lcore_id());\n-\tif (unlikely(cidx == -1)) {\n-\t\trte_errno = ENOTSUP;\n-\t\treturn NULL;\n-\t}\n \tif (unlikely(!pool->cache[cidx])) {\n \t\tpool->cache[cidx] = pool->cfg.malloc(MLX5_MEM_ZERO,\n \t\t\tsizeof(struct mlx5_ipool_per_lcore) +\n@@ -549,15 +544,27 @@ mlx5_ipool_get_cache(struct mlx5_indexed_pool *pool, uint32_t idx)\n }\n \n static void *\n-mlx5_ipool_malloc_cache(struct mlx5_indexed_pool *pool, uint32_t *idx)\n+mlx5_ipool_get_cache(struct mlx5_indexed_pool *pool, uint32_t idx)\n {\n+\tvoid *entry;\n \tint cidx;\n \n \tcidx = rte_lcore_index(rte_lcore_id());\n \tif (unlikely(cidx == -1)) {\n-\t\trte_errno = ENOTSUP;\n-\t\treturn NULL;\n+\t\tcidx = RTE_MAX_LCORE;\n+\t\trte_spinlock_lock(&pool->lcore_lock);\n \t}\n+\tentry = _mlx5_ipool_get_cache(pool, cidx, idx);\n+\tif (unlikely(cidx == RTE_MAX_LCORE))\n+\t\trte_spinlock_unlock(&pool->lcore_lock);\n+\treturn entry;\n+}\n+\n+\n+static void *\n+_mlx5_ipool_malloc_cache(struct mlx5_indexed_pool *pool, int cidx,\n+\t\t\t uint32_t *idx)\n+{\n \tif (unlikely(!pool->cache[cidx])) {\n \t\tpool->cache[cidx] = pool->cfg.malloc(MLX5_MEM_ZERO,\n \t\t\tsizeof(struct mlx5_ipool_per_lcore) +\n@@ -570,29 +577,40 @@ mlx5_ipool_malloc_cache(struct mlx5_indexed_pool *pool, uint32_t *idx)\n \t} else if (pool->cache[cidx]->len) {\n \t\tpool->cache[cidx]->len--;\n \t\t*idx = pool->cache[cidx]->idx[pool->cache[cidx]->len];\n-\t\treturn mlx5_ipool_get_cache(pool, *idx);\n+\t\treturn _mlx5_ipool_get_cache(pool, cidx, *idx);\n \t}\n \t/* Not enough idx in global cache. Keep fetching from global. */\n \t*idx = mlx5_ipool_allocate_from_global(pool, cidx);\n \tif (unlikely(!(*idx)))\n \t\treturn NULL;\n-\treturn mlx5_ipool_get_cache(pool, *idx);\n+\treturn _mlx5_ipool_get_cache(pool, cidx, *idx);\n }\n \n-static void\n-mlx5_ipool_free_cache(struct mlx5_indexed_pool *pool, uint32_t idx)\n+static void *\n+mlx5_ipool_malloc_cache(struct mlx5_indexed_pool *pool, uint32_t *idx)\n {\n+\tvoid *entry;\n \tint cidx;\n+\n+\tcidx = rte_lcore_index(rte_lcore_id());\n+\tif (unlikely(cidx == -1)) {\n+\t\tcidx = RTE_MAX_LCORE;\n+\t\trte_spinlock_lock(&pool->lcore_lock);\n+\t}\n+\tentry = _mlx5_ipool_malloc_cache(pool, cidx, idx);\n+\tif (unlikely(cidx == RTE_MAX_LCORE))\n+\t\trte_spinlock_unlock(&pool->lcore_lock);\n+\treturn entry;\n+}\n+\n+static void\n+_mlx5_ipool_free_cache(struct mlx5_indexed_pool *pool, int cidx, uint32_t idx)\n+{\n \tstruct mlx5_ipool_per_lcore *ilc;\n \tstruct mlx5_indexed_cache *gc, *olc = NULL;\n \tuint32_t reclaim_num = 0;\n \n \tMLX5_ASSERT(idx);\n-\tcidx = rte_lcore_index(rte_lcore_id());\n-\tif (unlikely(cidx == -1)) {\n-\t\trte_errno = ENOTSUP;\n-\t\treturn;\n-\t}\n \t/*\n \t * When index was allocated on core A but freed on core B. In this\n \t * case check if local cache on core B was allocated before.\n@@ -635,6 +653,21 @@ mlx5_ipool_free_cache(struct mlx5_indexed_pool *pool, uint32_t idx)\n \tpool->cache[cidx]->len++;\n }\n \n+static void\n+mlx5_ipool_free_cache(struct mlx5_indexed_pool *pool, uint32_t idx)\n+{\n+\tint cidx;\n+\n+\tcidx = rte_lcore_index(rte_lcore_id());\n+\tif (unlikely(cidx == -1)) {\n+\t\tcidx = RTE_MAX_LCORE;\n+\t\trte_spinlock_lock(&pool->lcore_lock);\n+\t}\n+\t_mlx5_ipool_free_cache(pool, cidx, idx);\n+\tif (unlikely(cidx == RTE_MAX_LCORE))\n+\t\trte_spinlock_unlock(&pool->lcore_lock);\n+}\n+\n void *\n mlx5_ipool_malloc(struct mlx5_indexed_pool *pool, uint32_t *idx)\n {\n@@ -814,7 +847,7 @@ mlx5_ipool_destroy(struct mlx5_indexed_pool *pool)\n \tMLX5_ASSERT(pool);\n \tmlx5_ipool_lock(pool);\n \tif (pool->cfg.per_core_cache) {\n-\t\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n+\t\tfor (i = 0; i <= RTE_MAX_LCORE; i++) {\n \t\t\t/*\n \t\t\t * Free only old global cache. Pool gc will be\n \t\t\t * freed at last.\n@@ -883,7 +916,7 @@ mlx5_ipool_flush_cache(struct mlx5_indexed_pool *pool)\n \tfor (i = 0; i < gc->len; i++)\n \t\trte_bitmap_clear(ibmp, gc->idx[i] - 1);\n \t/* Clear core cache. */\n-\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n+\tfor (i = 0; i < RTE_MAX_LCORE + 1; i++) {\n \t\tstruct mlx5_ipool_per_lcore *ilc = pool->cache[i];\n \n \t\tif (!ilc)\ndiff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h\nindex 737dd7052d..a509b0a4eb 100644\n--- a/drivers/net/mlx5/mlx5_utils.h\n+++ b/drivers/net/mlx5/mlx5_utils.h\n@@ -248,6 +248,7 @@ struct mlx5_ipool_per_lcore {\n struct mlx5_indexed_pool {\n \tstruct mlx5_indexed_pool_config cfg; /* Indexed pool configuration. */\n \trte_spinlock_t rsz_lock; /* Pool lock for multiple thread usage. */\n+\trte_spinlock_t lcore_lock;\n \t/* Dim of trunk pointer array. */\n \tunion {\n \t\tstruct {\n@@ -259,7 +260,7 @@ struct mlx5_indexed_pool {\n \t\tstruct {\n \t\t\tstruct mlx5_indexed_cache *gc;\n \t\t\t/* Global cache. */\n-\t\t\tstruct mlx5_ipool_per_lcore *cache[RTE_MAX_LCORE];\n+\t\t\tstruct mlx5_ipool_per_lcore *cache[RTE_MAX_LCORE + 1];\n \t\t\t/* Local cache. */\n \t\t\tstruct rte_bitmap *ibmp;\n \t\t\tvoid *bmp_mem;\n", "prefixes": [ "v5", "04/26" ] }