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GET /api/patches/95057/?format=api
{ "id": 95057, "url": "http://patches.dpdk.org/api/patches/95057/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210630124609.8711-4-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210630124609.8711-4-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210630124609.8711-4-suanmingm@nvidia.com", "date": "2021-06-30T12:45:50", "name": "[v2,03/22] net/mlx5: add index pool foreach define", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "26b50cbb58cf0476002d862dfd96f750f20a77f9", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210630124609.8711-4-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17549, "url": "http://patches.dpdk.org/api/series/17549/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17549", "date": "2021-06-30T12:45:47", "name": "net/mlx5: insertion rate optimization", "version": 2, "mbox": "http://patches.dpdk.org/series/17549/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/95057/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/95057/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2C2AEA0A0F;\n\tWed, 30 Jun 2021 14:46:53 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 408FD41279;\n\tWed, 30 Jun 2021 14:46:46 +0200 (CEST)", "from NAM02-SN1-obe.outbound.protection.outlook.com\n (mail-sn1anam02on2059.outbound.protection.outlook.com [40.107.96.59])\n by mails.dpdk.org (Postfix) with ESMTP id 23A3140141\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Date": "Wed, 30 Jun 2021 15:45:50 +0300", "Message-ID": "<20210630124609.8711-4-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20210630124609.8711-1-suanmingm@nvidia.com>", "References": "<20210527093403.1153127-1-suanmingm@nvidia.com>\n <20210630124609.8711-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "b0b86662-d09c-4ec6-3226-08d93bc51bc8", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB3244:", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB32449B0782C05859E6364017C1019@DM6PR12MB3244.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:156;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n V/G7yWR2k21CeOzu7UEbBkQbMzyC7k8VT17vKT9GcFEM9AUfepG85skZLCNuLluAKewrLdzsOQEqsJlBgpZA1U2fosccT5yqimLAISZ6Ukr0Juu4DiBhIP6hrftOfApRm740rUoXl/j5Bt3G4E5xrKipqkP4SuktetOUa/87MR49Psc9hcD6W6cp3r87Nk+u2r0BuDC0o6vMbCLCKhEsxgk3RSGALx1Kg1SZ+rQFUZQDTGOR8Nzzu0nhFjyPGYv4VbCJOn8EUtVIq2dSqvlLABC7CL0fd75nNa+wkpBWPIETH1UjioCuefIkuzcCZ/LGV2d3JZP1DmL31AApilTZxAXClt7Sg6iH4aoKlIUXJzi8MDENTm79Q1ZBohvFXMmjqfDdiQOvquv7yy14Q729ehM7ZHotgxJMHnAexCgkufM0Wk2hpvDseFhoBaXjBQRP932cyjjfML4zH4PWYDj+yVOPnrIcD8LpI4UNxpepe5S6xu86/t69oyebEh/5LLXOQ8xJ1WibwbZXOOQOES/WCe+tMSkVme+rAVLyogYpQKdJ4lEeEXRNPejMFTjM3NGCoU82RblOJdRTvT9sAEjT3IaUtL85FogwXcK/fzptBUAakkkLXzv6M7/O/QyRv6kVon0GCM6AXLHK08VWV8r4ltOx5NPSE8U0MZOxyRfdIWkWZoPgP+4ab3oy2+mTZf4POz1ZECa5GGZNXkhXaiIrYA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(376002)(136003)(39860400002)(346002)(396003)(46966006)(36840700001)(70586007)(70206006)(5660300002)(6636002)(336012)(7696005)(86362001)(2906002)(36756003)(36860700001)(186003)(83380400001)(16526019)(55016002)(82310400003)(47076005)(82740400003)(2616005)(110136005)(54906003)(6666004)(1076003)(8936002)(7636003)(426003)(26005)(478600001)(316002)(4326008)(8676002)(6286002)(356005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Jun 2021 12:46:40.8667 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b0b86662-d09c-4ec6-3226-08d93bc51bc8", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT042.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB3244", "Subject": "[dpdk-dev] [PATCH v2 03/22] net/mlx5: add index pool foreach define", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "In some cases, application may want to know all the allocated\nindex in order to apply some operations to the allocated index.\n\nThis commit adds the indexed pool functions to support foreach\noperation.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_utils.c | 86 +++++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_utils.h | 8 ++++\n 2 files changed, 94 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5_utils.c b/drivers/net/mlx5/mlx5_utils.c\nindex 215024632d..0ed279e162 100644\n--- a/drivers/net/mlx5/mlx5_utils.c\n+++ b/drivers/net/mlx5/mlx5_utils.c\n@@ -839,6 +839,92 @@ mlx5_ipool_destroy(struct mlx5_indexed_pool *pool)\n \treturn 0;\n }\n \n+void\n+mlx5_ipool_flush_cache(struct mlx5_indexed_pool *pool)\n+{\n+\tuint32_t i, j;\n+\tstruct mlx5_indexed_cache *gc;\n+\tstruct rte_bitmap *ibmp;\n+\tuint32_t bmp_num, mem_size;\n+\n+\tif (!pool->cfg.per_core_cache)\n+\t\treturn;\n+\tgc = pool->gc;\n+\tif (!gc)\n+\t\treturn;\n+\t/* Reset bmp. */\n+\tbmp_num = mlx5_trunk_idx_offset_get(pool, gc->n_trunk_valid);\n+\tmem_size = rte_bitmap_get_memory_footprint(bmp_num);\n+\tpool->bmp_mem = pool->cfg.malloc(MLX5_MEM_ZERO, mem_size,\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE, rte_socket_id());\n+\tif (!pool->bmp_mem) {\n+\t\tDRV_LOG(ERR, \"Ipool bitmap mem allocate failed.\\n\");\n+\t\treturn;\n+\t}\n+\tibmp = rte_bitmap_init_with_all_set(bmp_num, pool->bmp_mem, mem_size);\n+\tif (!ibmp) {\n+\t\tpool->cfg.free(pool->bmp_mem);\n+\t\tpool->bmp_mem = NULL;\n+\t\tDRV_LOG(ERR, \"Ipool bitmap create failed.\\n\");\n+\t\treturn;\n+\t}\n+\tpool->ibmp = ibmp;\n+\t/* Clear global cache. */\n+\tfor (i = 0; i < gc->len; i++)\n+\t\trte_bitmap_clear(ibmp, gc->idx[i] - 1);\n+\t/* Clear core cache. */\n+\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n+\t\tstruct mlx5_ipool_per_lcore *ilc = pool->cache[i];\n+\n+\t\tif (!ilc)\n+\t\t\tcontinue;\n+\t\tfor (j = 0; j < ilc->len; j++)\n+\t\t\trte_bitmap_clear(ibmp, ilc->idx[j] - 1);\n+\t}\n+}\n+\n+static void *\n+mlx5_ipool_get_next_cache(struct mlx5_indexed_pool *pool, uint32_t *pos)\n+{\n+\tstruct rte_bitmap *ibmp;\n+\tuint64_t slab = 0;\n+\tuint32_t iidx = *pos;\n+\n+\tibmp = pool->ibmp;\n+\tif (!ibmp || !rte_bitmap_scan(ibmp, &iidx, &slab)) {\n+\t\tif (pool->bmp_mem) {\n+\t\t\tpool->cfg.free(pool->bmp_mem);\n+\t\t\tpool->bmp_mem = NULL;\n+\t\t\tpool->ibmp = NULL;\n+\t\t}\n+\t\treturn NULL;\n+\t}\n+\tiidx += __builtin_ctzll(slab);\n+\trte_bitmap_clear(ibmp, iidx);\n+\tiidx++;\n+\t*pos = iidx;\n+\treturn mlx5_ipool_get_cache(pool, iidx);\n+}\n+\n+void *\n+mlx5_ipool_get_next(struct mlx5_indexed_pool *pool, uint32_t *pos)\n+{\n+\tuint32_t idx = *pos;\n+\tvoid *entry;\n+\n+\tif (pool->cfg.per_core_cache)\n+\t\treturn mlx5_ipool_get_next_cache(pool, pos);\n+\twhile (idx <= mlx5_trunk_idx_offset_get(pool, pool->n_trunk)) {\n+\t\tentry = mlx5_ipool_get(pool, idx);\n+\t\tif (entry) {\n+\t\t\t*pos = idx;\n+\t\t\treturn entry;\n+\t\t}\n+\t\tidx++;\n+\t}\n+\treturn NULL;\n+}\n+\n void\n mlx5_ipool_dump(struct mlx5_indexed_pool *pool)\n {\ndiff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h\nindex 0469062695..737dd7052d 100644\n--- a/drivers/net/mlx5/mlx5_utils.h\n+++ b/drivers/net/mlx5/mlx5_utils.h\n@@ -261,6 +261,9 @@ struct mlx5_indexed_pool {\n \t\t\t/* Global cache. */\n \t\t\tstruct mlx5_ipool_per_lcore *cache[RTE_MAX_LCORE];\n \t\t\t/* Local cache. */\n+\t\t\tstruct rte_bitmap *ibmp;\n+\t\t\tvoid *bmp_mem;\n+\t\t\t/* Allocate objects bitmap. Use during flush. */\n \t\t};\n \t};\n #ifdef POOL_DEBUG\n@@ -862,4 +865,9 @@ struct {\t\t\t\t\t\t\t\t\\\n \t (entry);\t\t\t\t\t\t\t\\\n \t idx++, (entry) = mlx5_l3t_get_next((tbl), &idx))\n \n+#define MLX5_IPOOL_FOREACH(ipool, idx, entry)\t\t\t\t\\\n+\tfor ((idx) = 0, mlx5_ipool_flush_cache((ipool)),\t\t\\\n+\t (entry) = mlx5_ipool_get_next((ipool), &idx);\t\t\\\n+\t (entry); idx++, (entry) = mlx5_ipool_get_next((ipool), &idx))\n+\n #endif /* RTE_PMD_MLX5_UTILS_H_ */\n", "prefixes": [ "v2", "03/22" ] }