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GET /api/patches/93826/?format=api
{ "id": 93826, "url": "http://patches.dpdk.org/api/patches/93826/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1622652221-22732-19-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1622652221-22732-19-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1622652221-22732-19-git-send-email-anoobj@marvell.com", "date": "2021-06-02T16:43:39", "name": "[18/20] crypto/cnxk: add KASUMI decrypt", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e56b9f4db2894499bd927dc89639c9b5c12bf9b2", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1622652221-22732-19-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17213, "url": "http://patches.dpdk.org/api/series/17213/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17213", "date": "2021-06-02T16:43:21", "name": "Add Marvell CNXK crypto PMDs", "version": 1, "mbox": "http://patches.dpdk.org/series/17213/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/93826/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/93826/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 69398A0524;\n\tWed, 2 Jun 2021 18:46:44 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0365E410E6;\n\tWed, 2 Jun 2021 18:45:49 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id B2804410EA\n for <dev@dpdk.org>; Wed, 2 Jun 2021 18:45:46 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 152GarZf016120; Wed, 2 Jun 2021 09:45:45 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 38wug73va0-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Wed, 02 Jun 2021 09:45:45 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 2 Jun 2021 09:45:44 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 2 Jun 2021 09:45:44 -0700", "from HY-LT1002.marvell.com (unknown [10.193.70.1])\n by maili.marvell.com (Postfix) with ESMTP id D816F3F7048;\n Wed, 2 Jun 2021 09:45:39 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=AzWscRvCGjGtTxv3MBbMcCtrcrcvjXxLYnQOq2Y+jb4=;\n b=Sju5Cz339dS6C5l9YwaKbc/WBvQAKHuid2CEyf72EgKuXzTnGUuKG2+XR24irtAGdE48\n rb27Ib67Ax/jj6vxOFx3FAMCNzTPuiE5xXHR+/Rmlk6c/Y7NdU7sRKZOQ+sZ3OqBwqEy\n qzNarxZj1UtRW/dU53lKAwBtkt7vgtO/5ByoJD/fZyvCXz/aimlICjeAWL5B3SJTN7bO\n Kg0Xc7EC2B/oQ1u/1qFcDCC25BQRURjqCjmGUFz3pNTQAQTb2aXqBdfbohrZRij637oW\n dBTyBZof1sSLqKxe9TmqEyaIa5J+ySrg6mo8U4RoL4apTyWcIaKdJbCeQKdnr/rSHbZn fg==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Tejasree Kondoj <ktejasree@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n Ankur Dwivedi <adwivedi@marvell.com>, <dev@dpdk.org>, Anoob Joseph\n <anoobj@marvell.com>, Archana Muniganti <marchana@marvell.com>", "Date": "Wed, 2 Jun 2021 22:13:39 +0530", "Message-ID": "<1622652221-22732-19-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1622652221-22732-1-git-send-email-anoobj@marvell.com>", "References": "<1622652221-22732-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "k-M65QNCebo35KQYSyipkZl0jjLlLMAk", "X-Proofpoint-GUID": "k-M65QNCebo35KQYSyipkZl0jjLlLMAk", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-06-02_09:2021-06-02,\n 2021-06-02 signatures=0", "Subject": "[dpdk-dev] [PATCH 18/20] crypto/cnxk: add KASUMI decrypt", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Tejasree Kondoj <ktejasree@marvell.com>\n\nAdd KASUMI decrypt support.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Archana Muniganti <marchana@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n drivers/crypto/cnxk/cnxk_se.h | 133 ++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 133 insertions(+)", "diff": "diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h\nindex c0e5cff..1bdd028 100644\n--- a/drivers/crypto/cnxk/cnxk_se.h\n+++ b/drivers/crypto/cnxk/cnxk_se.h\n@@ -1758,6 +1758,137 @@ cpt_kasumi_enc_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n }\n \n static __rte_always_inline int\n+cpt_kasumi_dec_prep(uint64_t d_offs, uint64_t d_lens,\n+\t\t struct roc_se_fc_params *params, struct cpt_inst_s *inst)\n+{\n+\tvoid *m_vaddr = params->meta_buf.vaddr;\n+\tuint32_t size;\n+\tint32_t inputlen = 0, outputlen;\n+\tstruct roc_se_ctx *se_ctx;\n+\tuint8_t i = 0, iv_len = 8;\n+\tuint32_t encr_offset;\n+\tuint32_t encr_data_len;\n+\tint flags;\n+\tuint8_t dir = 0;\n+\tuint64_t *offset_vaddr;\n+\tunion cpt_inst_w4 cpt_inst_w4;\n+\tuint8_t *in_buffer;\n+\tuint32_t g_size_bytes, s_size_bytes;\n+\tstruct roc_se_sglist_comp *gather_comp;\n+\tstruct roc_se_sglist_comp *scatter_comp;\n+\n+\tencr_offset = ROC_SE_ENCR_OFFSET(d_offs) / 8;\n+\tencr_data_len = ROC_SE_ENCR_DLEN(d_lens);\n+\n+\tse_ctx = params->ctx_buf.vaddr;\n+\tflags = se_ctx->zsk_flags;\n+\n+\tcpt_inst_w4.u64 = 0;\n+\tcpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_KASUMI | ROC_SE_DMA_MODE;\n+\n+\t/* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */\n+\tcpt_inst_w4.s.opcode_minor = ((1 << 6) | (se_ctx->k_ecb << 5) |\n+\t\t\t\t (dir << 4) | (0 << 3) | (flags & 0x7));\n+\n+\t/*\n+\t * GP op header, lengths are expected in bits.\n+\t */\n+\tcpt_inst_w4.s.param1 = encr_data_len;\n+\n+\t/* consider iv len */\n+\tencr_offset += iv_len;\n+\n+\tinputlen = iv_len + (RTE_ALIGN(encr_data_len, 8) / 8);\n+\toutputlen = inputlen;\n+\n+\t/* save space for offset ctrl & iv */\n+\toffset_vaddr = m_vaddr;\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + iv_len;\n+\n+\t/* DPTR has SG list */\n+\tin_buffer = m_vaddr;\n+\n+\t((uint16_t *)in_buffer)[0] = 0;\n+\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t/* TODO Add error check if space will be sufficient */\n+\tgather_comp = (struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);\n+\n+\t/*\n+\t * Input Gather List\n+\t */\n+\ti = 0;\n+\n+\t/* Offset control word followed by iv */\n+\t*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);\n+\tif (unlikely((encr_offset >> 16))) {\n+\t\tCPT_LOG_DP_ERR(\"Offset not supported\");\n+\t\tCPT_LOG_DP_ERR(\"enc_offset: %d\", encr_offset);\n+\t\treturn -1;\n+\t}\n+\n+\ti = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,\n+\t\t\t ROC_SE_OFF_CTRL_LEN + iv_len);\n+\n+\t/* IV */\n+\tmemcpy((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN, params->iv_buf,\n+\t iv_len);\n+\n+\t/* Add input data */\n+\tsize = inputlen - iv_len;\n+\tif (size) {\n+\t\ti = fill_sg_comp_from_iov(gather_comp, i, params->src_iov, 0,\n+\t\t\t\t\t &size, NULL, 0);\n+\t\tif (unlikely(size)) {\n+\t\t\tCPT_LOG_DP_ERR(\"Insufficient buffer space,\"\n+\t\t\t\t \" size %d needed\",\n+\t\t\t\t size);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\tg_size_bytes = ((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);\n+\n+\t/*\n+\t * Output Scatter List\n+\t */\n+\n+\ti = 0;\n+\tscatter_comp = (struct roc_se_sglist_comp *)((uint8_t *)gather_comp +\n+\t\t\t\t\t\t g_size_bytes);\n+\n+\t/* IV */\n+\ti = fill_sg_comp(scatter_comp, i,\n+\t\t\t (uint64_t)offset_vaddr + ROC_SE_OFF_CTRL_LEN, iv_len);\n+\n+\t/* Add output data */\n+\tsize = outputlen - iv_len;\n+\tif (size) {\n+\t\ti = fill_sg_comp_from_iov(scatter_comp, i, params->dst_iov, 0,\n+\t\t\t\t\t &size, NULL, 0);\n+\t\tif (unlikely(size)) {\n+\t\t\tCPT_LOG_DP_ERR(\"Insufficient buffer space,\"\n+\t\t\t\t \" size %d needed\",\n+\t\t\t\t size);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\ts_size_bytes = ((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);\n+\n+\tsize = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;\n+\n+\t/* This is DPTR len in case of SG mode */\n+\tcpt_inst_w4.s.dlen = size;\n+\n+\tinst->dptr = (uint64_t)in_buffer;\n+\tinst->w4.u64 = cpt_inst_w4.u64;\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \t\t struct roc_se_fc_params *fc_params,\n \t\t struct cpt_inst_s *inst)\n@@ -1773,6 +1904,8 @@ cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \t} else if (fc_type == ROC_SE_PDCP) {\n \t\tret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens, fc_params,\n \t\t\t\t\t inst);\n+\t} else if (fc_type == ROC_SE_KASUMI) {\n+\t\tret = cpt_kasumi_dec_prep(d_offs, d_lens, fc_params, inst);\n \t}\n \treturn ret;\n }\n", "prefixes": [ "18/20" ] }