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GET /api/patches/93688/?format=api
{ "id": 93688, "url": "http://patches.dpdk.org/api/patches/93688/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210601071122.1612432-2-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210601071122.1612432-2-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210601071122.1612432-2-michaelba@nvidia.com", "date": "2021-06-01T07:11:20", "name": "[2/4] compress/mlx5: fix constant size in QP creation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7db690cf821fcb367d4710d0f841c64375d94fd6", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210601071122.1612432-2-michaelba@nvidia.com/mbox/", "series": [ { "id": 17180, "url": "http://patches.dpdk.org/api/series/17180/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17180", "date": "2021-06-01T07:11:21", "name": "[1/4] regex/mlx5: fix size of setup constants", "version": 1, "mbox": "http://patches.dpdk.org/series/17180/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/93688/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/93688/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 00A13A0A0E;\n\tTue, 1 Jun 2021 09:31:19 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4532C410FC;\n\tTue, 1 Jun 2021 09:11:54 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2067.outbound.protection.outlook.com [40.107.92.67])\n by mails.dpdk.org (Postfix) with ESMTP id 0BE00410ED;\n Tue, 1 Jun 2021 09:11:52 +0200 (CEST)", "from BN6PR13CA0043.namprd13.prod.outlook.com (2603:10b6:404:13e::29)\n by BYAPR12MB3000.namprd12.prod.outlook.com (2603:10b6:a03:d7::17)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.24; 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dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, <stable@dpdk.org>", "Date": "Tue, 1 Jun 2021 10:11:20 +0300", "Message-ID": "<20210601071122.1612432-2-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210601071122.1612432-1-michaelba@nvidia.com>", "References": "<20210601071122.1612432-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "92cfd506-00ef-452c-e202-08d924cc876d", "X-MS-TrafficTypeDiagnostic": "BYAPR12MB3000:", "X-Microsoft-Antispam-PRVS": "\n <BYAPR12MB30006BD9D0CB5DA2686123F7CC3E9@BYAPR12MB3000.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:3513;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n sbbVKqOu2NAS7WPbNxC+HyAloLme8ZCm+b0WnkW+wl04iJyJ8diCP3aAOXkzHysWgGrzYPtoqcwKRCoxwJtkY9gGDWPU1Yeo77QjrEQ/CACX24lMI7gGcaVjRda2SC33z5BdEH9lyt1coCti/VTw1Ku5zONaZSC+f6M1OobUKU2iaEu3dJArbuSbUb3t/WwxJovseLCwI/NhObWZC3Ll6SeJjnBlMqbz4dQYPrOP0om9v5VFpkOi8w6v2Z/ClTPgnlMDuR1OLSr0F1Iu2OIodidNl9CF58XNvcU7te0BXmMSjhkDmBKPRTeLXW/Sy8lf4x1HzHym8D2KBfzEuh8wfc746ERkbFOa8lt3mIsccGQ6uMGsRibQS6JoVnLI6LpXrewUnvYUFBnS2v/nZcO9ALncNVf5mHaC/sDTIS7d39Ji9T4NrZhx5VB1MGUUAa+StcYCKHIXTH4QbH6Gru5frjkRgF/NvPn7xcfPjvCeweute8QLMoN0pqiFJTFJEvv/KmqE37doB5B7aXgmJ2FLrh7MieWkgpmyiLlkbzEku4l7sqXaoRV4pNfJ08jy6/CuGjT79RTNbsW0btLnf0PSwNTCJ8sPVnyOxbF96rFIGlbsLwTgwhrMJe72RrtAsuV8QcVpQS5GBuFtlucR39ozxg==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(39860400002)(376002)(396003)(136003)(346002)(36840700001)(46966006)(5660300002)(36756003)(26005)(7636003)(426003)(6916009)(6286002)(16526019)(36906005)(7696005)(316002)(8676002)(82310400003)(336012)(70586007)(450100002)(36860700001)(4326008)(55016002)(8936002)(86362001)(83380400001)(82740400003)(2906002)(1076003)(478600001)(2616005)(186003)(54906003)(6666004)(356005)(70206006)(47076005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Jun 2021 07:11:51.1950 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 92cfd506-00ef-452c-e202-08d924cc876d", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT003.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR12MB3000", "Subject": "[dpdk-dev] [PATCH 2/4] compress/mlx5: fix constant size in QP\n creation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The mlx5_compress_qp_setup function makes shifting to the numeric\nconstant 1, then sends it as a parameter to rte_calloc function.\n\nThe rte_calloc function expects to get size_t (64 bits, unsigned) and\ninstead gets a 32-bit variable, because the numeric constant size is a\n32-bit.\nIn case the shift is greater than 32 the variable will lose its value\neven though the function can get 64-bit argument.\n\nChange the size of the numeric constant 1 to 64-bit.\n\nFixes: 8619fcd5161b (\"compress/mlx5: support queue pair operations\")\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/compress/mlx5/mlx5_compress.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)", "diff": "diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex 80c564f10b..90d009c56b 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -209,7 +209,7 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \t\treturn -rte_errno;\n \t}\n \tdev->data->queue_pairs[qp_id] = qp;\n-\topaq_buf = rte_calloc(__func__, 1u << log_ops_n,\n+\topaq_buf = rte_calloc(__func__, RTE_BIT64(log_ops_n),\n \t\t\t sizeof(struct mlx5_gga_compress_opaque),\n \t\t\t sizeof(struct mlx5_gga_compress_opaque));\n \tif (opaq_buf == NULL) {\n", "prefixes": [ "2/4" ] }