Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/93642/?format=api
{ "id": 93642, "url": "http://patches.dpdk.org/api/patches/93642/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210531214142.30167-4-tduszynski@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210531214142.30167-4-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210531214142.30167-4-tduszynski@marvell.com", "date": "2021-05-31T21:41:17", "name": "[03/28] common/cnxk: add support for getting link information", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "eaaa45c5d378ade5d9aa5aca010b5e96050a5d65", "submitter": { "id": 2215, "url": "http://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210531214142.30167-4-tduszynski@marvell.com/mbox/", "series": [ { "id": 17173, "url": "http://patches.dpdk.org/api/series/17173/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17173", "date": "2021-05-31T21:41:14", "name": "add support for baseband phy", "version": 1, "mbox": "http://patches.dpdk.org/series/17173/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/93642/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/93642/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 56339A0524;\n\tMon, 31 May 2021 23:42:15 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5B36C410E2;\n\tMon, 31 May 2021 23:42:05 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id BD3BE410D7\n for <dev@dpdk.org>; Mon, 31 May 2021 23:42:03 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 14VLeJBF002825; Mon, 31 May 2021 14:42:01 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 38vtnja11w-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 31 May 2021 14:42:01 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 31 May 2021 14:41:59 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 31 May 2021 14:41:59 -0700", "from EH-LT0048.marvell.com (unknown [10.193.32.52])\n by maili.marvell.com (Postfix) with ESMTP id 44FDC3F7041;\n Mon, 31 May 2021 14:41:57 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=M1s4SIMWI1PSoSUatIQPj2YV3K0RjAIlp+pugI9LUqQ=;\n b=NTAU1PCSM5QY8OjFkqmzPN9NcSh/apg19A7tAcNNV6D86iJCvH80G57eWSeC3VqSBqOS\n kz7N+ybt2Rcki++UYluN8H2TnCpl2E/ZGxXYy/1+l1UFDwLW6dPm/KM0zwdc6f8mlWuW\n fhD5FHTJlXmJagtrWEsXNMIgIL3j8FO8iAyTfDqleU8918gcqFX5MMPxJCHAab2CTG/7\n qndgIosKCCbd19da/E770krqOQzF+p+AS1tPZ9RZM2amvMH7CP2LElGH+1MPUdM6FzaK\n qxVpSNjfFZT/842tsYsKFf6MA7PhTs0+7815pjTHZaSveF8Z7TAxrXaVqr+pdn7oe+BJ nA==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jpalider@marvell.com>, <jerinj@marvell.com>, Tomasz Duszynski\n <tduszynski@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>,\n \"Kiran Kumar K\" <kirankumark@marvell.com>,\n Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>,\n Neil Horman <nhorman@tuxdriver.com>", "Date": "Mon, 31 May 2021 23:41:17 +0200", "Message-ID": "<20210531214142.30167-4-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210531214142.30167-1-tduszynski@marvell.com>", "References": "<20210531214142.30167-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "qt32av-jSSHnSPrsmYcoTSlJPUNtpG4H", "X-Proofpoint-ORIG-GUID": "qt32av-jSSHnSPrsmYcoTSlJPUNtpG4H", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-05-31_15:2021-05-31,\n 2021-05-31 signatures=0", "Subject": "[dpdk-dev] [PATCH 03/28] common/cnxk: add support for getting link\n information", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for retrieving link information.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\nSigned-off-by: Jakub Palider <jpalider@marvell.com>\n---\n drivers/common/cnxk/roc_bphy_cgx.c | 38 ++++++++++++++\n drivers/common/cnxk/roc_bphy_cgx.h | 70 +++++++++++++++++++++++++\n drivers/common/cnxk/roc_bphy_cgx_priv.h | 9 ++++\n drivers/common/cnxk/version.map | 1 +\n 4 files changed, 118 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c\nindex 5048a90de..c7ba53ede 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx.c\n+++ b/drivers/common/cnxk/roc_bphy_cgx.c\n@@ -205,3 +205,41 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)\n \n \treturn 0;\n }\n+\n+static bool\n+roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)\n+{\n+\treturn (lmac < MAX_LMACS_PER_CGX) &&\n+\t (roc_cgx->lmac_bmap & BIT_ULL(lmac));\n+}\n+\n+int\n+roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n+\t\t\t struct roc_bphy_cgx_link_info *info)\n+{\n+\tuint64_t scr1, scr0;\n+\tint ret;\n+\n+\tif (!roc_cgx)\n+\t\treturn -EINVAL;\n+\n+\tif (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))\n+\t\treturn -EINVAL;\n+\n+\tif (!info)\n+\t\treturn -EINVAL;\n+\n+\tscr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_LINK_STS);\n+\tret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tinfo->link_up = FIELD_GET(SCR0_ETH_LNK_STS_S_LINK_UP, scr0);\n+\tinfo->full_duplex = FIELD_GET(SCR0_ETH_LNK_STS_S_FULL_DUPLEX, scr0);\n+\tinfo->speed = FIELD_GET(SCR0_ETH_LNK_STS_S_SPEED, scr0);\n+\tinfo->an = FIELD_GET(SCR0_ETH_LNK_STS_S_AN, scr0);\n+\tinfo->fec = FIELD_GET(SCR0_ETH_LNK_STS_S_FEC, scr0);\n+\tinfo->mode = FIELD_GET(SCR0_ETH_LNK_STS_S_MODE, scr0);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h\nindex 37b5c2742..bb1d903eb 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx.h\n+++ b/drivers/common/cnxk/roc_bphy_cgx.h\n@@ -9,6 +9,8 @@\n \n #include \"roc_api.h\"\n \n+#define MAX_LMACS_PER_CGX 4\n+\n struct roc_bphy_cgx {\n \tuint64_t bar0_pa;\n \tvoid *bar0_va;\n@@ -18,7 +20,75 @@ struct roc_bphy_cgx {\n \tpthread_mutex_t lock;\n } __plt_cache_aligned;\n \n+enum roc_bphy_cgx_eth_link_speed {\n+\tROC_BPHY_CGX_ETH_LINK_SPEED_NONE,\n+\tROC_BPHY_CGX_ETH_LINK_SPEED_10M,\n+\tROC_BPHY_CGX_ETH_LINK_SPEED_100M,\n+\tROC_BPHY_CGX_ETH_LINK_SPEED_1G,\n+\tROC_BPHY_CGX_ETH_LINK_SPEED_2HG,\n+\tROC_BPHY_CGX_ETH_LINK_SPEED_5G,\n+\tROC_BPHY_CGX_ETH_LINK_SPEED_10G,\n+\tROC_BPHY_CGX_ETH_LINK_SPEED_20G,\n+\tROC_BPHY_CGX_ETH_LINK_SPEED_25G,\n+\tROC_BPHY_CGX_ETH_LINK_SPEED_40G,\n+\tROC_BPHY_CGX_ETH_LINK_SPEED_50G,\n+\tROC_BPHY_CGX_ETH_LINK_SPEED_80G,\n+\tROC_BPHY_CGX_ETH_LINK_SPEED_100G,\n+\t__MAX_ROC_BPHY_CGX_ETH_LINK_SPEED\n+};\n+\n+enum roc_bphy_cgx_eth_link_fec {\n+\tROC_BPHY_CGX_ETH_LINK_FEC_NONE,\n+\tROC_BPHY_CGX_ETH_LINK_FEC_BASE_R,\n+\tROC_BPHY_CGX_ETH_LINK_FEC_RS,\n+\t__MAX_ROC_BPHY_CGX_ETH_LINK_FEC\n+};\n+\n+enum roc_bphy_cgx_eth_link_mode {\n+\tROC_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,\n+\t__MAX_ROC_BPHY_CGX_ETH_LINK_MODE\n+};\n+\n+struct roc_bphy_cgx_link_info {\n+\tbool link_up;\n+\tbool full_duplex;\n+\tenum roc_bphy_cgx_eth_link_speed speed;\n+\tbool an;\n+\tenum roc_bphy_cgx_eth_link_fec fec;\n+\tenum roc_bphy_cgx_eth_link_mode mode;\n+};\n+\n __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);\n __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);\n \n+__roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,\n+\t\t\t\t\tunsigned int lmac,\n+\t\t\t\t\tstruct roc_bphy_cgx_link_info *info);\n+\n #endif /* _ROC_BPHY_CGX_H_ */\ndiff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h\nindex 42d0bce7a..c0550ae87 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h\n+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h\n@@ -7,6 +7,7 @@\n \n /* REQUEST ID types. Input to firmware */\n enum eth_cmd_id {\n+\tETH_CMD_GET_LINK_STS = 4,\n \tETH_CMD_INTF_SHUTDOWN = 12,\n };\n \n@@ -41,6 +42,14 @@ enum eth_cmd_own {\n \n /* struct eth_lnk_sts_s */\n #define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15)\n+#define SCR0_ETH_LNK_STS_S_LINK_UP BIT_ULL(9)\n+#define SCR0_ETH_LNK_STS_S_FULL_DUPLEX BIT_ULL(10)\n+#define SCR0_ETH_LNK_STS_S_SPEED GENMASK_ULL(14, 11)\n+#define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15)\n+#define SCR0_ETH_LNK_STS_S_AN\t BIT_ULL(25)\n+#define SCR0_ETH_LNK_STS_S_FEC\t GENMASK_ULL(27, 26)\n+#define SCR0_ETH_LNK_STS_S_LMAC_TYPE GENMASK_ULL(35, 28)\n+#define SCR0_ETH_LNK_STS_S_MODE\t GENMASK_ULL(43, 36)\n \n /* scratchx(1) CSR used for non-secure SW->ATF communication\n * This CSR acts as a command register\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 1db4d104a..466207f9d 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -11,6 +11,7 @@ INTERNAL {\n \tcnxk_logtype_tm;\n \troc_bphy_cgx_dev_fini;\n \troc_bphy_cgx_dev_init;\n+\troc_bphy_cgx_get_linkinfo;\n \troc_clk_freq_get;\n \troc_error_msg_get;\n \troc_idev_lmt_base_addr_get;\n", "prefixes": [ "03/28" ] }