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{
    "id": 93583,
    "url": "http://patches.dpdk.org/api/patches/93583/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210530085929.29695-38-venkatkumar.duvvuru@broadcom.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210530085929.29695-38-venkatkumar.duvvuru@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210530085929.29695-38-venkatkumar.duvvuru@broadcom.com",
    "date": "2021-05-30T08:59:08",
    "name": "[37/58] net/bnxt: modify ULP template",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "f983cafacd9ece9e3b9610a94f3c52571a3e0940",
    "submitter": {
        "id": 1635,
        "url": "http://patches.dpdk.org/api/people/1635/?format=api",
        "name": "Venkat Duvvuru",
        "email": "venkatkumar.duvvuru@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "http://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210530085929.29695-38-venkatkumar.duvvuru@broadcom.com/mbox/",
    "series": [
        {
            "id": 17161,
            "url": "http://patches.dpdk.org/api/series/17161/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17161",
            "date": "2021-05-30T08:58:31",
            "name": "enhancements to host based flow table management",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/17161/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/93583/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/93583/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2BF42A0524;\n\tSun, 30 May 2021 11:05:30 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 36697411D3;\n\tSun, 30 May 2021 11:01:34 +0200 (CEST)",
            "from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com\n [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id C6CE8411D6\n for <dev@dpdk.org>; Sun, 30 May 2021 11:01:30 +0200 (CEST)",
            "from S60.dhcp.broadcom.net (unknown [10.123.66.170])\n (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n (No client certificate requested)\n by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 614587DAF;\n Sun, 30 May 2021 02:01:29 -0700 (PDT)"
        ],
        "DKIM-Filter": "OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 614587DAF",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n s=dkimrelay; t=1622365290;\n bh=1SIm1JJQaF4m3Quz+aVIA51E4NaqThXqfbn/Oy4TAYg=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=YmxFoBPmIAtscXVFb5xbQZC6SNNctJslwawWhiH1JAseyO4yIQuT0YNwNhwabCn8E\n V7yYz3E6VYJJSgsyxWmIxn3JrJp21suMOJvvyI4M0qDRCTfS8UCrfmPSkVA1Lba8Oi\n M7AACWpK6mMbcs6+qfGCF9t3ZpeELW7DpHLdUiDk=",
        "From": "Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "Kishore Padmanabha <kishore.padmanabha@broadcom.com>,\n Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "Date": "Sun, 30 May 2021 14:29:08 +0530",
        "Message-Id": "<20210530085929.29695-38-venkatkumar.duvvuru@broadcom.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com>",
        "References": "<20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com>",
        "Subject": "[dpdk-dev] [PATCH 37/58] net/bnxt: modify ULP template",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\n\n1. Update template to add both ipv4 and ipv6 flows.\n2. The VF representor template missed generic table read.\n\nSigned-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\nReviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>\nReviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>\nReviewed-by: Michael Baucom <michael.baucom@broadcom.com>\n---\n .../net/bnxt/tf_ulp/ulp_template_db_class.c   | 3224 ++++-------------\n .../net/bnxt/tf_ulp/ulp_template_db_enum.h    |  272 +-\n .../net/bnxt/tf_ulp/ulp_template_db_field.h   |  194 +-\n drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c |  202 +-\n .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c |   72 +-\n .../tf_ulp/ulp_template_db_wh_plus_class.c    | 2163 +++++++++--\n 6 files changed, 2946 insertions(+), 3181 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c\nindex a5133f7caf..3197ed2072 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Tue Dec  1 11:40:24 2020 */\n+/* date: Mon Dec  7 09:51:03 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -16,1800 +16,571 @@\n  * maps hash id to ulp_class_match_list[] index\n  */\n uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {\n-\t[BNXT_ULP_CLASS_HID_07e0] = 1,\n-\t[BNXT_ULP_CLASS_HID_01dc] = 2,\n-\t[BNXT_ULP_CLASS_HID_006e] = 3,\n-\t[BNXT_ULP_CLASS_HID_025a] = 4,\n-\t[BNXT_ULP_CLASS_HID_0146] = 5,\n-\t[BNXT_ULP_CLASS_HID_0332] = 6,\n-\t[BNXT_ULP_CLASS_HID_01c4] = 7,\n-\t[BNXT_ULP_CLASS_HID_078a] = 8,\n-\t[BNXT_ULP_CLASS_HID_02ed] = 9,\n-\t[BNXT_ULP_CLASS_HID_04d9] = 10,\n-\t[BNXT_ULP_CLASS_HID_036b] = 11,\n-\t[BNXT_ULP_CLASS_HID_0131] = 12,\n-\t[BNXT_ULP_CLASS_HID_0217] = 13,\n-\t[BNXT_ULP_CLASS_HID_03c3] = 14,\n-\t[BNXT_ULP_CLASS_HID_0295] = 15,\n-\t[BNXT_ULP_CLASS_HID_0441] = 16,\n-\t[BNXT_ULP_CLASS_HID_0095] = 17,\n-\t[BNXT_ULP_CLASS_HID_0241] = 18,\n-\t[BNXT_ULP_CLASS_HID_04ed] = 19,\n-\t[BNXT_ULP_CLASS_HID_06d9] = 20,\n-\t[BNXT_ULP_CLASS_HID_07bf] = 21,\n-\t[BNXT_ULP_CLASS_HID_016b] = 22,\n-\t[BNXT_ULP_CLASS_HID_0417] = 23,\n-\t[BNXT_ULP_CLASS_HID_05c3] = 24,\n-\t[BNXT_ULP_CLASS_HID_0187] = 25,\n-\t[BNXT_ULP_CLASS_HID_0373] = 26,\n-\t[BNXT_ULP_CLASS_HID_0205] = 27,\n-\t[BNXT_ULP_CLASS_HID_03f1] = 28,\n-\t[BNXT_ULP_CLASS_HID_00a1] = 29,\n-\t[BNXT_ULP_CLASS_HID_029d] = 30,\n-\t[BNXT_ULP_CLASS_HID_012f] = 31,\n-\t[BNXT_ULP_CLASS_HID_031b] = 32,\n-\t[BNXT_ULP_CLASS_HID_072f] = 33,\n-\t[BNXT_ULP_CLASS_HID_011b] = 34,\n-\t[BNXT_ULP_CLASS_HID_0387] = 35,\n-\t[BNXT_ULP_CLASS_HID_0573] = 36,\n-\t[BNXT_ULP_CLASS_HID_0649] = 37,\n-\t[BNXT_ULP_CLASS_HID_0005] = 38,\n-\t[BNXT_ULP_CLASS_HID_02a1] = 39,\n-\t[BNXT_ULP_CLASS_HID_049d] = 40,\n-\t[BNXT_ULP_CLASS_HID_01ea] = 41,\n-\t[BNXT_ULP_CLASS_HID_03de] = 42,\n-\t[BNXT_ULP_CLASS_HID_0672] = 43,\n-\t[BNXT_ULP_CLASS_HID_0026] = 44,\n-\t[BNXT_ULP_CLASS_HID_0746] = 45,\n-\t[BNXT_ULP_CLASS_HID_010a] = 46,\n-\t[BNXT_ULP_CLASS_HID_03ae] = 47,\n-\t[BNXT_ULP_CLASS_HID_0592] = 48,\n-\t[BNXT_ULP_CLASS_HID_07d0] = 49,\n-\t[BNXT_ULP_CLASS_HID_01ec] = 50,\n-\t[BNXT_ULP_CLASS_HID_005e] = 51,\n-\t[BNXT_ULP_CLASS_HID_026a] = 52,\n-\t[BNXT_ULP_CLASS_HID_0176] = 53,\n-\t[BNXT_ULP_CLASS_HID_0302] = 54,\n-\t[BNXT_ULP_CLASS_HID_01f4] = 55,\n-\t[BNXT_ULP_CLASS_HID_07ba] = 56,\n-\t[BNXT_ULP_CLASS_HID_06a7] = 57,\n-\t[BNXT_ULP_CLASS_HID_006b] = 58,\n-\t[BNXT_ULP_CLASS_HID_0725] = 59,\n-\t[BNXT_ULP_CLASS_HID_00e9] = 60,\n-\t[BNXT_ULP_CLASS_HID_05d9] = 61,\n-\t[BNXT_ULP_CLASS_HID_078d] = 62,\n-\t[BNXT_ULP_CLASS_HID_065f] = 63,\n-\t[BNXT_ULP_CLASS_HID_0003] = 64,\n-\t[BNXT_ULP_CLASS_HID_045f] = 65,\n-\t[BNXT_ULP_CLASS_HID_0603] = 66,\n-\t[BNXT_ULP_CLASS_HID_00a7] = 67,\n-\t[BNXT_ULP_CLASS_HID_026b] = 68,\n-\t[BNXT_ULP_CLASS_HID_0371] = 69,\n-\t[BNXT_ULP_CLASS_HID_0525] = 70,\n-\t[BNXT_ULP_CLASS_HID_07d9] = 71,\n-\t[BNXT_ULP_CLASS_HID_018d] = 72,\n-\t[BNXT_ULP_CLASS_HID_0177] = 73,\n-\t[BNXT_ULP_CLASS_HID_033b] = 74,\n-\t[BNXT_ULP_CLASS_HID_05df] = 75,\n-\t[BNXT_ULP_CLASS_HID_0783] = 76,\n-\t[BNXT_ULP_CLASS_HID_0069] = 77,\n-\t[BNXT_ULP_CLASS_HID_025d] = 78,\n-\t[BNXT_ULP_CLASS_HID_00ef] = 79,\n-\t[BNXT_ULP_CLASS_HID_06a5] = 80,\n-\t[BNXT_ULP_CLASS_HID_02f1] = 81,\n-\t[BNXT_ULP_CLASS_HID_04a5] = 82,\n-\t[BNXT_ULP_CLASS_HID_0377] = 83,\n-\t[BNXT_ULP_CLASS_HID_053b] = 84,\n-\t[BNXT_ULP_CLASS_HID_0601] = 85,\n-\t[BNXT_ULP_CLASS_HID_03df] = 86,\n-\t[BNXT_ULP_CLASS_HID_0269] = 87,\n-\t[BNXT_ULP_CLASS_HID_045d] = 88,\n-\t[BNXT_ULP_CLASS_HID_02dd] = 89,\n-\t[BNXT_ULP_CLASS_HID_04e9] = 90,\n-\t[BNXT_ULP_CLASS_HID_035b] = 91,\n-\t[BNXT_ULP_CLASS_HID_0101] = 92,\n-\t[BNXT_ULP_CLASS_HID_0227] = 93,\n-\t[BNXT_ULP_CLASS_HID_03f3] = 94,\n-\t[BNXT_ULP_CLASS_HID_02a5] = 95,\n-\t[BNXT_ULP_CLASS_HID_0471] = 96,\n-\t[BNXT_ULP_CLASS_HID_00a5] = 97,\n-\t[BNXT_ULP_CLASS_HID_0271] = 98,\n-\t[BNXT_ULP_CLASS_HID_04dd] = 99,\n-\t[BNXT_ULP_CLASS_HID_06e9] = 100,\n-\t[BNXT_ULP_CLASS_HID_078f] = 101,\n-\t[BNXT_ULP_CLASS_HID_015b] = 102,\n-\t[BNXT_ULP_CLASS_HID_0427] = 103,\n-\t[BNXT_ULP_CLASS_HID_05f3] = 104,\n-\t[BNXT_ULP_CLASS_HID_01b7] = 105,\n-\t[BNXT_ULP_CLASS_HID_0343] = 106,\n-\t[BNXT_ULP_CLASS_HID_0235] = 107,\n-\t[BNXT_ULP_CLASS_HID_03c1] = 108,\n-\t[BNXT_ULP_CLASS_HID_0091] = 109,\n-\t[BNXT_ULP_CLASS_HID_02ad] = 110,\n-\t[BNXT_ULP_CLASS_HID_011f] = 111,\n-\t[BNXT_ULP_CLASS_HID_032b] = 112,\n-\t[BNXT_ULP_CLASS_HID_071f] = 113,\n-\t[BNXT_ULP_CLASS_HID_012b] = 114,\n-\t[BNXT_ULP_CLASS_HID_03b7] = 115,\n-\t[BNXT_ULP_CLASS_HID_0543] = 116,\n-\t[BNXT_ULP_CLASS_HID_0679] = 117,\n-\t[BNXT_ULP_CLASS_HID_0035] = 118,\n-\t[BNXT_ULP_CLASS_HID_0291] = 119,\n-\t[BNXT_ULP_CLASS_HID_04ad] = 120,\n-\t[BNXT_ULP_CLASS_HID_01da] = 121,\n-\t[BNXT_ULP_CLASS_HID_03ee] = 122,\n-\t[BNXT_ULP_CLASS_HID_0642] = 123,\n-\t[BNXT_ULP_CLASS_HID_0016] = 124,\n-\t[BNXT_ULP_CLASS_HID_0776] = 125,\n-\t[BNXT_ULP_CLASS_HID_013a] = 126,\n-\t[BNXT_ULP_CLASS_HID_039e] = 127,\n-\t[BNXT_ULP_CLASS_HID_05a2] = 128,\n-\t[BNXT_ULP_CLASS_HID_0697] = 129,\n-\t[BNXT_ULP_CLASS_HID_005b] = 130,\n-\t[BNXT_ULP_CLASS_HID_0715] = 131,\n-\t[BNXT_ULP_CLASS_HID_00d9] = 132,\n-\t[BNXT_ULP_CLASS_HID_05e9] = 133,\n-\t[BNXT_ULP_CLASS_HID_07bd] = 134,\n-\t[BNXT_ULP_CLASS_HID_066f] = 135,\n-\t[BNXT_ULP_CLASS_HID_0033] = 136,\n-\t[BNXT_ULP_CLASS_HID_046f] = 137,\n-\t[BNXT_ULP_CLASS_HID_0633] = 138,\n-\t[BNXT_ULP_CLASS_HID_0097] = 139,\n-\t[BNXT_ULP_CLASS_HID_025b] = 140,\n-\t[BNXT_ULP_CLASS_HID_0341] = 141,\n-\t[BNXT_ULP_CLASS_HID_0515] = 142,\n-\t[BNXT_ULP_CLASS_HID_07e9] = 143,\n-\t[BNXT_ULP_CLASS_HID_01bd] = 144,\n-\t[BNXT_ULP_CLASS_HID_0147] = 145,\n-\t[BNXT_ULP_CLASS_HID_030b] = 146,\n-\t[BNXT_ULP_CLASS_HID_05ef] = 147,\n-\t[BNXT_ULP_CLASS_HID_07b3] = 148,\n-\t[BNXT_ULP_CLASS_HID_0059] = 149,\n-\t[BNXT_ULP_CLASS_HID_026d] = 150,\n-\t[BNXT_ULP_CLASS_HID_00df] = 151,\n-\t[BNXT_ULP_CLASS_HID_0695] = 152,\n-\t[BNXT_ULP_CLASS_HID_02c1] = 153,\n-\t[BNXT_ULP_CLASS_HID_0495] = 154,\n-\t[BNXT_ULP_CLASS_HID_0347] = 155,\n-\t[BNXT_ULP_CLASS_HID_050b] = 156,\n-\t[BNXT_ULP_CLASS_HID_0631] = 157,\n-\t[BNXT_ULP_CLASS_HID_03ef] = 158,\n-\t[BNXT_ULP_CLASS_HID_0259] = 159,\n-\t[BNXT_ULP_CLASS_HID_046d] = 160\n+\t[BNXT_ULP_CLASS_HID_005c] = 1,\n+\t[BNXT_ULP_CLASS_HID_0003] = 2,\n+\t[BNXT_ULP_CLASS_HID_0132] = 3,\n+\t[BNXT_ULP_CLASS_HID_00e1] = 4,\n+\t[BNXT_ULP_CLASS_HID_0044] = 5,\n+\t[BNXT_ULP_CLASS_HID_001b] = 6,\n+\t[BNXT_ULP_CLASS_HID_012a] = 7,\n+\t[BNXT_ULP_CLASS_HID_00f9] = 8,\n+\t[BNXT_ULP_CLASS_HID_018d] = 9,\n+\t[BNXT_ULP_CLASS_HID_00a7] = 10,\n+\t[BNXT_ULP_CLASS_HID_006f] = 11,\n+\t[BNXT_ULP_CLASS_HID_0181] = 12,\n+\t[BNXT_ULP_CLASS_HID_0195] = 13,\n+\t[BNXT_ULP_CLASS_HID_00bf] = 14,\n+\t[BNXT_ULP_CLASS_HID_0077] = 15,\n+\t[BNXT_ULP_CLASS_HID_0199] = 16,\n+\t[BNXT_ULP_CLASS_HID_009a] = 17,\n+\t[BNXT_ULP_CLASS_HID_0192] = 18,\n+\t[BNXT_ULP_CLASS_HID_01e2] = 19,\n+\t[BNXT_ULP_CLASS_HID_00fa] = 20,\n+\t[BNXT_ULP_CLASS_HID_0165] = 21,\n+\t[BNXT_ULP_CLASS_HID_0042] = 22,\n+\t[BNXT_ULP_CLASS_HID_00cd] = 23,\n+\t[BNXT_ULP_CLASS_HID_01aa] = 24,\n+\t[BNXT_ULP_CLASS_HID_0178] = 25,\n+\t[BNXT_ULP_CLASS_HID_0070] = 26,\n+\t[BNXT_ULP_CLASS_HID_00f3] = 27,\n+\t[BNXT_ULP_CLASS_HID_01d8] = 28,\n+\t[BNXT_ULP_CLASS_HID_005b] = 29,\n+\t[BNXT_ULP_CLASS_HID_0153] = 30,\n+\t[BNXT_ULP_CLASS_HID_01a3] = 31,\n+\t[BNXT_ULP_CLASS_HID_00bb] = 32,\n+\t[BNXT_ULP_CLASS_HID_0082] = 33,\n+\t[BNXT_ULP_CLASS_HID_018a] = 34,\n+\t[BNXT_ULP_CLASS_HID_01fa] = 35,\n+\t[BNXT_ULP_CLASS_HID_00e2] = 36,\n+\t[BNXT_ULP_CLASS_HID_017d] = 37,\n+\t[BNXT_ULP_CLASS_HID_005a] = 38,\n+\t[BNXT_ULP_CLASS_HID_00d5] = 39,\n+\t[BNXT_ULP_CLASS_HID_01b2] = 40,\n+\t[BNXT_ULP_CLASS_HID_0160] = 41,\n+\t[BNXT_ULP_CLASS_HID_0068] = 42,\n+\t[BNXT_ULP_CLASS_HID_00eb] = 43,\n+\t[BNXT_ULP_CLASS_HID_01c0] = 44,\n+\t[BNXT_ULP_CLASS_HID_0043] = 45,\n+\t[BNXT_ULP_CLASS_HID_014b] = 46,\n+\t[BNXT_ULP_CLASS_HID_01bb] = 47,\n+\t[BNXT_ULP_CLASS_HID_00a3] = 48,\n+\t[BNXT_ULP_CLASS_HID_00cb] = 49,\n+\t[BNXT_ULP_CLASS_HID_00b4] = 50,\n+\t[BNXT_ULP_CLASS_HID_0013] = 51,\n+\t[BNXT_ULP_CLASS_HID_001c] = 52,\n+\t[BNXT_ULP_CLASS_HID_017b] = 53,\n+\t[BNXT_ULP_CLASS_HID_0164] = 54,\n+\t[BNXT_ULP_CLASS_HID_00c3] = 55,\n+\t[BNXT_ULP_CLASS_HID_00cc] = 56,\n+\t[BNXT_ULP_CLASS_HID_01a5] = 57,\n+\t[BNXT_ULP_CLASS_HID_0196] = 58,\n+\t[BNXT_ULP_CLASS_HID_010d] = 59,\n+\t[BNXT_ULP_CLASS_HID_00fe] = 60,\n+\t[BNXT_ULP_CLASS_HID_0084] = 61,\n+\t[BNXT_ULP_CLASS_HID_0046] = 62,\n+\t[BNXT_ULP_CLASS_HID_01ec] = 63,\n+\t[BNXT_ULP_CLASS_HID_01ae] = 64,\n+\t[BNXT_ULP_CLASS_HID_00d3] = 65,\n+\t[BNXT_ULP_CLASS_HID_00ac] = 66,\n+\t[BNXT_ULP_CLASS_HID_000b] = 67,\n+\t[BNXT_ULP_CLASS_HID_0004] = 68,\n+\t[BNXT_ULP_CLASS_HID_0163] = 69,\n+\t[BNXT_ULP_CLASS_HID_017c] = 70,\n+\t[BNXT_ULP_CLASS_HID_00db] = 71,\n+\t[BNXT_ULP_CLASS_HID_00d4] = 72,\n+\t[BNXT_ULP_CLASS_HID_01bd] = 73,\n+\t[BNXT_ULP_CLASS_HID_018e] = 74,\n+\t[BNXT_ULP_CLASS_HID_0115] = 75,\n+\t[BNXT_ULP_CLASS_HID_00e6] = 76,\n+\t[BNXT_ULP_CLASS_HID_009c] = 77,\n+\t[BNXT_ULP_CLASS_HID_005e] = 78,\n+\t[BNXT_ULP_CLASS_HID_01f4] = 79,\n+\t[BNXT_ULP_CLASS_HID_01b6] = 80\n };\n \n /* Array for the proto matcher list */\n struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t[1] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_07e0,\n+\t.class_hid = BNXT_ULP_CLASS_HID_005c,\n \t.class_tid = 1,\n \t.hdr_sig_id = 0,\n \t.flow_sig_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[2] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01dc,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0003,\n \t.class_tid = 1,\n \t.hdr_sig_id = 0,\n \t.flow_sig_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[3] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_006e,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0132,\n \t.class_tid = 1,\n \t.hdr_sig_id = 0,\n-\t.flow_sig_id = 2,\n+\t.flow_sig_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[4] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_025a,\n+\t.class_hid = BNXT_ULP_CLASS_HID_00e1,\n \t.class_tid = 1,\n \t.hdr_sig_id = 0,\n-\t.flow_sig_id = 2,\n+\t.flow_sig_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[5] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0146,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0044,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 0,\n-\t.flow_sig_id = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[6] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0332,\n+\t.class_hid = BNXT_ULP_CLASS_HID_001b,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 0,\n+\t.hdr_sig_id = 1,\n \t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[7] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01c4,\n+\t.class_hid = BNXT_ULP_CLASS_HID_012a,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 0,\n+\t.hdr_sig_id = 1,\n \t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[8] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_078a,\n+\t.class_hid = BNXT_ULP_CLASS_HID_00f9,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 0,\n+\t.hdr_sig_id = 1,\n \t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[9] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_02ed,\n+\t.class_hid = BNXT_ULP_CLASS_HID_018d,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n+\t.hdr_sig_id = 2,\n \t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[10] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_04d9,\n+\t.class_hid = BNXT_ULP_CLASS_HID_00a7,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 3,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[11] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_036b,\n+\t.class_hid = BNXT_ULP_CLASS_HID_006f,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 3,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[12] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0131,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0181,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 3,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[13] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0217,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0195,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 3,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[14] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_03c3,\n+\t.class_hid = BNXT_ULP_CLASS_HID_00bf,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 3,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[15] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0295,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0077,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n+\t.hdr_sig_id = 3,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[16] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0441,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0199,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n+\t.hdr_sig_id = 3,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[17] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0095,\n+\t.class_hid = BNXT_ULP_CLASS_HID_009a,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n+\t.hdr_sig_id = 4,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[18] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0241,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0192,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n+\t.hdr_sig_id = 4,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[19] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_04ed,\n+\t.class_hid = BNXT_ULP_CLASS_HID_01e2,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n+\t.hdr_sig_id = 4,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[20] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_06d9,\n+\t.class_hid = BNXT_ULP_CLASS_HID_00fa,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n+\t.hdr_sig_id = 4,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[21] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_07bf,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0165,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n+\t.hdr_sig_id = 4,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[22] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_016b,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0042,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[23] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0417,\n+\t.class_hid = BNXT_ULP_CLASS_HID_00cd,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[24] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_05c3,\n+\t.class_hid = BNXT_ULP_CLASS_HID_01aa,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[25] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0187,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[26] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0373,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[27] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0205,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[28] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_03f1,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[29] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00a1,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[30] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_029d,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[31] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_012f,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[32] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_031b,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[33] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_072f,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[34] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_011b,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[35] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0387,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[36] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0573,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[37] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0649,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[38] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0005,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[39] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_02a1,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[40] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_049d,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[41] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01ea,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 4,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[42] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_03de,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 5,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[43] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0672,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 6,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[44] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0026,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 6,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[45] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0746,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 6,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[46] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_010a,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 6,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[47] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_03ae,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 6,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[48] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0592,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 6,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[49] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_07d0,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 3,\n-\t.flow_sig_id = 6,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[50] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01ec,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 3,\n-\t.flow_sig_id = 7,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[51] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_005e,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 3,\n-\t.flow_sig_id = 8,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[52] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_026a,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 3,\n-\t.flow_sig_id = 8,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[53] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0176,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 3,\n-\t.flow_sig_id = 8,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[54] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0302,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 3,\n-\t.flow_sig_id = 8,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[55] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01f4,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 3,\n-\t.flow_sig_id = 8,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[56] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_07ba,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 3,\n-\t.flow_sig_id = 8,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[57] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_06a7,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 8,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[58] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_006b,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 8,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[59] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0725,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 8,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[60] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00e9,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 8,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[61] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_05d9,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 8,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[62] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_078d,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 9,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[63] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_065f,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[64] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0003,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[65] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_045f,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[66] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0603,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[67] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00a7,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[68] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_026b,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[69] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0371,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[70] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0525,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[71] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_07d9,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[72] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_018d,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[73] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0177,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[74] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_033b,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[75] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_05df,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[76] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0783,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[77] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0069,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[78] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_025d,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[79] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00ef,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[80] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_06a5,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[81] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_02f1,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[82] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_04a5,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[83] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0377,\n+\t[25] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0178,\n \t.class_tid = 1,\n \t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n@@ -1817,8 +588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n@@ -1826,11 +596,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[84] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_053b,\n+\t[26] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0070,\n \t.class_tid = 1,\n \t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n@@ -1839,20 +609,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[85] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0601,\n+\t[27] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00f3,\n \t.class_tid = 1,\n \t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n@@ -1860,7 +627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n@@ -1869,11 +636,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[86] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_03df,\n+\t[28] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01d8,\n \t.class_tid = 1,\n \t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n@@ -1882,20 +649,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[87] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0269,\n+\t[29] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_005b,\n \t.class_tid = 1,\n \t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n@@ -1903,9 +668,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n@@ -1913,11 +677,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[88] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_045d,\n+\t[30] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0153,\n \t.class_tid = 1,\n \t.hdr_sig_id = 4,\n-\t.flow_sig_id = 10,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n@@ -1926,1472 +690,1060 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[89] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_02dd,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[90] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_04e9,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[91] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_035b,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[92] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0101,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[93] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0227,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 10,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[94] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_03f3,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 11,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[95] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_02a5,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[96] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0471,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[97] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00a5,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[98] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0271,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[99] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_04dd,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[100] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_06e9,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[101] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_078f,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[102] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_015b,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[103] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0427,\n+\t[31] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01a3,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[104] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_05f3,\n+\t[32] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00bb,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[105] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01b7,\n+\t[33] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0082,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[106] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0343,\n+\t[34] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_018a,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[107] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0235,\n+\t[35] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01fa,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[108] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_03c1,\n+\t[36] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00e2,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[109] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0091,\n+\t[37] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_017d,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 5,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[110] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_02ad,\n+\t[38] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_005a,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[111] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_011f,\n+\t[39] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00d5,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[112] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_032b,\n+\t[40] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01b2,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[113] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_071f,\n+\t[41] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0160,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[114] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_012b,\n+\t[42] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0068,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[115] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_03b7,\n+\t[43] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00eb,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[116] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0543,\n+\t[44] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01c0,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[117] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0679,\n+\t[45] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0043,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[118] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0035,\n+\t[46] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_014b,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[119] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0291,\n+\t[47] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01bb,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[120] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_04ad,\n+\t[48] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00a3,\n \t.class_tid = 1,\n \t.hdr_sig_id = 5,\n-\t.flow_sig_id = 12,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[121] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01da,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 12,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[122] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_03ee,\n+\t[49] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00cb,\n \t.class_tid = 1,\n \t.hdr_sig_id = 6,\n-\t.flow_sig_id = 13,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[123] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0642,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 14,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[124] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0016,\n+\t[50] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00b4,\n \t.class_tid = 1,\n \t.hdr_sig_id = 6,\n-\t.flow_sig_id = 14,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[125] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0776,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 14,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[126] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_013a,\n+\t[51] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0013,\n \t.class_tid = 1,\n \t.hdr_sig_id = 6,\n-\t.flow_sig_id = 14,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[127] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_039e,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 14,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[128] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_05a2,\n+\t[52] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_001c,\n \t.class_tid = 1,\n \t.hdr_sig_id = 6,\n-\t.flow_sig_id = 14,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[129] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0697,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 14,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[130] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_005b,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 14,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[131] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0715,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 14,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[132] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00d9,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 14,\n-\t.hdr_sig = { .bits =\n-\t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n-\t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n-\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n-\t},\n-\t[133] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_05e9,\n+\t[53] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_017b,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 14,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 6,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[134] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_07bd,\n+\t[54] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0164,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 15,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[135] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_066f,\n+\t[55] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00c3,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[136] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0033,\n+\t[56] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00cc,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[137] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_046f,\n+\t[57] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01a5,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[138] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0633,\n+\t[58] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0196,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[139] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0097,\n+\t[59] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_010d,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[140] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_025b,\n+\t[60] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00fe,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[141] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0341,\n+\t[61] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0084,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[142] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0515,\n+\t[62] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0046,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[143] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_07e9,\n+\t[63] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01ec,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[144] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01bd,\n+\t[64] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01ae,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[145] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0147,\n+\t[65] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00d3,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[146] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_030b,\n+\t[66] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00ac,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[147] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_05ef,\n+\t[67] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_000b,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[148] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_07b3,\n+\t[68] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0004,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[149] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0059,\n+\t[69] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0163,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 7,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[150] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_026d,\n+\t[70] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_017c,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 8,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[151] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00df,\n+\t[71] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00db,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 8,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[152] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0695,\n+\t[72] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00d4,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 8,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[153] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_02c1,\n+\t[73] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01bd,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 8,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[154] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0495,\n+\t[74] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_018e,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 8,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[155] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0347,\n+\t[75] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0115,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 8,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[156] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_050b,\n+\t[76] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00e6,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 8,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[157] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0631,\n+\t[77] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_009c,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 8,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[158] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_03ef,\n+\t[78] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_005e,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 8,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[159] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0259,\n+\t[79] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01f4,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 8,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[160] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_046d,\n+\t[80] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01b6,\n \t.class_tid = 1,\n \t.hdr_sig_id = 7,\n-\t.flow_sig_id = 16,\n+\t.flow_sig_id = 8,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h\nindex fc342bef0a..0bae79fe03 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h\n@@ -3,22 +3,22 @@\n  * All rights reserved.\n  */\n \n-/* date: Tue Dec  1 10:17:11 2020 */\n+/* date: Fri Dec  4 18:49:44 2020 */\n \n #ifndef ULP_TEMPLATE_DB_H_\n #define ULP_TEMPLATE_DB_H_\n \n-#define BNXT_ULP_REGFILE_MAX_SZ 31\n+#define BNXT_ULP_REGFILE_MAX_SZ 32\n #define BNXT_ULP_MAX_NUM_DEVICES 4\n #define BNXT_ULP_LOG2_MAX_NUM_DEV 2\n #define BNXT_ULP_GEN_TBL_MAX_SZ 6\n-#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048\n-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 161\n-#define BNXT_ULP_CLASS_HID_LOW_PRIME 7669\n+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 512\n+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 81\n+#define BNXT_ULP_CLASS_HID_LOW_PRIME 4049\n #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919\n-#define BNXT_ULP_CLASS_HID_SHFTR 24\n+#define BNXT_ULP_CLASS_HID_SHFTR 25\n #define BNXT_ULP_CLASS_HID_SHFTL 23\n-#define BNXT_ULP_CLASS_HID_MASK 2047\n+#define BNXT_ULP_CLASS_HID_MASK 511\n #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048\n #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 15\n #define BNXT_ULP_ACT_HID_LOW_PRIME 7919\n@@ -32,11 +32,11 @@\n #define BNXT_ULP_HDR_SIG_ID_SHIFT 4\n #define BNXT_ULP_GLB_FIELD_TBL_SIZE 3033\n #define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 7\n-#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 38\n-#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 192\n-#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 10\n-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 341\n-#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 10\n+#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 41\n+#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 257\n+#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 11\n+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 367\n+#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 14\n #define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 7\n #define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 38\n #define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 192\n@@ -48,7 +48,7 @@\n #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 0\n #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 0\n #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 65\n-#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 2\n+#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 11\n #define ULP_STINGRAY_ACT_TMPL_LIST_SIZE 2\n #define ULP_STINGRAY_ACT_TBL_LIST_SIZE 4\n #define ULP_STINGRAY_ACT_KEY_INFO_LIST_SIZE 0\n@@ -248,7 +248,8 @@ enum bnxt_ulp_field_cond_src {\n \tBNXT_ULP_FIELD_COND_SRC_ACT_BIT = 3,\n \tBNXT_ULP_FIELD_COND_SRC_HDR_BIT = 4,\n \tBNXT_ULP_FIELD_COND_SRC_FIELD_BIT = 5,\n-\tBNXT_ULP_FIELD_COND_SRC_LAST = 6\n+\tBNXT_ULP_FIELD_COND_SRC_SRC1_PLUS_SRC2 = 6,\n+\tBNXT_ULP_FIELD_COND_SRC_LAST = 7\n };\n \n enum bnxt_ulp_field_src {\n@@ -368,10 +369,11 @@ enum bnxt_ulp_rf_idx {\n \tBNXT_ULP_RF_IDX_SRC_PROPERTY_PTR = 25,\n \tBNXT_ULP_RF_IDX_GENERIC_TBL_HIT = 26,\n \tBNXT_ULP_RF_IDX_MIRROR_PTR_0 = 27,\n-\tBNXT_ULP_RF_IDX_HDR_SIG_ID = 28,\n-\tBNXT_ULP_RF_IDX_FLOW_SIG_ID = 29,\n-\tBNXT_ULP_RF_IDX_RID = 30,\n-\tBNXT_ULP_RF_IDX_LAST = 31\n+\tBNXT_ULP_RF_IDX_MIRROR_ID_0 = 28,\n+\tBNXT_ULP_RF_IDX_HDR_SIG_ID = 29,\n+\tBNXT_ULP_RF_IDX_FLOW_SIG_ID = 30,\n+\tBNXT_ULP_RF_IDX_RID = 31,\n+\tBNXT_ULP_RF_IDX_LAST = 32\n };\n \n enum bnxt_ulp_tcam_tbl_opc {\n@@ -427,7 +429,7 @@ enum bnxt_ulp_resource_sub_type {\n \tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT = 4,\n \tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM = 0,\n \tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1,\n-\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL = 2\n+\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2\n };\n \n enum bnxt_ulp_act_prop_sz {\n@@ -959,166 +961,86 @@ enum ulp_sr_sym {\n };\n \n enum bnxt_ulp_class_hid {\n-\tBNXT_ULP_CLASS_HID_07e0 = 0x07e0,\n-\tBNXT_ULP_CLASS_HID_01dc = 0x01dc,\n-\tBNXT_ULP_CLASS_HID_006e = 0x006e,\n-\tBNXT_ULP_CLASS_HID_025a = 0x025a,\n-\tBNXT_ULP_CLASS_HID_0146 = 0x0146,\n-\tBNXT_ULP_CLASS_HID_0332 = 0x0332,\n-\tBNXT_ULP_CLASS_HID_01c4 = 0x01c4,\n-\tBNXT_ULP_CLASS_HID_078a = 0x078a,\n-\tBNXT_ULP_CLASS_HID_02ed = 0x02ed,\n-\tBNXT_ULP_CLASS_HID_04d9 = 0x04d9,\n-\tBNXT_ULP_CLASS_HID_036b = 0x036b,\n-\tBNXT_ULP_CLASS_HID_0131 = 0x0131,\n-\tBNXT_ULP_CLASS_HID_0217 = 0x0217,\n-\tBNXT_ULP_CLASS_HID_03c3 = 0x03c3,\n-\tBNXT_ULP_CLASS_HID_0295 = 0x0295,\n-\tBNXT_ULP_CLASS_HID_0441 = 0x0441,\n-\tBNXT_ULP_CLASS_HID_0095 = 0x0095,\n-\tBNXT_ULP_CLASS_HID_0241 = 0x0241,\n-\tBNXT_ULP_CLASS_HID_04ed = 0x04ed,\n-\tBNXT_ULP_CLASS_HID_06d9 = 0x06d9,\n-\tBNXT_ULP_CLASS_HID_07bf = 0x07bf,\n-\tBNXT_ULP_CLASS_HID_016b = 0x016b,\n-\tBNXT_ULP_CLASS_HID_0417 = 0x0417,\n-\tBNXT_ULP_CLASS_HID_05c3 = 0x05c3,\n-\tBNXT_ULP_CLASS_HID_0187 = 0x0187,\n-\tBNXT_ULP_CLASS_HID_0373 = 0x0373,\n-\tBNXT_ULP_CLASS_HID_0205 = 0x0205,\n-\tBNXT_ULP_CLASS_HID_03f1 = 0x03f1,\n-\tBNXT_ULP_CLASS_HID_00a1 = 0x00a1,\n-\tBNXT_ULP_CLASS_HID_029d = 0x029d,\n-\tBNXT_ULP_CLASS_HID_012f = 0x012f,\n-\tBNXT_ULP_CLASS_HID_031b = 0x031b,\n-\tBNXT_ULP_CLASS_HID_072f = 0x072f,\n-\tBNXT_ULP_CLASS_HID_011b = 0x011b,\n-\tBNXT_ULP_CLASS_HID_0387 = 0x0387,\n-\tBNXT_ULP_CLASS_HID_0573 = 0x0573,\n-\tBNXT_ULP_CLASS_HID_0649 = 0x0649,\n-\tBNXT_ULP_CLASS_HID_0005 = 0x0005,\n-\tBNXT_ULP_CLASS_HID_02a1 = 0x02a1,\n-\tBNXT_ULP_CLASS_HID_049d = 0x049d,\n-\tBNXT_ULP_CLASS_HID_01ea = 0x01ea,\n-\tBNXT_ULP_CLASS_HID_03de = 0x03de,\n-\tBNXT_ULP_CLASS_HID_0672 = 0x0672,\n-\tBNXT_ULP_CLASS_HID_0026 = 0x0026,\n-\tBNXT_ULP_CLASS_HID_0746 = 0x0746,\n-\tBNXT_ULP_CLASS_HID_010a = 0x010a,\n-\tBNXT_ULP_CLASS_HID_03ae = 0x03ae,\n-\tBNXT_ULP_CLASS_HID_0592 = 0x0592,\n-\tBNXT_ULP_CLASS_HID_07d0 = 0x07d0,\n-\tBNXT_ULP_CLASS_HID_01ec = 0x01ec,\n-\tBNXT_ULP_CLASS_HID_005e = 0x005e,\n-\tBNXT_ULP_CLASS_HID_026a = 0x026a,\n-\tBNXT_ULP_CLASS_HID_0176 = 0x0176,\n-\tBNXT_ULP_CLASS_HID_0302 = 0x0302,\n-\tBNXT_ULP_CLASS_HID_01f4 = 0x01f4,\n-\tBNXT_ULP_CLASS_HID_07ba = 0x07ba,\n-\tBNXT_ULP_CLASS_HID_06a7 = 0x06a7,\n-\tBNXT_ULP_CLASS_HID_006b = 0x006b,\n-\tBNXT_ULP_CLASS_HID_0725 = 0x0725,\n-\tBNXT_ULP_CLASS_HID_00e9 = 0x00e9,\n-\tBNXT_ULP_CLASS_HID_05d9 = 0x05d9,\n-\tBNXT_ULP_CLASS_HID_078d = 0x078d,\n-\tBNXT_ULP_CLASS_HID_065f = 0x065f,\n+\tBNXT_ULP_CLASS_HID_005c = 0x005c,\n \tBNXT_ULP_CLASS_HID_0003 = 0x0003,\n-\tBNXT_ULP_CLASS_HID_045f = 0x045f,\n-\tBNXT_ULP_CLASS_HID_0603 = 0x0603,\n-\tBNXT_ULP_CLASS_HID_00a7 = 0x00a7,\n-\tBNXT_ULP_CLASS_HID_026b = 0x026b,\n-\tBNXT_ULP_CLASS_HID_0371 = 0x0371,\n-\tBNXT_ULP_CLASS_HID_0525 = 0x0525,\n-\tBNXT_ULP_CLASS_HID_07d9 = 0x07d9,\n+\tBNXT_ULP_CLASS_HID_0132 = 0x0132,\n+\tBNXT_ULP_CLASS_HID_00e1 = 0x00e1,\n+\tBNXT_ULP_CLASS_HID_0044 = 0x0044,\n+\tBNXT_ULP_CLASS_HID_001b = 0x001b,\n+\tBNXT_ULP_CLASS_HID_012a = 0x012a,\n+\tBNXT_ULP_CLASS_HID_00f9 = 0x00f9,\n \tBNXT_ULP_CLASS_HID_018d = 0x018d,\n-\tBNXT_ULP_CLASS_HID_0177 = 0x0177,\n-\tBNXT_ULP_CLASS_HID_033b = 0x033b,\n-\tBNXT_ULP_CLASS_HID_05df = 0x05df,\n-\tBNXT_ULP_CLASS_HID_0783 = 0x0783,\n-\tBNXT_ULP_CLASS_HID_0069 = 0x0069,\n-\tBNXT_ULP_CLASS_HID_025d = 0x025d,\n-\tBNXT_ULP_CLASS_HID_00ef = 0x00ef,\n-\tBNXT_ULP_CLASS_HID_06a5 = 0x06a5,\n-\tBNXT_ULP_CLASS_HID_02f1 = 0x02f1,\n-\tBNXT_ULP_CLASS_HID_04a5 = 0x04a5,\n-\tBNXT_ULP_CLASS_HID_0377 = 0x0377,\n-\tBNXT_ULP_CLASS_HID_053b = 0x053b,\n-\tBNXT_ULP_CLASS_HID_0601 = 0x0601,\n-\tBNXT_ULP_CLASS_HID_03df = 0x03df,\n-\tBNXT_ULP_CLASS_HID_0269 = 0x0269,\n-\tBNXT_ULP_CLASS_HID_045d = 0x045d,\n-\tBNXT_ULP_CLASS_HID_02dd = 0x02dd,\n-\tBNXT_ULP_CLASS_HID_04e9 = 0x04e9,\n-\tBNXT_ULP_CLASS_HID_035b = 0x035b,\n-\tBNXT_ULP_CLASS_HID_0101 = 0x0101,\n-\tBNXT_ULP_CLASS_HID_0227 = 0x0227,\n-\tBNXT_ULP_CLASS_HID_03f3 = 0x03f3,\n-\tBNXT_ULP_CLASS_HID_02a5 = 0x02a5,\n-\tBNXT_ULP_CLASS_HID_0471 = 0x0471,\n-\tBNXT_ULP_CLASS_HID_00a5 = 0x00a5,\n-\tBNXT_ULP_CLASS_HID_0271 = 0x0271,\n-\tBNXT_ULP_CLASS_HID_04dd = 0x04dd,\n-\tBNXT_ULP_CLASS_HID_06e9 = 0x06e9,\n-\tBNXT_ULP_CLASS_HID_078f = 0x078f,\n-\tBNXT_ULP_CLASS_HID_015b = 0x015b,\n-\tBNXT_ULP_CLASS_HID_0427 = 0x0427,\n-\tBNXT_ULP_CLASS_HID_05f3 = 0x05f3,\n-\tBNXT_ULP_CLASS_HID_01b7 = 0x01b7,\n-\tBNXT_ULP_CLASS_HID_0343 = 0x0343,\n-\tBNXT_ULP_CLASS_HID_0235 = 0x0235,\n-\tBNXT_ULP_CLASS_HID_03c1 = 0x03c1,\n-\tBNXT_ULP_CLASS_HID_0091 = 0x0091,\n-\tBNXT_ULP_CLASS_HID_02ad = 0x02ad,\n-\tBNXT_ULP_CLASS_HID_011f = 0x011f,\n-\tBNXT_ULP_CLASS_HID_032b = 0x032b,\n-\tBNXT_ULP_CLASS_HID_071f = 0x071f,\n-\tBNXT_ULP_CLASS_HID_012b = 0x012b,\n-\tBNXT_ULP_CLASS_HID_03b7 = 0x03b7,\n-\tBNXT_ULP_CLASS_HID_0543 = 0x0543,\n-\tBNXT_ULP_CLASS_HID_0679 = 0x0679,\n-\tBNXT_ULP_CLASS_HID_0035 = 0x0035,\n-\tBNXT_ULP_CLASS_HID_0291 = 0x0291,\n-\tBNXT_ULP_CLASS_HID_04ad = 0x04ad,\n-\tBNXT_ULP_CLASS_HID_01da = 0x01da,\n-\tBNXT_ULP_CLASS_HID_03ee = 0x03ee,\n-\tBNXT_ULP_CLASS_HID_0642 = 0x0642,\n-\tBNXT_ULP_CLASS_HID_0016 = 0x0016,\n-\tBNXT_ULP_CLASS_HID_0776 = 0x0776,\n-\tBNXT_ULP_CLASS_HID_013a = 0x013a,\n-\tBNXT_ULP_CLASS_HID_039e = 0x039e,\n-\tBNXT_ULP_CLASS_HID_05a2 = 0x05a2,\n-\tBNXT_ULP_CLASS_HID_0697 = 0x0697,\n+\tBNXT_ULP_CLASS_HID_00a7 = 0x00a7,\n+\tBNXT_ULP_CLASS_HID_006f = 0x006f,\n+\tBNXT_ULP_CLASS_HID_0181 = 0x0181,\n+\tBNXT_ULP_CLASS_HID_0195 = 0x0195,\n+\tBNXT_ULP_CLASS_HID_00bf = 0x00bf,\n+\tBNXT_ULP_CLASS_HID_0077 = 0x0077,\n+\tBNXT_ULP_CLASS_HID_0199 = 0x0199,\n+\tBNXT_ULP_CLASS_HID_009a = 0x009a,\n+\tBNXT_ULP_CLASS_HID_0192 = 0x0192,\n+\tBNXT_ULP_CLASS_HID_01e2 = 0x01e2,\n+\tBNXT_ULP_CLASS_HID_00fa = 0x00fa,\n+\tBNXT_ULP_CLASS_HID_0165 = 0x0165,\n+\tBNXT_ULP_CLASS_HID_0042 = 0x0042,\n+\tBNXT_ULP_CLASS_HID_00cd = 0x00cd,\n+\tBNXT_ULP_CLASS_HID_01aa = 0x01aa,\n+\tBNXT_ULP_CLASS_HID_0178 = 0x0178,\n+\tBNXT_ULP_CLASS_HID_0070 = 0x0070,\n+\tBNXT_ULP_CLASS_HID_00f3 = 0x00f3,\n+\tBNXT_ULP_CLASS_HID_01d8 = 0x01d8,\n \tBNXT_ULP_CLASS_HID_005b = 0x005b,\n-\tBNXT_ULP_CLASS_HID_0715 = 0x0715,\n-\tBNXT_ULP_CLASS_HID_00d9 = 0x00d9,\n-\tBNXT_ULP_CLASS_HID_05e9 = 0x05e9,\n-\tBNXT_ULP_CLASS_HID_07bd = 0x07bd,\n-\tBNXT_ULP_CLASS_HID_066f = 0x066f,\n-\tBNXT_ULP_CLASS_HID_0033 = 0x0033,\n-\tBNXT_ULP_CLASS_HID_046f = 0x046f,\n-\tBNXT_ULP_CLASS_HID_0633 = 0x0633,\n-\tBNXT_ULP_CLASS_HID_0097 = 0x0097,\n-\tBNXT_ULP_CLASS_HID_025b = 0x025b,\n-\tBNXT_ULP_CLASS_HID_0341 = 0x0341,\n-\tBNXT_ULP_CLASS_HID_0515 = 0x0515,\n-\tBNXT_ULP_CLASS_HID_07e9 = 0x07e9,\n+\tBNXT_ULP_CLASS_HID_0153 = 0x0153,\n+\tBNXT_ULP_CLASS_HID_01a3 = 0x01a3,\n+\tBNXT_ULP_CLASS_HID_00bb = 0x00bb,\n+\tBNXT_ULP_CLASS_HID_0082 = 0x0082,\n+\tBNXT_ULP_CLASS_HID_018a = 0x018a,\n+\tBNXT_ULP_CLASS_HID_01fa = 0x01fa,\n+\tBNXT_ULP_CLASS_HID_00e2 = 0x00e2,\n+\tBNXT_ULP_CLASS_HID_017d = 0x017d,\n+\tBNXT_ULP_CLASS_HID_005a = 0x005a,\n+\tBNXT_ULP_CLASS_HID_00d5 = 0x00d5,\n+\tBNXT_ULP_CLASS_HID_01b2 = 0x01b2,\n+\tBNXT_ULP_CLASS_HID_0160 = 0x0160,\n+\tBNXT_ULP_CLASS_HID_0068 = 0x0068,\n+\tBNXT_ULP_CLASS_HID_00eb = 0x00eb,\n+\tBNXT_ULP_CLASS_HID_01c0 = 0x01c0,\n+\tBNXT_ULP_CLASS_HID_0043 = 0x0043,\n+\tBNXT_ULP_CLASS_HID_014b = 0x014b,\n+\tBNXT_ULP_CLASS_HID_01bb = 0x01bb,\n+\tBNXT_ULP_CLASS_HID_00a3 = 0x00a3,\n+\tBNXT_ULP_CLASS_HID_00cb = 0x00cb,\n+\tBNXT_ULP_CLASS_HID_00b4 = 0x00b4,\n+\tBNXT_ULP_CLASS_HID_0013 = 0x0013,\n+\tBNXT_ULP_CLASS_HID_001c = 0x001c,\n+\tBNXT_ULP_CLASS_HID_017b = 0x017b,\n+\tBNXT_ULP_CLASS_HID_0164 = 0x0164,\n+\tBNXT_ULP_CLASS_HID_00c3 = 0x00c3,\n+\tBNXT_ULP_CLASS_HID_00cc = 0x00cc,\n+\tBNXT_ULP_CLASS_HID_01a5 = 0x01a5,\n+\tBNXT_ULP_CLASS_HID_0196 = 0x0196,\n+\tBNXT_ULP_CLASS_HID_010d = 0x010d,\n+\tBNXT_ULP_CLASS_HID_00fe = 0x00fe,\n+\tBNXT_ULP_CLASS_HID_0084 = 0x0084,\n+\tBNXT_ULP_CLASS_HID_0046 = 0x0046,\n+\tBNXT_ULP_CLASS_HID_01ec = 0x01ec,\n+\tBNXT_ULP_CLASS_HID_01ae = 0x01ae,\n+\tBNXT_ULP_CLASS_HID_00d3 = 0x00d3,\n+\tBNXT_ULP_CLASS_HID_00ac = 0x00ac,\n+\tBNXT_ULP_CLASS_HID_000b = 0x000b,\n+\tBNXT_ULP_CLASS_HID_0004 = 0x0004,\n+\tBNXT_ULP_CLASS_HID_0163 = 0x0163,\n+\tBNXT_ULP_CLASS_HID_017c = 0x017c,\n+\tBNXT_ULP_CLASS_HID_00db = 0x00db,\n+\tBNXT_ULP_CLASS_HID_00d4 = 0x00d4,\n \tBNXT_ULP_CLASS_HID_01bd = 0x01bd,\n-\tBNXT_ULP_CLASS_HID_0147 = 0x0147,\n-\tBNXT_ULP_CLASS_HID_030b = 0x030b,\n-\tBNXT_ULP_CLASS_HID_05ef = 0x05ef,\n-\tBNXT_ULP_CLASS_HID_07b3 = 0x07b3,\n-\tBNXT_ULP_CLASS_HID_0059 = 0x0059,\n-\tBNXT_ULP_CLASS_HID_026d = 0x026d,\n-\tBNXT_ULP_CLASS_HID_00df = 0x00df,\n-\tBNXT_ULP_CLASS_HID_0695 = 0x0695,\n-\tBNXT_ULP_CLASS_HID_02c1 = 0x02c1,\n-\tBNXT_ULP_CLASS_HID_0495 = 0x0495,\n-\tBNXT_ULP_CLASS_HID_0347 = 0x0347,\n-\tBNXT_ULP_CLASS_HID_050b = 0x050b,\n-\tBNXT_ULP_CLASS_HID_0631 = 0x0631,\n-\tBNXT_ULP_CLASS_HID_03ef = 0x03ef,\n-\tBNXT_ULP_CLASS_HID_0259 = 0x0259,\n-\tBNXT_ULP_CLASS_HID_046d = 0x046d\n+\tBNXT_ULP_CLASS_HID_018e = 0x018e,\n+\tBNXT_ULP_CLASS_HID_0115 = 0x0115,\n+\tBNXT_ULP_CLASS_HID_00e6 = 0x00e6,\n+\tBNXT_ULP_CLASS_HID_009c = 0x009c,\n+\tBNXT_ULP_CLASS_HID_005e = 0x005e,\n+\tBNXT_ULP_CLASS_HID_01f4 = 0x01f4,\n+\tBNXT_ULP_CLASS_HID_01b6 = 0x01b6\n };\n \n enum bnxt_ulp_act_hid {\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h\nindex 0e197e362e..fc388cc490 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Tue Dec  1 10:17:11 2020 */\n+/* date: Mon Dec  7 09:51:03 2020 */\n \n #ifndef ULP_HDR_FIELD_ENUMS_H_\n #define ULP_HDR_FIELD_ENUMS_H_\n@@ -113,23 +113,25 @@ enum bnxt_ulp_hf1_0_bitmask {\n \tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n \tBNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n \tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_VER         = 0x0400000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_TC          = 0x0200000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_TTL         = 0x0020000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT     = 0x0004000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT     = 0x0002000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SENT_SEQ     = 0x0001000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_RECV_ACK     = 0x0000800000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DATA_OFF     = 0x0000400000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_TCP_FLAGS    = 0x0000200000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_RX_WIN       = 0x0000100000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_CSUM         = 0x0000080000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_URP          = 0x0000040000000000\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_TOS         = 0x0200000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_LEN         = 0x0100000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT     = 0x0001000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT     = 0x0000800000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SENT_SEQ     = 0x0000400000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_RECV_ACK     = 0x0000200000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DATA_OFF     = 0x0000100000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_TCP_FLAGS    = 0x0000080000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_RX_WIN       = 0x0000040000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_CSUM         = 0x0000020000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_URP          = 0x0000010000000000\n };\n \n enum bnxt_ulp_hf1_1_bitmask {\n@@ -138,26 +140,20 @@ enum bnxt_ulp_hf1_1_bitmask {\n \tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n \tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n \tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_VER         = 0x0080000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_TC          = 0x0040000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_TTL         = 0x0004000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT     = 0x0000800000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT     = 0x0000400000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SENT_SEQ     = 0x0000200000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_RECV_ACK     = 0x0000100000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DATA_OFF     = 0x0000080000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_TCP_FLAGS    = 0x0000040000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_RX_WIN       = 0x0000020000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_CSUM         = 0x0000010000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_URP          = 0x0000008000000000\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_TOS         = 0x0200000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_LEN         = 0x0100000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT     = 0x0001000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT     = 0x0000800000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_UDP_LENGTH       = 0x0000400000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_UDP_CSUM         = 0x0000200000000000\n };\n \n enum bnxt_ulp_hf1_2_bitmask {\n@@ -166,25 +162,23 @@ enum bnxt_ulp_hf1_2_bitmask {\n \tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n \tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n \tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_VER         = 0x0400000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_TOS         = 0x0200000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_LEN         = 0x0100000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_TTL         = 0x0020000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT     = 0x0001000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT     = 0x0000800000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SENT_SEQ     = 0x0000400000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_RECV_ACK     = 0x0000200000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DATA_OFF     = 0x0000100000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_TCP_FLAGS    = 0x0000080000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_RX_WIN       = 0x0000040000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_CSUM         = 0x0000020000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_URP          = 0x0000010000000000\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_TC          = 0x0200000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT     = 0x0004000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT     = 0x0002000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SENT_SEQ     = 0x0001000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_RECV_ACK     = 0x0000800000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DATA_OFF     = 0x0000400000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_TCP_FLAGS    = 0x0000200000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_RX_WIN       = 0x0000100000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_CSUM         = 0x0000080000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_URP          = 0x0000040000000000\n };\n \n enum bnxt_ulp_hf1_3_bitmask {\n@@ -246,18 +240,20 @@ enum bnxt_ulp_hf1_5_bitmask {\n \tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n \tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n \tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_VER         = 0x0080000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_TC          = 0x0040000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_TTL         = 0x0004000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT     = 0x0000800000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT     = 0x0000400000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH       = 0x0000200000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM         = 0x0000100000000000\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM         = 0x0000040000000000\n };\n \n enum bnxt_ulp_hf1_6_bitmask {\n@@ -266,20 +262,26 @@ enum bnxt_ulp_hf1_6_bitmask {\n \tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n \tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n \tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_VER         = 0x0400000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_TOS         = 0x0200000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_LEN         = 0x0100000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_TTL         = 0x0020000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT     = 0x0001000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT     = 0x0000800000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_UDP_LENGTH       = 0x0000400000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_UDP_CSUM         = 0x0000200000000000\n+\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_TC          = 0x0040000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT     = 0x0000800000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT     = 0x0000400000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SENT_SEQ     = 0x0000200000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_TCP_RECV_ACK     = 0x0000100000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DATA_OFF     = 0x0000080000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_TCP_TCP_FLAGS    = 0x0000040000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_TCP_RX_WIN       = 0x0000020000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_TCP_CSUM         = 0x0000010000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_TCP_URP          = 0x0000008000000000\n };\n \n enum bnxt_ulp_hf1_7_bitmask {\n@@ -291,19 +293,17 @@ enum bnxt_ulp_hf1_7_bitmask {\n \tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n \tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n \tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_UDP_CSUM         = 0x0000040000000000\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_TC          = 0x0040000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT     = 0x0000800000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT     = 0x0000400000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_UDP_LENGTH       = 0x0000200000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_UDP_CSUM         = 0x0000100000000000\n };\n #endif\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c\nindex ff003b2ebd..6b49a9d93f 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Tue Dec  1 10:17:11 2020 */\n+/* date: Fri Dec  4 19:01:47 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -36,13 +36,13 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {\n \t.result_num_bytes        = 16,\n \t.result_byte_order       = BNXT_ULP_BYTE_ORDER_LE\n \t},\n-\t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 |\n+\t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 |\n \t\tBNXT_ULP_DIRECTION_INGRESS] = {\n \t.result_num_entries      = 16,\n \t.result_num_bytes        = 16,\n \t.result_byte_order       = BNXT_ULP_BYTE_ORDER_LE\n \t},\n-\t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 |\n+\t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 |\n \t\tBNXT_ULP_DIRECTION_EGRESS] = {\n \t.result_num_entries      = 16,\n \t.result_num_bytes        = 16,\n@@ -207,11 +207,11 @@ uint32_t ulp_glb_template_tbl[] = {\n \n /* Provides act_bitmask */\n struct bnxt_ulp_shared_act_info ulp_shared_act_info[] = {\n-\t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 |\n+\t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 |\n \t\tBNXT_ULP_DIRECTION_INGRESS] = {\n \t.act_bitmask             = BNXT_ULP_ACT_BIT_SHARED_SAMPLE\n \t},\n-\t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 |\n+\t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 |\n \t\tBNXT_ULP_DIRECTION_EGRESS] = {\n \t.act_bitmask             = BNXT_ULP_ACT_BIT_SHARED_SAMPLE\n \t}\n@@ -312,72 +312,66 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[2050] = 2,\n \t[2052] = 3,\n \t[2054] = 4,\n-\t[2076] = 5,\n-\t[2078] = 6,\n-\t[2080] = 7,\n-\t[2082] = 8,\n-\t[2084] = 9,\n-\t[2086] = 10,\n-\t[2088] = 11,\n-\t[2090] = 12,\n-\t[2102] = 13,\n-\t[2104] = 14,\n-\t[2106] = 15,\n-\t[2108] = 16,\n-\t[2110] = 17,\n-\t[2112] = 18,\n-\t[2114] = 19,\n-\t[2116] = 20,\n-\t[2118] = 21,\n+\t[2056] = 5,\n+\t[2058] = 6,\n+\t[2060] = 7,\n+\t[2062] = 8,\n+\t[2064] = 9,\n+\t[2066] = 10,\n+\t[2068] = 11,\n+\t[2070] = 12,\n+\t[2072] = 13,\n+\t[2074] = 14,\n+\t[2102] = 15,\n+\t[2104] = 16,\n+\t[2106] = 17,\n+\t[2108] = 18,\n+\t[2110] = 19,\n+\t[2112] = 20,\n+\t[2114] = 21,\n+\t[2116] = 22,\n+\t[2118] = 23,\n \t[2176] = 0,\n \t[2177] = 1,\n \t[2178] = 2,\n \t[2180] = 3,\n \t[2182] = 4,\n-\t[2204] = 8,\n-\t[2206] = 9,\n-\t[2208] = 10,\n-\t[2210] = 11,\n-\t[2212] = 12,\n-\t[2214] = 13,\n-\t[2216] = 14,\n-\t[2218] = 15,\n-\t[2230] = 16,\n-\t[2232] = 17,\n-\t[2234] = 18,\n-\t[2236] = 19,\n-\t[2238] = 20,\n-\t[2240] = 21,\n-\t[2242] = 22,\n-\t[2244] = 23,\n-\t[2246] = 24,\n-\t[2256] = 5,\n-\t[2260] = 6,\n-\t[2264] = 7,\n+\t[2184] = 5,\n+\t[2186] = 6,\n+\t[2188] = 7,\n+\t[2190] = 8,\n+\t[2192] = 9,\n+\t[2194] = 10,\n+\t[2196] = 11,\n+\t[2198] = 12,\n+\t[2200] = 13,\n+\t[2202] = 14,\n+\t[2248] = 15,\n+\t[2250] = 16,\n+\t[2252] = 17,\n+\t[2254] = 18,\n \t[2304] = 0,\n \t[2305] = 1,\n \t[2306] = 2,\n \t[2308] = 3,\n \t[2310] = 4,\n-\t[2312] = 5,\n-\t[2314] = 6,\n-\t[2316] = 7,\n-\t[2318] = 8,\n-\t[2320] = 9,\n-\t[2322] = 10,\n-\t[2324] = 11,\n-\t[2326] = 12,\n-\t[2328] = 13,\n-\t[2330] = 14,\n-\t[2358] = 15,\n-\t[2360] = 16,\n-\t[2362] = 17,\n-\t[2364] = 18,\n-\t[2366] = 19,\n-\t[2368] = 20,\n-\t[2370] = 21,\n-\t[2372] = 22,\n-\t[2374] = 23,\n+\t[2332] = 5,\n+\t[2334] = 6,\n+\t[2336] = 7,\n+\t[2338] = 8,\n+\t[2340] = 9,\n+\t[2342] = 10,\n+\t[2344] = 11,\n+\t[2346] = 12,\n+\t[2358] = 13,\n+\t[2360] = 14,\n+\t[2362] = 15,\n+\t[2364] = 16,\n+\t[2366] = 17,\n+\t[2368] = 18,\n+\t[2370] = 19,\n+\t[2372] = 20,\n+\t[2374] = 21,\n \t[2432] = 0,\n \t[2433] = 1,\n \t[2434] = 2,\n@@ -427,18 +421,20 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[2690] = 2,\n \t[2692] = 3,\n \t[2694] = 4,\n-\t[2716] = 8,\n-\t[2718] = 9,\n-\t[2720] = 10,\n-\t[2722] = 11,\n-\t[2724] = 12,\n-\t[2726] = 13,\n-\t[2728] = 14,\n-\t[2730] = 15,\n-\t[2760] = 16,\n-\t[2762] = 17,\n-\t[2764] = 18,\n-\t[2766] = 19,\n+\t[2696] = 8,\n+\t[2698] = 9,\n+\t[2700] = 10,\n+\t[2702] = 11,\n+\t[2704] = 12,\n+\t[2706] = 13,\n+\t[2708] = 14,\n+\t[2710] = 15,\n+\t[2712] = 16,\n+\t[2714] = 17,\n+\t[2760] = 18,\n+\t[2762] = 19,\n+\t[2764] = 20,\n+\t[2766] = 21,\n \t[2768] = 5,\n \t[2772] = 6,\n \t[2776] = 7,\n@@ -447,39 +443,43 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[2818] = 2,\n \t[2820] = 3,\n \t[2822] = 4,\n-\t[2824] = 5,\n-\t[2826] = 6,\n-\t[2828] = 7,\n-\t[2830] = 8,\n-\t[2832] = 9,\n-\t[2834] = 10,\n-\t[2836] = 11,\n-\t[2838] = 12,\n-\t[2840] = 13,\n-\t[2842] = 14,\n-\t[2888] = 15,\n-\t[2890] = 16,\n-\t[2892] = 17,\n-\t[2894] = 18,\n+\t[2844] = 8,\n+\t[2846] = 9,\n+\t[2848] = 10,\n+\t[2850] = 11,\n+\t[2852] = 12,\n+\t[2854] = 13,\n+\t[2856] = 14,\n+\t[2858] = 15,\n+\t[2870] = 16,\n+\t[2872] = 17,\n+\t[2874] = 18,\n+\t[2876] = 19,\n+\t[2878] = 20,\n+\t[2880] = 21,\n+\t[2882] = 22,\n+\t[2884] = 23,\n+\t[2886] = 24,\n+\t[2896] = 5,\n+\t[2900] = 6,\n+\t[2904] = 7,\n \t[2944] = 0,\n \t[2945] = 1,\n \t[2946] = 2,\n \t[2948] = 3,\n \t[2950] = 4,\n-\t[2952] = 8,\n-\t[2954] = 9,\n-\t[2956] = 10,\n-\t[2958] = 11,\n-\t[2960] = 12,\n-\t[2962] = 13,\n-\t[2964] = 14,\n-\t[2966] = 15,\n-\t[2968] = 16,\n-\t[2970] = 17,\n-\t[3016] = 18,\n-\t[3018] = 19,\n-\t[3020] = 20,\n-\t[3022] = 21,\n+\t[2972] = 8,\n+\t[2974] = 9,\n+\t[2976] = 10,\n+\t[2978] = 11,\n+\t[2980] = 12,\n+\t[2982] = 13,\n+\t[2984] = 14,\n+\t[2986] = 15,\n+\t[3016] = 16,\n+\t[3018] = 17,\n+\t[3020] = 18,\n+\t[3022] = 19,\n \t[3024] = 5,\n \t[3028] = 6,\n \t[3032] = 7\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c\nindex 5b098cff37..78ee8ed6d1 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Tue Dec  1 17:07:12 2020 */\n+/* date: Mon Dec  7 09:51:03 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -18,9 +18,9 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = {\n \t.num_tbls = 4,\n \t.start_tbl_idx = 0,\n \t.reject_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 0,\n-\t\t.cond_nums = 0 }\n+\t\t.cond_nums = 9 }\n \t}\n };\n \n@@ -34,7 +34,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 0,\n+\t\t.cond_start_idx = 9,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,\n@@ -56,7 +56,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 1,\n+\t\t.cond_start_idx = 10,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n@@ -78,7 +78,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 2,\n+\t\t.cond_start_idx = 11,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n@@ -100,7 +100,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 2,\n+\t\t.cond_start_idx = 11,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n@@ -115,6 +115,42 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n };\n \n struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_SRC\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_TP_SRC\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_DST\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_TP_DST\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_VID\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_PCP\n+\t},\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n \t.cond_operand = BNXT_ULP_ACT_BIT_COUNT\n@@ -432,8 +468,21 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST\n \t},\n \t{\n \t.description = \"drop\",\n@@ -687,7 +736,10 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"drop\",\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c\nindex 52eab7a715..82cbb9b964 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Wed Dec  2 12:05:11 2020 */\n+/* date: Mon Dec  7 10:38:39 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {\n \t/* class_tid: 1, wh_plus, ingress */\n \t[1] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.num_tbls = 9,\n+\t.num_tbls = 11,\n \t.start_tbl_idx = 0,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n@@ -26,76 +26,55 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {\n \t[2] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.num_tbls = 6,\n-\t.start_tbl_idx = 9,\n+\t.start_tbl_idx = 11,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 4,\n+\t\t.cond_start_idx = 6,\n \t\t.cond_nums = 0 }\n \t},\n \t/* class_tid: 3, wh_plus, egress */\n \t[3] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.num_tbls = 8,\n-\t.start_tbl_idx = 15,\n+\t.start_tbl_idx = 17,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 4,\n+\t\t.cond_start_idx = 6,\n \t\t.cond_nums = 0 }\n \t},\n \t/* class_tid: 4, wh_plus, egress */\n \t[4] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.num_tbls = 7,\n-\t.start_tbl_idx = 23,\n+\t.num_tbls = 8,\n+\t.start_tbl_idx = 25,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 12,\n \t\t.cond_nums = 0 }\n \t},\n \t/* class_tid: 5, wh_plus, egress */\n \t[5] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.num_tbls = 7,\n-\t.start_tbl_idx = 30,\n+\t.start_tbl_idx = 33,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 14,\n \t\t.cond_nums = 0 }\n \t},\n \t/* class_tid: 6, wh_plus, egress */\n \t[6] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.num_tbls = 1,\n-\t.start_tbl_idx = 37,\n+\t.start_tbl_idx = 40,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 14,\n \t\t.cond_nums = 0 }\n \t}\n };\n \n struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n-\t{ /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_goto = 2,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 0,\n-\t\t.cond_nums = 1 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 0,\n-\t.blob_key_bit_size = 8,\n-\t.key_bit_size = 8,\n-\t.key_num_fields = 1,\n-\t.ident_start_idx = 0,\n-\t.ident_nums = 1\n-\t},\n \t{ /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n@@ -103,7 +82,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 1,\n+\t\t.cond_start_idx = 0,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n@@ -111,7 +90,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n-\t.key_start_idx = 1,\n+\t.key_start_idx = 0,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n@@ -119,7 +98,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 1,\n+\t.ident_start_idx = 0,\n \t.ident_nums = 1\n \t},\n \t{ /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */\n@@ -131,30 +110,57 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 1,\n+\t\t.cond_start_idx = 0,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 14,\n+\t.key_start_idx = 13,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n-\t.ident_start_idx = 2,\n+\t.ident_start_idx = 1,\n \t.ident_nums = 3\n \t},\n \t{ /* class_tid: 1, wh_plus, table: branch.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 3,\n+\t\t.cond_goto = 4,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 1,\n+\t\t.cond_start_idx = 0,\n \t\t.cond_nums = 1 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH\n \t},\n-\t{ /* class_tid: 1, wh_plus, table: profile_tcam.0 */\n+\t{ /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_goto = 2,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 1,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n+\t.key_start_idx = 16,\n+\t.blob_key_bit_size = 81,\n+\t.key_bit_size = 81,\n+\t.key_num_fields = 43,\n+\t.result_start_idx = 13,\n+\t.result_bit_size = 38,\n+\t.result_num_fields = 8,\n+\t.encap_num_fields = 0,\n+\t.ident_start_idx = 4,\n+\t.ident_nums = 1\n+\t},\n+\t{ /* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.direction = TF_DIR_RX,\n@@ -170,11 +176,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 17,\n+\t.key_start_idx = 59,\n \t.blob_key_bit_size = 81,\n \t.key_bit_size = 81,\n \t.key_num_fields = 43,\n-\t.result_start_idx = 13,\n+\t.result_start_idx = 21,\n \t.result_bit_size = 38,\n \t.result_num_fields = 8,\n \t.encap_num_fields = 0,\n@@ -195,16 +201,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 60,\n+\t.key_start_idx = 102,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n-\t.result_start_idx = 21,\n+\t.result_start_idx = 29,\n \t.result_bit_size = 66,\n \t.result_num_fields = 5,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 1, wh_plus, table: em.int_0 */\n+\t{ /* class_tid: 1, wh_plus, table: em.ipv4_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,\n \t.resource_type = TF_MEM_INTERNAL,\n \t.direction = TF_DIR_RX,\n@@ -218,22 +224,22 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 63,\n+\t.key_start_idx = 105,\n \t.blob_key_bit_size = 176,\n \t.key_bit_size = 176,\n \t.key_num_fields = 10,\n-\t.result_start_idx = 26,\n+\t.result_start_idx = 34,\n \t.result_bit_size = 64,\n \t.result_num_fields = 9,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 1, wh_plus, table: eem.ext_0 */\n+\t{ /* class_tid: 1, wh_plus, table: eem.ipv4_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,\n \t.resource_type = TF_MEM_EXTERNAL,\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_goto = 3,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 3,\n \t\t.cond_nums = 1 },\n@@ -241,22 +247,68 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 73,\n+\t.key_start_idx = 115,\n \t.blob_key_bit_size = 448,\n \t.key_bit_size = 448,\n \t.key_num_fields = 10,\n-\t.result_start_idx = 35,\n+\t.result_start_idx = 43,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 9,\n+\t.encap_num_fields = 0\n+\t},\n+\t{ /* class_tid: 1, wh_plus, table: em.ipv6_0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,\n+\t.resource_type = TF_MEM_INTERNAL,\n+\t.direction = TF_DIR_RX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n+\t.execute_info = {\n+\t\t.cond_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 4,\n+\t\t.cond_nums = 1 },\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n+\t.key_start_idx = 125,\n+\t.blob_key_bit_size = 416,\n+\t.key_bit_size = 416,\n+\t.key_num_fields = 11,\n+\t.result_start_idx = 52,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 9,\n+\t.encap_num_fields = 0\n+\t},\n+\t{ /* class_tid: 1, wh_plus, table: eem.ipv6_0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,\n+\t.resource_type = TF_MEM_EXTERNAL,\n+\t.direction = TF_DIR_RX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n+\t.execute_info = {\n+\t\t.cond_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 5,\n+\t\t.cond_nums = 1 },\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n+\t.key_start_idx = 136,\n+\t.blob_key_bit_size = 448,\n+\t.key_bit_size = 448,\n+\t.key_num_fields = 11,\n+\t.result_start_idx = 61,\n \t.result_bit_size = 64,\n \t.result_num_fields = 9,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 1, wh_plus, table: last */\n+\t{ /* class_tid: 1, wh_plus, table: branch.last */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 4,\n+\t\t.cond_start_idx = 6,\n \t\t.cond_nums = 0 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH\n@@ -270,14 +322,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 4,\n+\t\t.cond_start_idx = 6,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 44,\n+\t.result_start_idx = 70,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n@@ -289,7 +341,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 4,\n+\t\t.cond_start_idx = 6,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n@@ -300,11 +352,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 83,\n+\t.key_start_idx = 147,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 70,\n+\t.result_start_idx = 96,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n@@ -320,16 +372,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 4,\n+\t\t.cond_start_idx = 6,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 96,\n+\t.key_start_idx = 160,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 83,\n+\t.result_start_idx = 109,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4,\n \t.encap_num_fields = 0\n@@ -341,13 +393,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 4,\n+\t\t.cond_start_idx = 6,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 87,\n+\t.result_start_idx = 113,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n@@ -359,13 +411,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 4,\n+\t\t.cond_start_idx = 6,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 88,\n+\t.result_start_idx = 114,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n@@ -377,13 +429,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 4,\n+\t\t.cond_start_idx = 6,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 89,\n+\t.result_start_idx = 115,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n@@ -397,14 +449,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 4,\n+\t\t.cond_start_idx = 6,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 90,\n+\t.result_start_idx = 116,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n@@ -416,7 +468,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 4,\n+\t\t.cond_start_idx = 6,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n@@ -426,11 +478,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 97,\n+\t.key_start_idx = 161,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 116,\n+\t.result_start_idx = 142,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n@@ -446,12 +498,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 5,\n+\t\t.cond_start_idx = 7,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 110,\n+\t.key_start_idx = 174,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n@@ -465,7 +517,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 6,\n+\t\t.cond_start_idx = 8,\n \t\t.cond_nums = 2 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n@@ -474,11 +526,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 111,\n+\t.key_start_idx = 175,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 129,\n+\t.result_start_idx = 155,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n@@ -494,16 +546,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 8,\n+\t\t.cond_start_idx = 10,\n \t\t.cond_nums = 2 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 124,\n+\t.key_start_idx = 188,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 142,\n+\t.result_start_idx = 168,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4,\n \t.encap_num_fields = 0\n@@ -515,13 +567,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 12,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 146,\n+\t.result_start_idx = 172,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n@@ -533,13 +585,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 12,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 147,\n+\t.result_start_idx = 173,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n@@ -551,17 +603,38 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 12,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 148,\n+\t.result_start_idx = 174,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n+\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 12,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.key_start_idx = 189,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 9,\n+\t.ident_nums = 1\n+\t},\n \t{ /* class_tid: 4, wh_plus, table: int_vtag_encap_record.egr0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,\n@@ -571,14 +644,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 12,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 149,\n+\t.result_start_idx = 175,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n \t.encap_num_fields = 12\n@@ -592,14 +665,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 12,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 161,\n+\t.result_start_idx = 187,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n@@ -610,9 +683,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n \t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n-\t\t.cond_nums = 0 },\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 12,\n+\t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n@@ -620,15 +693,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n-\t.key_start_idx = 125,\n+\t.key_start_idx = 190,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 187,\n+\t.result_start_idx = 213,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 9,\n+\t.ident_start_idx = 10,\n \t.ident_nums = 0\n \t},\n \t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */\n@@ -639,22 +712,20 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n \t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n-\t\t.cond_nums = 0 },\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 13,\n+\t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 138,\n+\t.key_start_idx = 203,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 200,\n+\t.result_start_idx = 226,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4,\n-\t.encap_num_fields = 0,\n-\t.ident_start_idx = 9,\n-\t.ident_nums = 0\n+\t.encap_num_fields = 0\n \t},\n \t{ /* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -665,14 +736,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 14,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 204,\n+\t.result_start_idx = 230,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n@@ -684,7 +755,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 14,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n@@ -694,15 +765,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 139,\n+\t.key_start_idx = 204,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 230,\n+\t.result_start_idx = 256,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 9,\n+\t.ident_start_idx = 10,\n \t.ident_nums = 0\n \t},\n \t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n@@ -712,7 +783,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 14,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n@@ -722,15 +793,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 152,\n+\t.key_start_idx = 217,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 243,\n+\t.result_start_idx = 269,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 9,\n+\t.ident_start_idx = 10,\n \t.ident_nums = 0\n \t},\n \t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */\n@@ -740,24 +811,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 14,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n-\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n-\t.key_start_idx = 165,\n+\t.key_start_idx = 230,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 256,\n+\t.result_start_idx = 282,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 9,\n+\t.ident_start_idx = 10,\n \t.ident_nums = 1\n \t},\n \t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */\n@@ -769,16 +839,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 14,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 178,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.key_start_idx = 243,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 269,\n+\t.result_start_idx = 295,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4,\n \t.encap_num_fields = 0\n@@ -790,13 +861,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 14,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 273,\n+\t.result_start_idx = 299,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n@@ -808,13 +879,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 14,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 274,\n+\t.result_start_idx = 300,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n@@ -826,13 +897,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 14,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 275,\n+\t.result_start_idx = 301,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n@@ -846,14 +917,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 14,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,\n-\t.result_start_idx = 276,\n+\t.result_start_idx = 302,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n@@ -865,7 +936,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 14,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n@@ -875,15 +946,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 179,\n+\t.key_start_idx = 244,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 302,\n+\t.result_start_idx = 328,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 10,\n+\t.ident_start_idx = 11,\n \t.ident_nums = 0\n \t},\n \t{ /* class_tid: 6, wh_plus, table: int_full_act_record.0 */\n@@ -895,14 +966,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.execute_info = {\n \t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 10,\n+\t\t.cond_start_idx = 14,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,\n \t.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 315,\n+\t.result_start_idx = 341,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n@@ -910,10 +981,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n };\n \n struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,\n-\t.cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC\n-\t},\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n@@ -927,6 +994,18 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {\n \t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n \t},\n \t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV6\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV6\n+\t},\n+\t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n \t},\n@@ -949,31 +1028,18 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n \t}\n };\n \n struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n-\t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n-\t\t}\n-\t},\n \t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.field_info_mask = {\n@@ -1241,7 +1307,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 1, wh_plus, table: profile_tcam.0 */\n+\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l4_hdr_is_udp_tcp\",\n@@ -1374,22 +1440,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t.field_info_spec = {\n \t\t.description = \"l3_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_L3_HDR_TYPE_IPV4},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr2 = {\n-\t\t\tULP_WP_SYM_L3_HDR_TYPE_IPV6}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -1926,281 +1978,1181 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */\n+\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L4_HDR_TYPE_TCP},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_L4_HDR_TYPE_UDP}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n+\t\t\tULP_WP_SYM_L4_HDR_VALID_YES}\n \t\t}\n \t},\n-\t/* class_tid: 1, wh_plus, table: em.int_0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t\tULP_WP_SYM_L3_HDR_TYPE_IPV6}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_IP_PROTO_TCP},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr2 = {\n-\t\t\tULP_WP_SYM_IP_PROTO_UDP}\n+\t\t\tULP_WP_SYM_L3_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L2_HDR_VALID_YES}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_err\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_err\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"hrec_next\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"hrec_next\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n+\t\t}\n+\t},\n+\t/* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 1, wh_plus, table: em.ipv4_0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv4.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv4.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_IP_PROTO_TCP},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_IP_PROTO_UDP}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv4.dst\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv4.dst\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv4.src\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv4.src\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 1, wh_plus, table: eem.ipv4_0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 275,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 275,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv4.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv4.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_IP_PROTO_TCP},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_IP_PROTO_UDP}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv4.dst\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv4.dst\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv4.src\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv4.src\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t\t.field_opr1 = {\n@@ -2208,17 +3160,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 1, wh_plus, table: eem.ext_0 */\n+\t/* class_tid: 1, wh_plus, table: em.ipv6_0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"spare\",\n-\t\t.field_bit_size = 275,\n+\t\t.field_bit_size = 3,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"spare\",\n-\t\t.field_bit_size = 275,\n+\t\t.field_bit_size = 3,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n@@ -2307,7 +3259,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n+\t\t.description = \"o_ipv6.ip_proto\",\n \t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -2315,7 +3267,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n+\t\t.description = \"o_ipv6.ip_proto\",\n \t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n \t\t.field_cond_opr = {\n@@ -2337,42 +3289,290 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 1, wh_plus, table: eem.ipv6_0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 35,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 35,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_IP_PROTO_TCP},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_IP_PROTO_UDP}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n@@ -2397,6 +3597,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t}\n \t},\n \t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n \t.field_info_mask = {\n \t\t.description = \"l2_cntxt_id\",\n \t\t.field_bit_size = 10,\n@@ -3077,6 +4298,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n \t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */\n \t{\n \t.field_info_mask = {\n@@ -4208,14 +5449,12 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, wh_plus, table: profile_tcam.0 */\n+\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */\n \t{\n \t.description = \"wc_key_id\",\n \t.field_bit_size = 4,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t3}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"wc_profile_id\",\n@@ -4269,6 +5508,65 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */\n+\t{\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 4,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"wc_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask\",\n+\t.field_bit_size = 10,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t(249 >> 8) & 0xff,\n+\t\t249 & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 5,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t7}\n+\t},\n+\t{\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n+\t},\n+\t{\n+\t.description = \"pl_byp_lkup_en\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n \t/* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */\n \t{\n \t.description = \"rid\",\n@@ -4312,7 +5610,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n \t\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n \t},\n-\t/* class_tid: 1, wh_plus, table: em.int_0 */\n+\t/* class_tid: 1, wh_plus, table: em.ipv4_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 33,\n@@ -4374,7 +5672,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opr1 = {\n \t\t1}\n \t},\n-\t/* class_tid: 1, wh_plus, table: eem.ext_0 */\n+\t/* class_tid: 1, wh_plus, table: eem.ipv4_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 33,\n@@ -4444,6 +5742,138 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opr1 = {\n \t\t1}\n \t},\n+\t/* class_tid: 1, wh_plus, table: em.ipv6_0 */\n+\t{\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t},\n+\t{\n+\t.description = \"ext_flow_cntr\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"act_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"act_rec_size\",\n+\t.field_bit_size = 5,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n+\t},\n+\t{\n+\t.description = \"l1_cacheable\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"valid\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n+\t},\n+\t/* class_tid: 1, wh_plus, table: eem.ipv6_0 */\n+\t{\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t},\n+\t{\n+\t.description = \"ext_flow_cntr\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"act_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_EEM_ACT_REC_INT}\n+\t},\n+\t{\n+\t.description = \"act_rec_size\",\n+\t.field_bit_size = 5,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}\n+\t},\n+\t{\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t(413 >> 8) & 0xff,\n+\t\t413 & 0xff}\n+\t},\n+\t{\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n+\t},\n+\t{\n+\t.description = \"l1_cacheable\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"valid\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n+\t},\n \t/* class_tid: 2, wh_plus, table: int_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n@@ -6417,13 +7847,6 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n };\n \n struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n-\t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */\n-\t{\n-\t.description = \"l2_cntxt_id\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n-\t.ident_bit_size = 10,\n-\t.ident_bit_pos = 42\n-\t},\n \t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n@@ -6435,6 +7858,12 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t},\n \t/* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */\n \t{\n+\t.description = \"flow_sig_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,\n+\t.ident_bit_size = 8,\n+\t.ident_bit_pos = 58\n+\t},\n+\t{\n \t.description = \"profile_tcam_index\",\n \t.regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n \t.ident_bit_size = 10,\n@@ -6446,13 +7875,16 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 8,\n \t.ident_bit_pos = 42\n \t},\n+\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */\n \t{\n-\t.description = \"flow_sig_id\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,\n+\t.description = \"em_profile_id\",\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.ident_type = TF_IDENT_TYPE_EM_PROF,\n+\t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n \t.ident_bit_size = 8,\n-\t.ident_bit_pos = 58\n+\t.ident_bit_pos = 28\n \t},\n-\t/* class_tid: 1, wh_plus, table: profile_tcam.0 */\n+\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */\n \t{\n \t.description = \"em_profile_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -6486,6 +7918,13 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 0\n \t},\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */\n+\t{\n+\t.description = \"l2_cntxt_tcam_index\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.ident_bit_size = 10,\n+\t.ident_bit_pos = 32\n+\t},\n \t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */\n \t{\n \t.description = \"l2_cntxt_id\",\n",
    "prefixes": [
        "37/58"
    ]
}