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GET /api/patches/93235/?format=api
{ "id": 93235, "url": "http://patches.dpdk.org/api/patches/93235/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1620843888-882873-1-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1620843888-882873-1-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1620843888-882873-1-git-send-email-timothy.mcdaniel@intel.com", "date": "2021-05-12T18:24:48", "name": "[1/1] event/dlb2: fix vector based dequeue", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b60a5b0c7a115b3b53eaf7cb026ad7acdc6e6978", "submitter": { "id": 826, "url": "http://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1620843888-882873-1-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 16973, "url": "http://patches.dpdk.org/api/series/16973/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16973", "date": "2021-05-12T18:24:48", "name": "[1/1] event/dlb2: fix vector based dequeue", "version": 1, "mbox": "http://patches.dpdk.org/series/16973/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/93235/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/93235/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C6286A0C41;\n\tWed, 12 May 2021 20:24:59 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3D7FD4003F;\n\tWed, 12 May 2021 20:24:59 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id 7FA374003E\n for <dev@dpdk.org>; Wed, 12 May 2021 20:24:55 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 May 2021 11:24:53 -0700", "from txanpdk03.an.intel.com ([10.123.117.78])\n by fmsmga005.fm.intel.com with ESMTP; 12 May 2021 11:24:52 -0700" ], "IronPort-SDR": [ "\n bfd4SoqFQiaR48hySNQ1g6YjeQgV+BujJcfQ5y4XYGkn1QD6mdv4titLUh44YfFs/gv6/zNb/A\n B+pCMakmmCmw==", "\n xBh0nHtxXvht2AF2ucaaWS/K2YlssyWvxEqT8pUfDrvI13wtOvwFP6re6+zaj9lS9cN3oAXZrD\n vP1RkHKibhEQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9982\"; a=\"285280781\"", "E=Sophos;i=\"5.82,293,1613462400\"; d=\"scan'208\";a=\"285280781\"", "E=Sophos;i=\"5.82,293,1613462400\"; d=\"scan'208\";a=\"625528948\"" ], "X-ExtLoop1": "1", "From": "\"McDaniel, Timothy\" <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, harry.van.haaren@intel.com,\n jerinj@marvell.com, thomas@monjalon.net,\n Timothy McDaniel <timothy.mcdaniel@intel.com>", "Date": "Wed, 12 May 2021 13:24:48 -0500", "Message-Id": "<1620843888-882873-1-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "Subject": "[dpdk-dev] [PATCH 1/1] event/dlb2: fix vector based dequeue", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Timothy McDaniel <timothy.mcdaniel@intel.com>\n\nThis commit fixes the following bugs in the vector based\ndequeue path:\n- extract hw sched type\n- update xstats\n\nThe default mode of operation was also changed from vector\noptimized mode to scalar mode.\n\nFixes: 000a7b8e7582 (\"event/dlb2: optimize dequeue operation\")\nCc: timothy.mcdaniel@intel.com\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/dlb2.c | 40 ++++++++++++++++++++++++----------\n drivers/event/dlb2/dlb2_priv.h | 7 +++---\n 2 files changed, 31 insertions(+), 16 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex 3570678b9..b5745f6f4 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -376,11 +376,11 @@ set_default_depth_thresh(const char *key __rte_unused,\n }\n \n static int\n-set_vector_opts_disab(const char *key __rte_unused,\n+set_vector_opts_enab(const char *key __rte_unused,\n \tconst char *value,\n \tvoid *opaque)\n {\n-\tbool *dlb2_vector_opts_disabled = opaque;\n+\tbool *dlb2_vector_opts_enabled = opaque;\n \n \tif (value == NULL || opaque == NULL) {\n \t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n@@ -388,9 +388,9 @@ set_vector_opts_disab(const char *key __rte_unused,\n \t}\n \n \tif ((*value == 'y') || (*value == 'Y'))\n-\t\t*dlb2_vector_opts_disabled = true;\n+\t\t*dlb2_vector_opts_enabled = true;\n \telse\n-\t\t*dlb2_vector_opts_disabled = false;\n+\t\t*dlb2_vector_opts_enabled = false;\n \n \treturn 0;\n }\n@@ -1469,7 +1469,7 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,\n #else\n \tif ((qm_port->cq_depth > 64) ||\n \t (!rte_is_power_of_2(qm_port->cq_depth)) ||\n-\t (dlb2->vector_opts_disabled == true))\n+\t (dlb2->vector_opts_enabled == false))\n \t\tqm_port->use_scalar = true;\n #endif\n \n@@ -1665,7 +1665,7 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,\n #else\n \tif ((qm_port->cq_depth > 64) ||\n \t (!rte_is_power_of_2(qm_port->cq_depth)) ||\n-\t (dlb2->vector_opts_disabled == true))\n+\t (dlb2->vector_opts_enabled == false))\n \t\tqm_port->use_scalar = true;\n #endif\n \n@@ -3561,6 +3561,11 @@ _process_deq_qes_vec_impl(struct dlb2_port *qm_port,\n \tint ev_qid2 = qm_port->qid_mappings[hw_qid2];\n \tint ev_qid3 = qm_port->qid_mappings[hw_qid3];\n \n+\tint hw_sched0 = _mm_extract_epi8(v_qe_meta, 3) & 3ul;\n+\tint hw_sched1 = _mm_extract_epi8(v_qe_meta, 7) & 3ul;\n+\tint hw_sched2 = _mm_extract_epi8(v_qe_meta, 11) & 3ul;\n+\tint hw_sched3 = _mm_extract_epi8(v_qe_meta, 15) & 3ul;\n+\n \tv_qid_done = _mm_insert_epi8(v_qid_done, ev_qid0, 2);\n \tv_qid_done = _mm_insert_epi8(v_qid_done, ev_qid1, 6);\n \tv_qid_done = _mm_insert_epi8(v_qid_done, ev_qid2, 10);\n@@ -3682,19 +3687,30 @@ _process_deq_qes_vec_impl(struct dlb2_port *qm_port,\n \t\tv_ev_3 = _mm_blend_epi16(v_unpk_ev_23, v_qe_3, 0x0F);\n \t\tv_ev_3 = _mm_alignr_epi8(v_ev_3, v_ev_3, 8);\n \t\t_mm_storeu_si128((__m128i *)&events[3], v_ev_3);\n+\t\tDLB2_INC_STAT(qm_port->ev_port->stats.rx_sched_cnt[hw_sched3],\n+\t\t\t 1);\n+\n \t\t/* fallthrough */\n \tcase 3:\n \t\tv_ev_2 = _mm_unpacklo_epi64(v_unpk_ev_23, v_qe_2);\n \t\t_mm_storeu_si128((__m128i *)&events[2], v_ev_2);\n+\t\tDLB2_INC_STAT(qm_port->ev_port->stats.rx_sched_cnt[hw_sched2],\n+\t\t\t\t\t 1);\n \t\t/* fallthrough */\n \tcase 2:\n \t\tv_ev_1 = _mm_blend_epi16(v_unpk_ev_01, v_qe_1, 0x0F);\n \t\tv_ev_1 = _mm_alignr_epi8(v_ev_1, v_ev_1, 8);\n \t\t_mm_storeu_si128((__m128i *)&events[1], v_ev_1);\n+\t\tDLB2_INC_STAT(qm_port->ev_port->stats.rx_sched_cnt[hw_sched1],\n+\t\t1);\n+\n \t\t/* fallthrough */\n \tcase 1:\n \t\tv_ev_0 = _mm_unpacklo_epi64(v_unpk_ev_01, v_qe_0);\n \t\t_mm_storeu_si128((__m128i *)&events[0], v_ev_0);\n+\t\tDLB2_INC_STAT(qm_port->ev_port->stats.rx_sched_cnt[hw_sched0],\n+\t\t\t 1);\n+\n \t}\n }\n \n@@ -4421,7 +4437,7 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev,\n \tdlb2->poll_interval = dlb2_args->poll_interval;\n \tdlb2->sw_credit_quanta = dlb2_args->sw_credit_quanta;\n \tdlb2->default_depth_thresh = dlb2_args->default_depth_thresh;\n-\tdlb2->vector_opts_disabled = dlb2_args->vector_opts_disabled;\n+\tdlb2->vector_opts_enabled = dlb2_args->vector_opts_enabled;\n \n \terr = dlb2_iface_open(&dlb2->qm_instance, name);\n \tif (err < 0) {\n@@ -4525,7 +4541,7 @@ dlb2_parse_params(const char *params,\n \t\t\t\t\t DLB2_POLL_INTERVAL_ARG,\n \t\t\t\t\t DLB2_SW_CREDIT_QUANTA_ARG,\n \t\t\t\t\t DLB2_DEPTH_THRESH_ARG,\n-\t\t\t\t\t DLB2_VECTOR_OPTS_DISAB_ARG,\n+\t\t\t\t\t DLB2_VECTOR_OPTS_ENAB_ARG,\n \t\t\t\t\t NULL };\n \n \tif (params != NULL && params[0] != '\\0') {\n@@ -4640,11 +4656,11 @@ dlb2_parse_params(const char *params,\n \t\t\t}\n \n \t\t\tret = rte_kvargs_process(kvlist,\n-\t\t\t\t\tDLB2_VECTOR_OPTS_DISAB_ARG,\n-\t\t\t\t\tset_vector_opts_disab,\n-\t\t\t\t\t&dlb2_args->vector_opts_disabled);\n+\t\t\t\t\tDLB2_VECTOR_OPTS_ENAB_ARG,\n+\t\t\t\t\tset_vector_opts_enab,\n+\t\t\t\t\t&dlb2_args->vector_opts_enabled);\n \t\t\tif (ret != 0) {\n-\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing vector opts disabled\",\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing vector opts enabled\",\n \t\t\t\t\t name);\n \t\t\t\trte_kvargs_free(kvlist);\n \t\t\t\treturn ret;\ndiff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h\nindex 3140764a5..e23702100 100644\n--- a/drivers/event/dlb2/dlb2_priv.h\n+++ b/drivers/event/dlb2/dlb2_priv.h\n@@ -32,13 +32,12 @@\n #define DLB2_MAX_NUM_EVENTS \"max_num_events\"\n #define DLB2_NUM_DIR_CREDITS \"num_dir_credits\"\n #define DEV_ID_ARG \"dev_id\"\n-#define DLB2_DEFER_SCHED_ARG \"defer_sched\"\n #define DLB2_QID_DEPTH_THRESH_ARG \"qid_depth_thresh\"\n #define DLB2_COS_ARG \"cos\"\n #define DLB2_POLL_INTERVAL_ARG \"poll_interval\"\n #define DLB2_SW_CREDIT_QUANTA_ARG \"sw_credit_quanta\"\n #define DLB2_DEPTH_THRESH_ARG \"default_depth_thresh\"\n-#define DLB2_VECTOR_OPTS_DISAB_ARG \"vector_opts_disable\"\n+#define DLB2_VECTOR_OPTS_ENAB_ARG \"vector_opts_enable\"\n \n /* Begin HW related defines and structs */\n \n@@ -566,7 +565,7 @@ struct dlb2_eventdev {\n \tuint32_t new_event_limit;\n \tint max_num_events_override;\n \tint num_dir_credits_override;\n-\tbool vector_opts_disabled;\n+\tbool vector_opts_enabled;\n \tvolatile enum dlb2_run_state run_state;\n \tuint16_t num_dir_queues; /* total num of evdev dir queues requested */\n \tunion {\n@@ -626,7 +625,7 @@ struct dlb2_devargs {\n \tint poll_interval;\n \tint sw_credit_quanta;\n \tint default_depth_thresh;\n-\tbool vector_opts_disabled;\n+\tbool vector_opts_enabled;\n };\n \n /* End Eventdev related defines and structs */\n", "prefixes": [ "1/1" ] }