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GET /api/patches/92895/?format=api
{ "id": 92895, "url": "http://patches.dpdk.org/api/patches/92895/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210505095009.40250-2-bingz@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210505095009.40250-2-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210505095009.40250-2-bingz@nvidia.com", "date": "2021-05-05T09:49:53", "name": "[v6,01/17] common/mlx5: add connection tracking object definition", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "effd572fac3ef28a6003d53c9982cb13728879e4", "submitter": { "id": 1976, "url": "http://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210505095009.40250-2-bingz@nvidia.com/mbox/", "series": [ { "id": 16824, "url": "http://patches.dpdk.org/api/series/16824/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16824", "date": "2021-05-05T09:49:52", "name": "conntrack support in mlx5 PMD", "version": 6, "mbox": "http://patches.dpdk.org/series/16824/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92895/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92895/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A6E0EA0524;\n\tWed, 5 May 2021 11:50:34 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 63901410E5;\n\tWed, 5 May 2021 11:50:32 +0200 (CEST)", "from NAM04-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam08on2077.outbound.protection.outlook.com [40.107.101.77])\n by mails.dpdk.org (Postfix) with ESMTP id 9B904410E1\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>, <thomas@monjalon.net>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, <rasland@nvidia.com>", "Date": "Wed, 5 May 2021 12:49:53 +0300", "Message-ID": "<20210505095009.40250-2-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210505095009.40250-1-bingz@nvidia.com>", "References": "<20210427153811.11554-1-bingz@nvidia.com>\n <20210505095009.40250-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "45089a82-bde6-4047-4d3f-08d90fab379e", "X-MS-TrafficTypeDiagnostic": "DM5PR1201MB2521:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <DM5PR1201MB2521FDE3A83E4AA74EAB6976D0599@DM5PR1201MB2521.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:5797;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n gn/YVPwFGXs+0iPgZ62oQcG4MVeOVZT8vNaRMo+cG1MZMSQPgwYBr04lWkcTEb0lLtQ77EC5VfFC86HMN0S4VgbBlt1j295gDGpMzOjA40fkuWb58Z6OSzTRVrbUiZ6f4PGrwtOCfZoUOsePQFzd3E5Qw2jU8jd9Q85U+Q0XDYwjwVfLag56UOErQ6PiFOnQVI6M3Lc8J2d+ltQScJ1EFeapcQwY7qtoYCjf04J7nw1SDBlsD7MJyZHhVtFszOI5/s5GgfkfQYYYzDYzJSxjbs/A548CZ001wYXZUIHEWzATOQ38UiD6guNfsIgO6NEVNa1toNs93ajGNsu0oJ7T0pT41ztIFdYIxakSPZTSrUK4n4r0eWac3sL+jS3Kn7VGAl7ha4Jxd2qOXk13Jleyr7IMK3aCbzfHsOu6BqznNdGDov8l2KTQ/j1wBoap0R6aFr23kBYAzrHX2q6TgyRH7pSr3KfpZR/HYBbIddikM5qk1uxN0Q9tUN8tmiouyAXKGMLhLgpPZu/vzu7supKyuDnpfDI540Utj/edc53oMjGtuvbpQhRvPlXCMvwnl1UHIBvC8RkZkfOvWxqlX5LMXDrNfrk7K8ckkXtiyqTArkTmhFucHjFo4MAymlXR7OgrH0eSfcrGTU+VU3Fjt2EdkijecRC8nIRTvirlcav5C4I=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(39860400002)(136003)(376002)(346002)(396003)(46966006)(36840700001)(86362001)(7696005)(110136005)(2906002)(26005)(478600001)(336012)(8936002)(186003)(70206006)(70586007)(7636003)(1076003)(82310400003)(316002)(36756003)(82740400003)(55016002)(4326008)(426003)(36860700001)(83380400001)(356005)(6666004)(36906005)(5660300002)(47076005)(2616005)(107886003)(8676002)(16526019)(6286002)(54906003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 May 2021 09:50:29.4792 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 45089a82-bde6-4047-4d3f-08d90fab379e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT057.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR1201MB2521", "Subject": "[dpdk-dev] [PATCH v6 01/17] common/mlx5: add connection tracking\n object definition", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The structures of ASO connection tracking offload object are added\nbased on the definitions in the PRM. One CT object context will be\nloaded into the cache completely in a reversed order of dwords. The\nvalid bit should be the MSB of the last dword. This is used for the\nconntrack context creation and update, as well as for the query.\n\nThe capabilities 2 (HCA_CAP_2) layout is also added. The connection\ntracking related capabilities could be queried via the HCA_CAP_2.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 85 ++++++++++++++++++++++++++++++++++\n 1 file changed, 85 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 330101233a..683ab40338 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1124,6 +1124,7 @@ enum {\n \tMLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,\n+\tMLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,\n };\n \n #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \\\n@@ -1692,6 +1693,29 @@ struct mlx5_ifc_flow_table_nic_cap_bits {\n \t ft_field_support_2_nic_receive;\n };\n \n+struct mlx5_ifc_cmd_hca_cap_2_bits {\n+\tu8 reserved_at_0[0x80]; /* End of DW4. */\n+\tu8 reserved_at_80[0xb];\n+\tu8 log_max_num_reserved_qpn[0x5];\n+\tu8 reserved_at_90[0x3];\n+\tu8 log_reserved_qpn_granularity[0x5];\n+\tu8 reserved_at_98[0x3];\n+\tu8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */\n+\tu8 max_reformat_insert_size[0x8];\n+\tu8 max_reformat_insert_offset[0x8];\n+\tu8 max_reformat_remove_size[0x8];\n+\tu8 max_reformat_remove_offset[0x8]; /* End of DW6. */\n+\tu8 aso_conntrack_reg_id[0x8];\n+\tu8 reserved_at_c8[0x3];\n+\tu8 log_conn_track_granularity[0x5];\n+\tu8 reserved_at_d0[0x3];\n+\tu8 log_conn_track_max_alloc[0x5];\n+\tu8 reserved_at_d8[0x3];\n+\tu8 log_max_conn_track_offload[0x5];\n+\tu8 reserved_at_e0[0x20]; /* End of DW7. */\n+\tu8 reserved_at_100[0x700];\n+};\n+\n union mlx5_ifc_hca_cap_union_bits {\n \tstruct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;\n \tstruct mlx5_ifc_per_protocol_networking_offload_caps_bits\n@@ -2630,6 +2654,67 @@ struct mlx5_ifc_create_flow_meter_aso_in_bits {\n \tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n \tstruct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;\n };\n+\n+struct mlx5_ifc_tcp_window_params_bits {\n+\tu8 max_ack[0x20];\n+\tu8 max_win[0x20];\n+\tu8 reply_end[0x20];\n+\tu8 sent_end[0x20];\n+};\n+\n+struct mlx5_ifc_conn_track_aso_bits {\n+\tstruct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */\n+\tstruct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */\n+\tu8 last_end[0x20]; /* End of DW8. */\n+\tu8 last_ack[0x20]; /* End of DW9. */\n+\tu8 last_seq[0x20]; /* End of DW10. */\n+\tu8 last_win[0x10];\n+\tu8 reserved_at_170[0xa];\n+\tu8 last_dir[0x1];\n+\tu8 last_index[0x5]; /* End of DW11. */\n+\tu8 reserved_at_180[0x40]; /* End of DW13. */\n+\tu8 reply_direction_tcp_scale[0x4];\n+\tu8 reply_direction_tcp_close_initiated[0x1];\n+\tu8 reply_direction_tcp_liberal_enabled[0x1];\n+\tu8 reply_direction_tcp_data_unacked[0x1];\n+\tu8 reply_direction_tcp_max_ack[0x1];\n+\tu8 reserved_at_1c8[0x8];\n+\tu8 original_direction_tcp_scale[0x4];\n+\tu8 original_direction_tcp_close_initiated[0x1];\n+\tu8 original_direction_tcp_liberal_enabled[0x1];\n+\tu8 original_direction_tcp_data_unacked[0x1];\n+\tu8 original_direction_tcp_max_ack[0x1];\n+\tu8 reserved_at_1d8[0x8]; /* End of DW14. */\n+\tu8 valid[0x1];\n+\tu8 state[0x3];\n+\tu8 freeze_track[0x1];\n+\tu8 reserved_at_1e5[0xb];\n+\tu8 reserved_at_1f0[0x1];\n+\tu8 connection_assured[0x1];\n+\tu8 sack_permitted[0x1];\n+\tu8 challenged_acked[0x1];\n+\tu8 heartbeat[0x1];\n+\tu8 max_ack_window[0x3];\n+\tu8 reserved_at_1f8[0x1];\n+\tu8 retransmission_counter[0x3];\n+\tu8 retranmission_limit_exceeded[0x1];\n+\tu8 retranmission_limit[0x3]; /* End of DW15. */\n+};\n+\n+struct mlx5_ifc_conn_track_offload_bits {\n+\tu8 modify_field_select[0x40];\n+\tu8 reserved_at_40[0x40];\n+\tu8 reserved_at_80[0x8];\n+\tu8 conn_track_aso_access_pd[0x18];\n+\tu8 reserved_at_a0[0x160];\n+\tstruct mlx5_ifc_conn_track_aso_bits conn_track_aso;\n+};\n+\n+struct mlx5_ifc_create_conn_track_aso_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_conn_track_offload_bits conn_track_offload;\n+};\n+\n enum mlx5_access_aso_opc_mod {\n \tASO_OPC_MOD_IPSEC = 0x0,\n \tASO_OPC_MOD_CONNECTION_TRACKING = 0x1,\n", "prefixes": [ "v6", "01/17" ] }