Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/92801/?format=api
{ "id": 92801, "url": "http://patches.dpdk.org/api/patches/92801/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210505064104.30248-3-bingz@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210505064104.30248-3-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210505064104.30248-3-bingz@nvidia.com", "date": "2021-05-05T06:40:49", "name": "[v3,02/17] common/mlx5: add CT offload capability checking", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8d95d5481626871bc4fc08f7b7dcd46833268252", "submitter": { "id": 1976, "url": "http://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210505064104.30248-3-bingz@nvidia.com/mbox/", "series": [ { "id": 16817, "url": "http://patches.dpdk.org/api/series/16817/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16817", "date": "2021-05-05T06:40:47", "name": "conntrack support in mlx5 PMD", "version": 3, "mbox": "http://patches.dpdk.org/series/16817/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92801/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92801/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5D4B5A0524;\n\tWed, 5 May 2021 08:41:52 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4E1DC410E5;\n\tWed, 5 May 2021 08:41:52 +0200 (CEST)", "from NAM02-CY1-obe.outbound.protection.outlook.com\n (mail-eopbgr760057.outbound.protection.outlook.com [40.107.76.57])\n by mails.dpdk.org (Postfix) with ESMTP id EBF5E410E5\n for <dev@dpdk.org>; Wed, 5 May 2021 08:41:50 +0200 (CEST)", "from DM5PR2001CA0018.namprd20.prod.outlook.com (2603:10b6:4:16::28)\n by BY5PR12MB4968.namprd12.prod.outlook.com (2603:10b6:a03:1d2::14)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.35; Wed, 5 May\n 2021 06:41:49 +0000", "from DM6NAM11FT004.eop-nam11.prod.protection.outlook.com\n (2603:10b6:4:16:cafe::e1) by DM5PR2001CA0018.outlook.office365.com\n (2603:10b6:4:16::28) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.24 via Frontend\n Transport; Wed, 5 May 2021 06:41:49 +0000", "from mail.nvidia.com (216.228.112.34) by\n DM6NAM11FT004.mail.protection.outlook.com (10.13.172.217) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4108.25 via Frontend Transport; Wed, 5 May 2021 06:41:49 +0000", "from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 5 May\n 2021 06:41:42 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=UYUhan3BnfEoUjh3kbZLAzqv3u3yONXXSgXTrENh8Ep1D/dbygqwKzkOdMA1xuADDBzxOpF9WtfUzMk7J1uFUYHZeBkwjvSgFYi+KxCVCGeD4snHU8SOjXIQL4j+MUbfIqMRrgHzJe5HBVGtnzoaqeoJDKGRHvYsMdWaYjDY8hUfKQFjFwyWegrxWKgFGTtugD6qphtvphklAJWsMjDJfOYltIuP9AOLSlr/zZW+Qw191tRV9NtQe9z4JF9sH4JTacX5lrfTxo9Qo3riduyllDPmZ9pz3DTqcKy+sL/M3/J1Ea38SvuCzOyfCKqmTWPo4+Fnu05GQ0E/PeP54ZxwgA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=5uspStJGi7azuGBUFLAJhXBosm3Gerfwhq2gRdViM+E=;\n b=cgqr4ZQYUgf+gkS2WAGglOU28DAboesEsjc9eu8BX5zSqiVBVzoyKGeiOFMx60Qt4+D9T5Wo8dYTkQMnklNcH94ZR3tU+L3FDp6XQkc/txYy44FSGE+YJUTd8omAKXOzKxuQfXifuqzRwjwDiC/7WhL0h0dHCtipM/i+6TLNcdgLc5lJjbalEQ5QBqmC6fneyj0RtppNw7z7QgdIUNdR7EOSJgAxU0mjhWRZndl8R8sQFxp8mkNv56NwUC5xYFopnHmmvCvAthExpRMYVxXB61qdE3ufGR/rGPVwSQEWGkyQC4I+7s+2RLJjgG2N54Ju1268k3sAFpezG7hijX2bAQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=5uspStJGi7azuGBUFLAJhXBosm3Gerfwhq2gRdViM+E=;\n b=KsQb+zi4anSwZrZIAzneU8WOV+slLQcJeseVOeewtNG7BjhimVfybB0TD7J+/11TqlS2WwbvMlWA3c4yjwJlHTbtV2wIYQMBiOfR4GPKu7AjNKqKQ88g9NKBnrBmYP2kGFYrWFcdCqlC+bONwz88AQfrik/+gPro/qN9lPVAaqinGsMa5c6TNt7dBeoTGYrjTB4jIkfSeop5Bc9AIieAzNgZn7lqx0GEy93ViIfRWXi53iOzbDDxckQj03rENVbrPZObGRF1ZD8M3RVBnvX7GDHI0nybBkf7Pcb793DvUvZrcfz11WE6kqbNMOa9V/rCAewdmPrb2e4q0auTCebz8g==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>, <thomas@monjalon.net>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, <rasland@nvidia.com>", "Date": "Wed, 5 May 2021 09:40:49 +0300", "Message-ID": "<20210505064104.30248-3-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210505064104.30248-1-bingz@nvidia.com>", "References": "<20210427153811.11554-1-bingz@nvidia.com>\n <20210505064104.30248-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL105.nvidia.com (172.20.187.12) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "2b27c684-9ae9-4934-ec8f-08d90f90dc34", "X-MS-TrafficTypeDiagnostic": "BY5PR12MB4968:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BY5PR12MB496855C1AA631F50BEA8D9C8D0599@BY5PR12MB4968.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:6108;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n eUJnlio09c9TRNrfCB0fUcKCL0nPhAW/fkGldgCd9BArc9pbArQzURmmtkgI0xB+ujcwe4p8GoCIYXt3gU31a7tTxz6SypsuSJI2u8rrQhTrWourSK3gJpjLjTrFZbgaROMRkvjAdygyRnQAniLR0mEGDh+m732clCeIhoRpVBJkJtJAir2GVN16mUTdr11Yw1eWxtCqZT/BFyDRVEt/M3jltbZysL6iP4+Bael1S4arTjUtBfbCMPSSkNLQcfoBnrjTrxbN7x3QlvyOoAhr8Foh3hNK8sX2diyOCbyW7O9eu4kXgENt5/EbAmWO3rzhwg2l7HdT7icRF7aobw7aNUi0TJQnuVLVpwhbxpgNjsheGuK915vlb94AMlp4oewk2IkUsdgjDrTQQq8+zRnMowJYsHm6g4Zy3IrkEDpmNS52XBF1FtOZV17cAVk7ccjH+v+04DSb0QXtskkPAENG1qf9cFwAYZMXSQlb+3dJWrBREfWqGJl6zczaABlYlXoOyt51IGizRdJ1pUGoFujr4zWm8Cy7RqLy84guv8TVoJCetJG1j6aRGgE41eI7mTY3SW5LmxPZWRD3cAXlq+umXGCUcY++FSmAmbiZxGLyhwkvSV4lJ6Topu0LQWhwV4VXIwn5KSCm4SVy+OxpUf82MPjTE5c0X3ygcgAvvyWmEEk=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(136003)(39860400002)(396003)(376002)(36840700001)(46966006)(107886003)(36906005)(54906003)(5660300002)(316002)(7696005)(8676002)(70586007)(70206006)(16526019)(6286002)(82310400003)(8936002)(86362001)(1076003)(83380400001)(110136005)(26005)(7636003)(426003)(478600001)(36860700001)(2616005)(36756003)(82740400003)(47076005)(2906002)(336012)(186003)(55016002)(356005)(4326008);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 May 2021 06:41:49.2619 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2b27c684-9ae9-4934-ec8f-08d90f90dc34", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT004.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB4968", "Subject": "[dpdk-dev] [PATCH v3 02/17] common/mlx5: add CT offload capability\n checking", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "During startup, the ASO connection tracking offload capability could\nbe queried via HCA_CAP_QUERY command. If the HW doesn't support ASO\nCT, the value would be 0 by default. The following initialization\nshould be skipped and the creation of the CT object should return\na failure directly.\n\nThe following CT creation should also check this capability. With\nthe old driver, the pre-processing macro should be used in order to\nmake the compiling pass.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/common/mlx5/linux/meson.build | 2 ++\n drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n drivers/common/mlx5/mlx5_prm.h | 3 +++\n 4 files changed, 9 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build\nindex 3334bd5cb2..007834a49b 100644\n--- a/drivers/common/mlx5/linux/meson.build\n+++ b/drivers/common/mlx5/linux/meson.build\n@@ -189,6 +189,8 @@ has_sym_args = [\n 'MLX5_WQE_UMR_CTRL_FLAG_INLINE' ],\n [ 'HAVE_MLX5_DR_FLOW_DUMP_RULE', 'infiniband/mlx5dv.h',\n 'mlx5dv_dump_dr_rule' ],\n+ [ 'HAVE_MLX5_DR_ACTION_ASO_CT', 'infiniband/mlx5dv.h',\n+ 'MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR' ],\n ]\n config = configuration_data()\n foreach arg:has_sym_args\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 79fff6457c..ad67883fde 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -760,6 +760,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\tMLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);\n \tattr->umr_modify_entity_size_disabled =\n \t\tMLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);\n+\tattr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n+\t\t\t\t\t general_obj_types) &\n+\t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);\n \tif (attr->qos.sup) {\n \t\tMLX5_SET(query_hca_cap_in, in, op_mod,\n \t\t\t MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 870bdb6b30..746320cf04 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -137,6 +137,7 @@ struct mlx5_hca_attr {\n \tuint32_t qp_ts_format:2;\n \tuint32_t regex:1;\n \tuint32_t reg_c_preserve:1;\n+\tuint32_t ct_offload:1; /* General obj type ASO CT offload supported. */\n \tuint32_t regexp_num_of_engines;\n \tuint32_t log_max_ft_sampler_num:8;\n \tuint32_t geneve_tlv_opt;\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 4da89d3379..71bdf43668 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1134,6 +1134,8 @@ enum {\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)\n #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \\\n \t\t\t(1ULL << MLX5_OBJ_TYPE_GENEVE_TLV_OPT)\n+#define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \\\n+\t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD)\n \n enum {\n \tMLX5_HCA_CAP_OPMOD_GET_MAX = 0,\n@@ -2456,6 +2458,7 @@ enum {\n \tMLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,\n \tMLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,\n \tMLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,\n+\tMLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031,\n };\n \n struct mlx5_ifc_general_obj_in_cmd_hdr_bits {\n", "prefixes": [ "v3", "02/17" ] }