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GET /api/patches/92771/?format=api
{ "id": 92771, "url": "http://patches.dpdk.org/api/patches/92771/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210504210857.3398397-12-matan@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210504210857.3398397-12-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210504210857.3398397-12-matan@nvidia.com", "date": "2021-05-04T21:08:53", "name": "[v3,11/15] crypto/mlx5: add maximum segments device argument", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "52f5e9462c138847167d5b9bd2100a914ecdb7d0", "submitter": { "id": 1911, "url": "http://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210504210857.3398397-12-matan@nvidia.com/mbox/", "series": [ { "id": 16812, "url": "http://patches.dpdk.org/api/series/16812/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16812", "date": "2021-05-04T21:08:42", "name": "drivers: introduce mlx5 crypto PMD", "version": 3, "mbox": "http://patches.dpdk.org/series/16812/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92771/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92771/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EC0C9A0A02;\n\tTue, 4 May 2021 23:10:47 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3B4E541101;\n\tTue, 4 May 2021 23:09:48 +0200 (CEST)", "from NAM02-BN1-obe.outbound.protection.outlook.com\n (mail-bn1nam07on2072.outbound.protection.outlook.com [40.107.212.72])\n by mails.dpdk.org (Postfix) with ESMTP id 688FE4114C\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>", "Date": "Wed, 5 May 2021 00:08:53 +0300", "Message-ID": "<20210504210857.3398397-12-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210504210857.3398397-1-matan@nvidia.com>", "References": "<20210429154712.2820159-1-matan@nvidia.com>\n <20210504210857.3398397-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "64fc08a7-8147-4158-508c-08d90f40eff9", "X-MS-TrafficTypeDiagnostic": "BY5PR12MB3761:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BY5PR12MB37612D0F6CF1CFE67A783715DF5A9@BY5PR12MB3761.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:193;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n HFEnqeh5+7T8Kqj+F61li16e2uo0ydajltkJly23gm8vJY2qnSE744d1c7v9+QbS1uwyhhaC3gdHmLhVo0AMB5M4I5LjhIIt4F997+TuOkabUVif2Mu7SEQdIts6AD0Dsn8AU7zFo64uk8n0ZXUMcupFEnao4DFZEuseGnON8QEhaIPVlgCcJKxoj30tEmYYVAzS9X8bp2S53lPWqZEfJhrAyFIxWDC/chuOyOlN5ItIwfz2JH9YOKIL4c6wTAtnAmzgWavnCvdHPOhJG7BmLWKyOqulSdy46jRtWSBvTpWGgggMxcMYGElq5+HixnKS5ASnhz8uQNAPsQLbv0QTnxtKY8dgacJrUcRfSpHTFVNAhh20R9ChRA50auNYz0deiJ8tnxkYes2ojxiwrjbU5Q4GsJBqsvqQ+tHa5/LsSnOcDyhleGJCnHOyk7jSGMZGovyvrKVdOFn5ErQvJ2akTiEO8hRE78m8CTdWo2Oz4VYkq3S+ZA41fn2jlJFDVY3lWKZ0jkGYz/S2LnhwuzmoykceOadJnPbLn0MiBrvFRrzVMby06sGwrzbRLMxD4lMfmCah4Nr7e1xPYZdAK7vz+unycB8DJM2axX3z7EIl4MyRWRWA1tgoKf6XE2OPI/lvBYYSymYu+V61TrPlSy2wl/h0Glkfr++wnMKSbATYhO0=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(136003)(396003)(376002)(39860400002)(36840700001)(46966006)(8936002)(54906003)(316002)(356005)(86362001)(2616005)(70586007)(1076003)(16526019)(36906005)(7696005)(7636003)(2906002)(36756003)(83380400001)(82740400003)(426003)(6916009)(47076005)(336012)(82310400003)(8676002)(6286002)(186003)(5660300002)(4326008)(6666004)(55016002)(26005)(478600001)(36860700001)(70206006);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 May 2021 21:09:42.6064 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 64fc08a7-8147-4158-508c-08d90f40eff9", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT007.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB3761", "Subject": "[dpdk-dev] [PATCH v3 11/15] crypto/mlx5: add maximum segments\n device argument", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Suanming Mou <suanmingm@nvidia.com>\n\nThe mlx5 HW crypto operations are done by attaching crypto property\nto a memory region. Once done, every access to the memory via the\ncrypto-enabled memory region will result with in-line encryption or\ndecryption of the data.\n\nAs a result, the design choice is to provide two types of WQEs. One\nis UMR WQE which sets the crypto property and the other is rdma write\nWQE which sends DMA command to copy data from local MR to remote MR.\n\nThe size of the WQEs will be defined by a new devarg called\nmax_segs_num.\n\nThis devarg also defines the maximum segments in mbuf chain that will be\nsupported for crypto operations.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nSigned-off-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 35 +++++++++++++++++++++++++++----\n drivers/crypto/mlx5/mlx5_crypto.h | 7 +++++++\n 2 files changed, 38 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 73cca8136b..6de44398bd 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -21,6 +21,7 @@\n #define MLX5_CRYPTO_DRIVER_NAME mlx5_crypto\n #define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5\n #define MLX5_CRYPTO_MAX_QPS 1024\n+#define MLX5_CRYPTO_MAX_SEGS 56\n \n TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list =\n \t\t\t\tTAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list);\n@@ -464,14 +465,24 @@ mlx5_crypto_args_check_handler(const char *key, const char *val, void *opaque)\n \t\tDRV_LOG(WARNING, \"%s: \\\"%s\\\" is an invalid integer.\", key, val);\n \t\treturn -errno;\n \t}\n-\tif (strcmp(key, \"import_kek_id\") == 0)\n+\tif (strcmp(key, \"max_segs_num\") == 0) {\n+\t\tif (!tmp || tmp > MLX5_CRYPTO_MAX_SEGS) {\n+\t\t\tDRV_LOG(WARNING, \"Invalid max_segs_num: %d, should\"\n+\t\t\t\t\" be less than %d.\",\n+\t\t\t\t(uint32_t)tmp, MLX5_CRYPTO_MAX_SEGS);\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t\tdevarg_prms->max_segs_num = (uint32_t)tmp;\n+\t} else if (strcmp(key, \"import_kek_id\") == 0) {\n \t\tattr->session_import_kek_ptr = (uint32_t)tmp;\n-\telse if (strcmp(key, \"credential_id\") == 0)\n+\t} else if (strcmp(key, \"credential_id\") == 0) {\n \t\tattr->credential_pointer = (uint32_t)tmp;\n-\telse if (strcmp(key, \"keytag\") == 0)\n+\t} else if (strcmp(key, \"keytag\") == 0) {\n \t\tdevarg_prms->keytag = tmp;\n-\telse\n+\t} else {\n \t\tDRV_LOG(WARNING, \"Invalid key %s.\", key);\n+\t}\n \treturn 0;\n }\n \n@@ -486,6 +497,7 @@ mlx5_crypto_parse_devargs(struct rte_devargs *devargs,\n \tattr->credential_pointer = 0;\n \tattr->session_import_kek_ptr = 0;\n \tdevarg_prms->keytag = 0;\n+\tdevarg_prms->max_segs_num = 8;\n \tif (devargs == NULL) {\n \t\tDRV_LOG(ERR,\n \t\"No login devargs in order to enable crypto operations in the device.\");\n@@ -626,6 +638,21 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \tpriv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;\n \tpriv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;\n \tpriv->keytag = rte_cpu_to_be_64(devarg_prms.keytag);\n+\tpriv->max_segs_num = devarg_prms.max_segs_num;\n+\tpriv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) +\n+\t\t\t sizeof(struct mlx5_umr_wqe) +\n+\t\t\t RTE_ALIGN(priv->max_segs_num, 4) *\n+\t\t\t sizeof(struct mlx5_wqe_dseg);\n+\tpriv->rdmw_wqe_size = sizeof(struct mlx5_rdma_write_wqe) +\n+\t\t\t sizeof(struct mlx5_wqe_dseg) *\n+\t\t\t (priv->max_segs_num <= 2 ? 2 : 2 +\n+\t\t\t RTE_ALIGN(priv->max_segs_num - 2, 4));\n+\tpriv->wqe_set_size = priv->umr_wqe_size + priv->rdmw_wqe_size;\n+\tpriv->wqe_stride = (priv->umr_wqe_size + priv->rdmw_wqe_size) /\n+\t\t\t\t\t\t\t MLX5_SEND_WQE_BB;\n+\tpriv->max_rdmaw_klm_n = (priv->rdmw_wqe_size -\n+\t\t\t\t sizeof(struct mlx5_rdma_write_wqe)) /\n+\t\t\t\t sizeof(struct mlx5_wqe_dseg);\n \tpthread_mutex_lock(&priv_list_lock);\n \tTAILQ_INSERT_TAIL(&mlx5_crypto_priv_list, priv, next);\n \tpthread_mutex_unlock(&priv_list_lock);\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 34c65f9a24..81452bd700 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -25,12 +25,18 @@ struct mlx5_crypto_priv {\n \tstruct rte_cryptodev *crypto_dev;\n \tvoid *uar; /* User Access Region. */\n \tuint32_t pdn; /* Protection Domain number. */\n+\tuint32_t max_segs_num; /* Maximum supported data segs. */\n \tstruct ibv_pd *pd;\n \tstruct mlx5_hlist *dek_hlist; /* Dek hash list. */\n \tstruct rte_cryptodev_config dev_config;\n \tstruct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */\n \tstruct mlx5_devx_obj *login_obj;\n \tuint64_t keytag;\n+\tuint16_t wqe_set_size;\n+\tuint16_t umr_wqe_size;\n+\tuint16_t rdmw_wqe_size;\n+\tuint16_t wqe_stride;\n+\tuint16_t max_rdmaw_klm_n;\n };\n \n struct mlx5_crypto_qp {\n@@ -54,6 +60,7 @@ struct mlx5_crypto_devarg_params {\n \tbool login_devarg;\n \tstruct mlx5_devx_crypto_login_attr login_attr;\n \tuint64_t keytag;\n+\tuint32_t max_segs_num;\n };\n \n int\n", "prefixes": [ "v3", "11/15" ] }