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GET /api/patches/92770/?format=api
{ "id": 92770, "url": "http://patches.dpdk.org/api/patches/92770/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210504210857.3398397-10-matan@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210504210857.3398397-10-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210504210857.3398397-10-matan@nvidia.com", "date": "2021-05-04T21:08:51", "name": "[v3,09/15] crypto/mlx5: adjust to the multiple data unit API", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "69eefa2711b2361e2c800e628ef2d0c41fee7060", "submitter": { "id": 1911, "url": "http://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210504210857.3398397-10-matan@nvidia.com/mbox/", "series": [ { "id": 16812, "url": "http://patches.dpdk.org/api/series/16812/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16812", "date": "2021-05-04T21:08:42", "name": "drivers: introduce mlx5 crypto PMD", "version": 3, "mbox": "http://patches.dpdk.org/series/16812/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92770/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92770/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 03E21A0A02;\n\tTue, 4 May 2021 23:10:41 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B3E2741145;\n\tTue, 4 May 2021 23:09:45 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2055.outbound.protection.outlook.com [40.107.236.55])\n by mails.dpdk.org (Postfix) with ESMTP id A42E541131\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>, Shiri Kuzin <shirik@nvidia.com>", "Date": "Wed, 5 May 2021 00:08:51 +0300", "Message-ID": "<20210504210857.3398397-10-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210504210857.3398397-1-matan@nvidia.com>", "References": "<20210429154712.2820159-1-matan@nvidia.com>\n <20210504210857.3398397-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "ceda3474-e291-497a-a955-08d90f40ede5", "X-MS-TrafficTypeDiagnostic": "CY4PR12MB1688:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <CY4PR12MB16887623094A9301D6C3260DDF5A9@CY4PR12MB1688.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:7691;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n z9VSKxsAlofuUlHtHl/SNzbZjuOlIdEcxrB2CzKx8lh+wYWswhrclU+zZgc8Aw059jJsrqjbNkFy6WSfxH1uvp0m7PuDftRV5Ll4kTcEMsf7DW63M0x25qia41X3Sjmb4rkPbskBdGeZZsDee41JpPXFg2wVN0rAlB+BlHmYL6adHO9MXCGEBq7WJiIRHIgkAt9lXMrdRl26qQ+vcWCD2TuAMFoExPV/z4JoyrR8jT+jOCBnGhMUuzQL+fwx9FlM0kjuU5Hjzvvv5cx8gSrUizW0OWY2assxasdVs9jdjbCY7avU4z7Lx8sCCD6E5gF0V201sRpLoA5Ye/+TvNK/xW17sAAP4uuWgoSrKZvNUJr+s8YBHOXLPxT5128qQ8k8Q0gWlUmqvurmxXJJwp83QwUGs7BqtaHgroj5yYOz9Thmv9TYiKIopsqyo8Ujhj9cpfrfiFl1UggSCK74jsGr8cvFzVvdMkMeSybRgGsgDSmD4zkYVZ6DqhZtCGdEkqw1rfHFPy6CPCbxwBnrLEAZmGK+yLbfihm6xMLsKMTzR7bmBCr1s4PR1DuxXF8+YbG6CkS+P7E1gzehY3CkpkYWk4fRhfibKhIV4Rpjm6iGivEiHFaQQBWPZ6Wcm7StTEVnU/HWOHJeEOhJ05TbOEW29FEhblRXI28uPFSKhUiZ9MYSsWlGpktVVurXgFi4ChWT2pUrxrl/pu+yyFDEE02IK2wzciHi2zLRgK+xqx4CI5o=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(136003)(376002)(346002)(39860400002)(396003)(36840700001)(46966006)(86362001)(5660300002)(7696005)(2906002)(36756003)(82740400003)(47076005)(6666004)(1076003)(8676002)(7636003)(8936002)(36860700001)(70206006)(70586007)(82310400003)(6286002)(316002)(6916009)(478600001)(55016002)(83380400001)(966005)(26005)(2616005)(54906003)(36906005)(4326008)(16526019)(186003)(426003)(336012)(107886003)(356005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 May 2021 21:09:39.1391 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ceda3474-e291-497a-a955-08d90f40ede5", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT056.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR12MB1688", "Subject": "[dpdk-dev] [PATCH v3 09/15] crypto/mlx5: adjust to the multiple\n data unit API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shiri Kuzin <shirik@nvidia.com>\n\nIn AES-XTS the data to be encrypted\\decrypted does not have to be\nin multiples of 16B size, the unit of data is called data-unit.\n\nAs a result of patch [1] a new field is added to the cipher capability,\ncalled dataunit_set, where the devices can report the range of\nsupported data-unit sizes.\n\nThe new field enables saving the data-unit size in the session\nstructure to the block size pointer variable in order to support\nseveral data-unit sizes.\n\n[1] https://www.mail-archive.com/dev@dpdk.org/msg205337.html\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 23 +++++++++++++++++++++++\n 1 file changed, 23 insertions(+)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 18b1a6be88..8cc29ced21 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -48,6 +48,11 @@ struct mlx5_crypto_session {\n \t * bsf_size, bsf_p_type, encryption_order and encryption standard,\n \t * saved in big endian format.\n \t */\n+\tuint32_t bsp_res;\n+\t/*\n+\t * crypto_block_size_pointer and reserved 24 bits saved in big endian\n+\t * format.\n+\t */\n \tuint32_t iv_offset:16;\n \t/* Starting point for Initialisation Vector. */\n \tstruct mlx5_crypto_dek *dek; /* Pointer to dek struct. */\n@@ -171,6 +176,24 @@ mlx5_crypto_sym_session_configure(struct rte_cryptodev *dev,\n \t\t\t MLX5_BSF_P_TYPE_CRYPTO << MLX5_BSF_P_TYPE_OFFSET |\n \t\t\t encryption_order << MLX5_ENCRYPTION_ORDER_OFFSET |\n \t\t\t MLX5_ENCRYPTION_STANDARD_AES_XTS);\n+\tswitch (xform->cipher.dataunit_len) {\n+\tcase 0:\n+\t\tsess_private_data->bsp_res = 0;\n+\t\tbreak;\n+\tcase 512:\n+\t\tsess_private_data->bsp_res = rte_cpu_to_be_32\n+\t\t\t\t\t ((uint32_t)MLX5_BLOCK_SIZE_512B <<\n+\t\t\t\t\t MLX5_BLOCK_SIZE_OFFSET);\n+\t\tbreak;\n+\tcase 4096:\n+\t\tsess_private_data->bsp_res = rte_cpu_to_be_32\n+\t\t\t\t\t ((uint32_t)MLX5_BLOCK_SIZE_4096B <<\n+\t\t\t\t\t MLX5_BLOCK_SIZE_OFFSET);\n+\t\tbreak;\n+\tdefault:\n+\t\tDRV_LOG(ERR, \"Cipher data unit length is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n \tsess_private_data->iv_offset = cipher->iv.offset;\n \tsess_private_data->dek_id =\n \t\t\trte_cpu_to_be_32(sess_private_data->dek->obj->id &\n", "prefixes": [ "v3", "09/15" ] }