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GET /api/patches/92769/?format=api
{ "id": 92769, "url": "http://patches.dpdk.org/api/patches/92769/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210504210857.3398397-11-matan@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210504210857.3398397-11-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210504210857.3398397-11-matan@nvidia.com", "date": "2021-05-04T21:08:52", "name": "[v3,10/15] crypto/mlx5: add keytag device argument", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "c4b914f03e617ade0da1c5aba94bd2329fe40646", "submitter": { "id": 1911, "url": "http://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210504210857.3398397-11-matan@nvidia.com/mbox/", "series": [ { "id": 16812, "url": "http://patches.dpdk.org/api/series/16812/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16812", "date": "2021-05-04T21:08:42", "name": "drivers: introduce mlx5 crypto PMD", "version": 3, "mbox": "http://patches.dpdk.org/series/16812/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92769/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92769/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2BCE4A0A02;\n\tTue, 4 May 2021 23:10:35 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 776B941142;\n\tTue, 4 May 2021 23:09:44 +0200 (CEST)", "from NAM04-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam08on2078.outbound.protection.outlook.com [40.107.101.78])\n by mails.dpdk.org (Postfix) with ESMTP id 2389D41131\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>", "Date": "Wed, 5 May 2021 00:08:52 +0300", "Message-ID": "<20210504210857.3398397-11-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210504210857.3398397-1-matan@nvidia.com>", "References": "<20210429154712.2820159-1-matan@nvidia.com>\n <20210504210857.3398397-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "b795d6b4-91a6-41f3-15e9-08d90f40ef12", "X-MS-TrafficTypeDiagnostic": "BL1PR12MB5350:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BL1PR12MB5350D4E0C14E2B17F5352044DF5A9@BL1PR12MB5350.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:125;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n U5WwrShSCNPTNDWYpKBW3tQomPt56NuLwjAh9yIw2SZX0l4sqM9y1upzfTs5f7uXDw67zv6H1E4s0ju3jfaoYnGW5io5RuANkafzJqhqkKdCPkx4lRjB24Xng9vaOSFeEDSvGDcwecu6C1pZUU6dMTCyCKbBVOuKHB5RHqciKY3VZiZLI2V2IixBSkixKvSJVyHciJJ6Uj0115bAqeYqBWahnuCINvTcwaEdu0JpSQkOLFyIlwmCppNUqcIQgIyFLUrd3KEQ+xpoUIMxZsrvAfVmOpFGbyCILOj4veFuk0/Jm7sbEP5D4BtVtliFebE8lFvsVKH2rRLuepA20S9AVbNt3UoMLwxcifn0CtB3UZduuRZ2/uoN6WxYPdXIlCFF0IbCU/csUPMJQksVuQg4p0psM0d1pNuuIKk2rCo2ThF86uVPp0smqWMqsDzW+ZidYPeUL3nUyTy4TwbdGBwmbM+FeBpVhOD1u8ZHL3qvmYE94K0nuDX9Er6D4vSln9GKAfHknuqAG0htx/Dv4HpFtOZ+zH22M+fWuZI4xMx7zVaTtcFVSD9VaO2nmk156HDPyMchuY5EBwErKXZGzq83tOQNnu0FxGJYR09CR5BunOJsjS8/65gl6syY1ad7UvfZNtbmGwZdXOYqkuXFFgPGNyacJS6hfnJXbI+cVvBj8Ro=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(396003)(376002)(346002)(136003)(39860400002)(46966006)(36840700001)(83380400001)(186003)(70206006)(2906002)(16526019)(4326008)(5660300002)(36756003)(70586007)(26005)(6286002)(336012)(6916009)(86362001)(426003)(8676002)(356005)(8936002)(1076003)(82740400003)(55016002)(47076005)(36860700001)(54906003)(36906005)(82310400003)(7636003)(316002)(6666004)(7696005)(2616005)(478600001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 May 2021 21:09:41.1759 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b795d6b4-91a6-41f3-15e9-08d90f40ef12", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT056.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL1PR12MB5350", "Subject": "[dpdk-dev] [PATCH v3 10/15] crypto/mlx5: add keytag device argument", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Suanming Mou <suanmingm@nvidia.com>\n\nA keytag is a piece of data encrypted together with a DEK.\n\nWhen a DEK is referenced by an MKEY.bsf through its index, the keytag is\nalso supplied in the BSF as plaintext. The HW will decrypt the DEK (and\nthe attached keytag) and will fail the operation if the keytags don't\nmatch.\n\nThis commit adds the configuration of the keytag with devargs.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nSigned-off-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 50 +++++++++++++++++--------------\n drivers/crypto/mlx5/mlx5_crypto.h | 3 +-\n 2 files changed, 30 insertions(+), 23 deletions(-)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 8cc29ced21..73cca8136b 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -468,56 +468,52 @@ mlx5_crypto_args_check_handler(const char *key, const char *val, void *opaque)\n \t\tattr->session_import_kek_ptr = (uint32_t)tmp;\n \telse if (strcmp(key, \"credential_id\") == 0)\n \t\tattr->credential_pointer = (uint32_t)tmp;\n+\telse if (strcmp(key, \"keytag\") == 0)\n+\t\tdevarg_prms->keytag = tmp;\n \telse\n \t\tDRV_LOG(WARNING, \"Invalid key %s.\", key);\n \treturn 0;\n }\n \n-static struct mlx5_devx_obj *\n-mlx5_crypto_config_login(struct rte_devargs *devargs,\n-\t\t\t struct ibv_context *ctx)\n+static int\n+mlx5_crypto_parse_devargs(struct rte_devargs *devargs,\n+\t\t\t struct mlx5_crypto_devarg_params *devarg_prms)\n {\n-\t/*\n-\t * Set credential pointer and session import KEK pointer to a default\n-\t * value of 0.\n-\t */\n-\tstruct mlx5_crypto_devarg_params login = {\n-\t\t\t.login_devarg = false,\n-\t\t\t.login_attr = {\n-\t\t\t\t\t.credential_pointer = 0,\n-\t\t\t\t\t.session_import_kek_ptr = 0,\n-\t\t\t}\n-\t};\n+\tstruct mlx5_devx_crypto_login_attr *attr = &devarg_prms->login_attr;\n \tstruct rte_kvargs *kvlist;\n \n+\t/* Default values. */\n+\tattr->credential_pointer = 0;\n+\tattr->session_import_kek_ptr = 0;\n+\tdevarg_prms->keytag = 0;\n \tif (devargs == NULL) {\n \t\tDRV_LOG(ERR,\n \t\"No login devargs in order to enable crypto operations in the device.\");\n \t\trte_errno = EINVAL;\n-\t\treturn NULL;\n+\t\treturn -1;\n \t}\n \tkvlist = rte_kvargs_parse(devargs->args, NULL);\n \tif (kvlist == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to parse devargs.\");\n \t\trte_errno = EINVAL;\n-\t\treturn NULL;\n+\t\treturn -1;\n \t}\n \tif (rte_kvargs_process(kvlist, NULL, mlx5_crypto_args_check_handler,\n-\t\t\t &login) != 0) {\n+\t\t\t devarg_prms) != 0) {\n \t\tDRV_LOG(ERR, \"Devargs handler function Failed.\");\n \t\trte_kvargs_free(kvlist);\n \t\trte_errno = EINVAL;\n-\t\treturn NULL;\n+\t\treturn -1;\n \t}\n \trte_kvargs_free(kvlist);\n-\tif (login.login_devarg == false) {\n+\tif (devarg_prms->login_devarg == false) {\n \t\tDRV_LOG(ERR,\n \t\"No login credential devarg in order to enable crypto operations \"\n \t\"in the device.\");\n \t\trte_errno = EINVAL;\n-\t\treturn NULL;\n+\t\treturn -1;\n \t}\n-\treturn mlx5_devx_cmd_create_crypto_login_obj(ctx, &login.login_attr);\n+\treturn 0;\n }\n \n /**\n@@ -543,6 +539,7 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \tstruct ibv_context *ctx;\n \tstruct mlx5_devx_obj *login;\n \tstruct mlx5_crypto_priv *priv;\n+\tstruct mlx5_crypto_devarg_params devarg_prms = { 0 };\n \tstruct mlx5_hca_attr attr = { 0 };\n \tstruct rte_cryptodev_pmd_init_params init_params = {\n \t\t.name = \"\",\n@@ -551,6 +548,8 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \t\t.max_nb_queue_pairs =\n \t\t\t\tRTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS,\n \t};\n+\tint ret;\n+\n \tRTE_SET_USED(pci_drv);\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n \t\tDRV_LOG(ERR, \"Non-primary process type is not supported.\");\n@@ -580,7 +579,13 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \t\trte_errno = ENOTSUP;\n \t\treturn -ENOTSUP;\n \t}\n-\tlogin = mlx5_crypto_config_login(pci_dev->device.devargs, ctx);\n+\tret = mlx5_crypto_parse_devargs(pci_dev->device.devargs, &devarg_prms);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to parse devargs.\");\n+\t\treturn -rte_errno;\n+\t}\n+\tlogin = mlx5_devx_cmd_create_crypto_login_obj(ctx,\n+\t\t\t\t\t\t &devarg_prms.login_attr);\n \tif (login == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to configure login.\");\n \t\treturn -rte_errno;\n@@ -620,6 +625,7 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \t}\n \tpriv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;\n \tpriv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;\n+\tpriv->keytag = rte_cpu_to_be_64(devarg_prms.keytag);\n \tpthread_mutex_lock(&priv_list_lock);\n \tTAILQ_INSERT_TAIL(&mlx5_crypto_priv_list, priv, next);\n \tpthread_mutex_unlock(&priv_list_lock);\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 0aef804b92..34c65f9a24 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -30,6 +30,7 @@ struct mlx5_crypto_priv {\n \tstruct rte_cryptodev_config dev_config;\n \tstruct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */\n \tstruct mlx5_devx_obj *login_obj;\n+\tuint64_t keytag;\n };\n \n struct mlx5_crypto_qp {\n@@ -49,10 +50,10 @@ struct mlx5_crypto_dek {\n \tbool size_is_48; /* Whether the key\\data size is 48 bytes or not. */\n };\n \n-\n struct mlx5_crypto_devarg_params {\n \tbool login_devarg;\n \tstruct mlx5_devx_crypto_login_attr login_attr;\n+\tuint64_t keytag;\n };\n \n int\n", "prefixes": [ "v3", "10/15" ] }