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GET /api/patches/92764/?format=api
{ "id": 92764, "url": "http://patches.dpdk.org/api/patches/92764/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210504210857.3398397-5-matan@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210504210857.3398397-5-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210504210857.3398397-5-matan@nvidia.com", "date": "2021-05-04T21:08:46", "name": "[v3,04/15] crypto/mlx5: add basic operations", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "010fcf3065e5885566c4a88aa93d096284ff58bc", "submitter": { "id": 1911, "url": "http://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210504210857.3398397-5-matan@nvidia.com/mbox/", "series": [ { "id": 16812, "url": "http://patches.dpdk.org/api/series/16812/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16812", "date": "2021-05-04T21:08:42", "name": "drivers: introduce mlx5 crypto PMD", "version": 3, "mbox": "http://patches.dpdk.org/series/16812/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92764/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92764/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 357FCA0A02;\n\tTue, 4 May 2021 23:09:57 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A7EB841103;\n\tTue, 4 May 2021 23:09:34 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2087.outbound.protection.outlook.com [40.107.244.87])\n by mails.dpdk.org (Postfix) with ESMTP id DF540410E9\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>, Shiri Kuzin <shirik@nvidia.com>", "Date": "Wed, 5 May 2021 00:08:46 +0300", "Message-ID": "<20210504210857.3398397-5-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210504210857.3398397-1-matan@nvidia.com>", "References": "<20210429154712.2820159-1-matan@nvidia.com>\n <20210504210857.3398397-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "71623cfb-618c-408f-bd1f-08d90f40e889", "X-MS-TrafficTypeDiagnostic": "BN9PR12MB5323:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BN9PR12MB5323B8385F25C112AB29E4F4DF5A9@BN9PR12MB5323.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:4941;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n /TmArQkCk5Jgntk2wK8Lkpy9Ou6KVXqtanHkTl79EtbWGGH6nBnXfRK08otdgIJ+DcrTMqdvO+YZwo7pd8lGF0p7dQ+bTquoRfaHX/rMkfAMuWQft0nwUDIL2XiKwTnvb6i+PwrHbGVQi37QsStIZgsgjKPv/iVqQ5erwcMJXrd+U2NXkQlOY22DvKck8GQKE5MuVMGkPAJsU2baLENyo0AN4JpOty6nzq1InJtYDs+s6CM8CjE0NMUlqIEbrsMs90dRrb2HQ1qvFWLFPcc2uogdNLzzSzXHHb7quVPKIqc9jZN4trOyr8oZxxCQ+fMEUAroBUHnukaiyGz8xigO0B9ULjPiDjKm64Ba5/vi053IPk+EUhRp2pYJv/nXKFGrgfXNFVUAYQGUvUA2nUEhkLhM2Ks8UtZXHmqVCfRHXo5ShBJsXqC2GeR+HNdCBB7UBl6HXihcuLc46V7443nCSJetE2HeGfEkf4LBUGZJxjo8+GdY5QpXUT7zg0sOmGakfVNi6bci8UUWiv/8bnbHYG/5LDht6xU64mvc3o4ZDKi+4p/kFYdPjjnNz1UcViZgy4mt3jX+JkmL/MGIO+I9YYCQF6TJTf3aeH9oqJqgtlliM0ODzAntQlhtPuZzXtwHBsozYnS6vnt4iQtLCvcQo7hXNyeMcrweqWGHWaYpdvY=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(396003)(376002)(346002)(39860400002)(136003)(36840700001)(46966006)(6286002)(82310400003)(83380400001)(2616005)(107886003)(4326008)(26005)(36906005)(82740400003)(186003)(86362001)(6666004)(336012)(426003)(54906003)(55016002)(47076005)(7696005)(1076003)(8676002)(36756003)(316002)(356005)(2906002)(478600001)(36860700001)(70586007)(6916009)(7636003)(5660300002)(70206006)(8936002)(16526019);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 May 2021 21:09:30.2221 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 71623cfb-618c-408f-bd1f-08d90f40e889", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT057.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN9PR12MB5323", "Subject": "[dpdk-dev] [PATCH v3 04/15] crypto/mlx5: add basic operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shiri Kuzin <shirik@nvidia.com>\n\nThe basic dev control operations are configure, close and get info.\n\nExtended the existing support of configure and close:\n\t-mlx5_crypto_dev_configure- function used to configure device.\n\t-mlx5_crypto_dev_close- function used to close a configured\n\t device.\n\nAdded support of get info function:\n\t-mlx5_crypto_dev_infos_get- function used to get specific\n\t information of a device.\n\nAdded config struct to user private data with the fields socket id,\nnumber of queue pairs and feature flags to be disabled.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 46 +++++++++++++++++++++++++++----\n drivers/crypto/mlx5/mlx5_crypto.h | 1 +\n 2 files changed, 42 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 32f5077066..cec21dbea7 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -19,6 +19,7 @@\n \n #define MLX5_CRYPTO_DRIVER_NAME mlx5_crypto\n #define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5\n+#define MLX5_CRYPTO_MAX_QPS 1024\n \n TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list =\n \t\t\t\tTAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list);\n@@ -28,6 +29,9 @@ int mlx5_crypto_logtype;\n \n uint8_t mlx5_crypto_driver_id;\n \n+const struct rte_cryptodev_capabilities\n+\t\tmlx5_crypto_caps[RTE_CRYPTO_OP_TYPE_UNDEFINED];\n+\n static const char mlx5_crypto_drv_name[] = RTE_STR(MLX5_CRYPTO_DRIVER_NAME);\n \n static const struct rte_driver mlx5_drv = {\n@@ -49,22 +53,47 @@ struct mlx5_crypto_session {\n \tuint32_t dek_id; /* DEK ID */\n } __rte_packed;\n \n-static unsigned int\n-mlx5_crypto_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)\n+static void\n+mlx5_crypto_dev_infos_get(struct rte_cryptodev *dev,\n+\t\t\t struct rte_cryptodev_info *dev_info)\n {\n-\treturn sizeof(struct mlx5_crypto_session);\n+\tRTE_SET_USED(dev);\n+\tif (dev_info != NULL) {\n+\t\tdev_info->driver_id = mlx5_crypto_driver_id;\n+\t\tdev_info->feature_flags = 0;\n+\t\tdev_info->capabilities = mlx5_crypto_caps;\n+\t\tdev_info->max_nb_queue_pairs = MLX5_CRYPTO_MAX_QPS;\n+\t\tdev_info->min_mbuf_headroom_req = 0;\n+\t\tdev_info->min_mbuf_tailroom_req = 0;\n+\t\tdev_info->sym.max_nb_sessions = 0;\n+\t\t/*\n+\t\t * If 0, the device does not have any limitation in number of\n+\t\t * sessions that can be used.\n+\t\t */\n+\t}\n }\n \n static int\n mlx5_crypto_dev_configure(struct rte_cryptodev *dev,\n-\t\tstruct rte_cryptodev_config *config __rte_unused)\n+\t\t\t struct rte_cryptodev_config *config)\n {\n \tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n \n+\tif (config == NULL) {\n+\t\tDRV_LOG(ERR, \"Invalid crypto dev configure parameters.\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif ((config->ff_disable & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) != 0) {\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"Disabled symmetric crypto feature is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n \tif (mlx5_crypto_dek_setup(priv) != 0) {\n \t\tDRV_LOG(ERR, \"Dek hash list creation has failed.\");\n \t\treturn -ENOMEM;\n \t}\n+\tpriv->dev_config = *config;\n+\tDRV_LOG(DEBUG, \"Device %u was configured.\", dev->driver_id);\n \treturn 0;\n }\n \n@@ -74,9 +103,16 @@ mlx5_crypto_dev_close(struct rte_cryptodev *dev)\n \tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n \n \tmlx5_crypto_dek_unset(priv);\n+\tDRV_LOG(DEBUG, \"Device %u was closed.\", dev->driver_id);\n \treturn 0;\n }\n \n+static unsigned int\n+mlx5_crypto_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)\n+{\n+\treturn sizeof(struct mlx5_crypto_session);\n+}\n+\n static int\n mlx5_crypto_sym_session_configure(struct rte_cryptodev *dev,\n \t\t\t\t struct rte_crypto_sym_xform *xform,\n@@ -153,7 +189,7 @@ static struct rte_cryptodev_ops mlx5_crypto_ops = {\n \t.dev_start\t\t\t= NULL,\n \t.dev_stop\t\t\t= NULL,\n \t.dev_close\t\t\t= mlx5_crypto_dev_close,\n-\t.dev_infos_get\t\t\t= NULL,\n+\t.dev_infos_get\t\t\t= mlx5_crypto_dev_infos_get,\n \t.stats_get\t\t\t= NULL,\n \t.stats_reset\t\t\t= NULL,\n \t.queue_pair_setup\t\t= NULL,\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 4ec67a7e0f..5e270d3d5a 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -24,6 +24,7 @@ struct mlx5_crypto_priv {\n \tuint32_t pdn; /* Protection Domain number. */\n \tstruct ibv_pd *pd;\n \tstruct mlx5_hlist *dek_hlist; /* Dek hash list. */\n+\tstruct rte_cryptodev_config dev_config;\n };\n \n struct mlx5_crypto_dek {\n", "prefixes": [ "v3", "04/15" ] }