Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/92759/?format=api
{ "id": 92759, "url": "http://patches.dpdk.org/api/patches/92759/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210504175500.3385811-16-matan@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210504175500.3385811-16-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210504175500.3385811-16-matan@nvidia.com", "date": "2021-05-04T17:55:00", "name": "[v3,15/15] common/mlx5: add UMR and RDMA write WQE defines", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "acd00b9c9c75c972c91428a9ae9708aa8c3f51b4", "submitter": { "id": 1911, "url": "http://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210504175500.3385811-16-matan@nvidia.com/mbox/", "series": [ { "id": 16811, "url": "http://patches.dpdk.org/api/series/16811/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16811", "date": "2021-05-04T17:54:45", "name": "mlx5 common part for crypto driver", "version": 3, "mbox": "http://patches.dpdk.org/series/16811/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92759/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92759/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EE0DAA0A02;\n\tTue, 4 May 2021 19:57:31 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CF44041101;\n\tTue, 4 May 2021 19:57:30 +0200 (CEST)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2089.outbound.protection.outlook.com [40.107.243.89])\n by mails.dpdk.org (Postfix) with ESMTP id 2F8CD410FF\n for <dev@dpdk.org>; Tue, 4 May 2021 19:57:29 +0200 (CEST)", "from DM5PR18CA0068.namprd18.prod.outlook.com (2603:10b6:3:22::30) by\n DM6PR12MB2924.namprd12.prod.outlook.com (2603:10b6:5:183::23) with\n Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.4087.35; Tue, 4 May 2021 17:57:27 +0000", "from DM6NAM11FT024.eop-nam11.prod.protection.outlook.com\n (2603:10b6:3:22:cafe::a6) by DM5PR18CA0068.outlook.office365.com\n (2603:10b6:3:22::30) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.25 via Frontend\n Transport; Tue, 4 May 2021 17:57:27 +0000", "from mail.nvidia.com (216.228.112.34) by\n DM6NAM11FT024.mail.protection.outlook.com (10.13.172.159) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4087.27 via Frontend Transport; Tue, 4 May 2021 17:57:27 +0000", "from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 May\n 2021 17:57:25 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=ZPrsKDRLL9BBqbHPJgynJkE8KY9t+jLCQn0uGD6lFV+d5KTkv9T8/x1DPJku38dCzTOUlCtJuUS9HHf5jPdX+yW/hebThxSWBDr0UyHjQJhYGBQcSOdDidJ0omz+3gAl6dhHoMZYbWuAcFfOK64LEfwvxntuQxxIoOp+pt3Jqm6yg8OIanKEKbF8kQ71/M50KOisIUm2cKcn1/KiW0IgbxTpWpTEjs7o3oDQ8BlvKQyX1KnkmBw11f1IyONBl/DDfYNI8y+1aAOrfdcr9Q0IHUD6Mq8V55s+bUu9GlxJXJkv5EZii8IOOCxXbMvjh9+Io6txnpZYDWwrMfMzf4Wy5g==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=rp6vOSaAuzukWT2OIVUyLyZCxGX1gmWEL71A566xJz4=;\n b=LLDxtUbCrs66xUIaoW86xmQ3L4RLw4N6zHjcpYm/kwifkgsgguC5HhVEJNooaWJhLkyk6e9uS3EqzBIT+bavJ3en1mpiIAmQUmLFCjgADldagWlHpitu/25qHkv1Q/WET9HnXol6+YU0bnDZLuoGumeZj/aiMK0e59jVd6iqgKXueVmSV0cC5IfnnoACNoHb+gpVBbB/UzaL4M/ZjHQPI8uAmcz9opgns69LJLZi4QIAtsXJptnhTqUNFPtbACDgBf7tXv+fiKMjidZNR1pnc0LKJqte1DK0kRfqkN5OxPimxQlKGn6q9uvJpYdj2bURBcVHUYCNzJDuts31veGY5A==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=rp6vOSaAuzukWT2OIVUyLyZCxGX1gmWEL71A566xJz4=;\n b=I3BWBkmB6IgbVemj+nWE08LhMJrWDDA60ueZXkSv3QHnyqYtcZcS1mgZYG8G8aigyQdn7iTYvGyTreVNIFwdBhe3r5ewTmkr974JYJ2AEbO/qw3gQIhb0Ms46YpBfOCeZKzO6JFTSDNwHWXLWMa6Vh24czKcZHKnufzeSt/bV8Hoo/HWRHA6hHbDFyCR1/f858VaOTgBoIhNBoef0XZjmE6b6twMekLhYeqUgP77yxmF6IZoZQgbp6M/SI6CUDacQU8u7GfDO5/sOFI41saVDoOJIeDoq5E46zezOiWsHtqQB+cL/DdjxSO9o6ZZa++lbM+BWkCTa7A+uIs3+0Mecg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed)\n header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>", "Date": "Tue, 4 May 2021 20:55:00 +0300", "Message-ID": "<20210504175500.3385811-16-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210504175500.3385811-1-matan@nvidia.com>", "References": "<20210429154335.2820028-1-matan@nvidia.com>\n <20210504175500.3385811-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "e7d80591-2c59-4193-4d4a-08d90f261444", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB2924:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB29246576393E77A3DF4501C0DF5A9@DM6PR12MB2924.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2201;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 7JDbybyGQjfA0x5UEF2lblK/iNlgv8+scswGeLpI8R+G03utc1W3Hq8xmDknj0Bnu9IJLnGattTCzLxLK0JJGNqWwBF0R+P4kkUW4vsY6qOpFmhJgOOHMZd6P5gJGb8WVV0DCGWDLdHb5EZiozGuGKqwaW/L+pJ1hRmj8sVtaVoHAcFxziR2CCCMeqsuz3+eWd2fMdoCsI14o5r8BLezBFDekBwwEPytqGUiit5AcrR4nM6RKW8elQY3JhTIMXhvERplGLHv2co66zyNPOhDto6QCwdPSGFAK+q42edt7gNNYC/StB2Xm/LVl77N0HNilXXfImdeR/XCgFeTQhpUgEHTumNKomsbxUHCOOXpbwaFkJUSnsoLztVDLltwrYCgTmI6vZVpshP8e9e2tqKtVNiZxPsT1c2RwoZT7XZYPXg/VhQHnR3CMp8/KahdXE2zAr0h0lCaDuIpLKabZo5ksQg80IikUmaTDsnZZeb20hGxehVSzScomQKjpEwM4hXZG9a93gli6GO/g2hWG//ur2f8r5AGPMIzslyiOa0nM/ShM1QL/dBe+/vQDR5HprQZ3zIz7tn0PRYA5hMd/QZk5orfGjcR18VMXwnkcYzMfWexl3mgkrEJgkySo0vxYI4aF9w+v2/+UGuvIltVwReHafOIvMXLoKnlzjEZx4+lz7k=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(136003)(346002)(39860400002)(396003)(376002)(46966006)(36840700001)(7696005)(186003)(16526019)(47076005)(82740400003)(356005)(82310400003)(36756003)(2616005)(6286002)(1076003)(5660300002)(36860700001)(7636003)(26005)(316002)(54906003)(86362001)(6916009)(336012)(6666004)(426003)(478600001)(36906005)(2906002)(55016002)(83380400001)(70586007)(8676002)(4326008)(70206006)(8936002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 May 2021 17:57:27.1760 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e7d80591-2c59-4193-4d4a-08d90f261444", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT024.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB2924", "Subject": "[dpdk-dev] [PATCH v3 15/15] common/mlx5: add UMR and RDMA write WQE\n defines", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Suanming Mou <suanmingm@nvidia.com>\n\nThis patch adds the struct defining UMR and RDMA write WQEs.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nSigned-off-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 187 +++++++++++++++++++++------------\n 1 file changed, 121 insertions(+), 66 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex c2cd2d9f70..1ffee5fd56 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -412,6 +412,127 @@ struct mlx5_cqe_ts {\n \tuint8_t op_own;\n };\n \n+struct mlx5_wqe_rseg {\n+\tuint64_t raddr;\n+\tuint32_t rkey;\n+\tuint32_t reserved;\n+} __rte_packed;\n+\n+#define MLX5_UMRC_IF_OFFSET 31u\n+#define MLX5_UMRC_KO_OFFSET 16u\n+#define MLX5_UMRC_TO_BS_OFFSET 0u\n+\n+struct mlx5_wqe_umr_cseg {\n+\tuint32_t if_cf_toe_cq_res;\n+\tuint32_t ko_to_bs;\n+\tuint64_t mkey_mask;\n+\tuint32_t rsvd1[8];\n+} __rte_packed;\n+\n+struct mlx5_wqe_mkey_cseg {\n+\tuint32_t fr_res_af_sf;\n+\tuint32_t qpn_mkey;\n+\tuint32_t reserved2;\n+\tuint32_t flags_pd;\n+\tuint64_t start_addr;\n+\tuint64_t len;\n+\tuint32_t bsf_octword_size;\n+\tuint32_t reserved3[4];\n+\tuint32_t translations_octword_size;\n+\tuint32_t res4_lps;\n+\tuint32_t reserved;\n+} __rte_packed;\n+\n+enum {\n+\tMLX5_BSF_SIZE_16B = 0x0,\n+\tMLX5_BSF_SIZE_32B = 0x1,\n+\tMLX5_BSF_SIZE_64B = 0x2,\n+\tMLX5_BSF_SIZE_128B = 0x3,\n+};\n+\n+enum {\n+\tMLX5_BSF_P_TYPE_SIGNATURE = 0x0,\n+\tMLX5_BSF_P_TYPE_CRYPTO = 0x1,\n+};\n+\n+enum {\n+\tMLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0,\n+\tMLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1,\n+\tMLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2,\n+\tMLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3,\n+};\n+\n+enum {\n+\tMLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0,\n+};\n+\n+enum {\n+\tMLX5_BLOCK_SIZE_512B\t= 0x1,\n+\tMLX5_BLOCK_SIZE_520B\t= 0x2,\n+\tMLX5_BLOCK_SIZE_4096B\t= 0x3,\n+\tMLX5_BLOCK_SIZE_4160B\t= 0x4,\n+\tMLX5_BLOCK_SIZE_1MB\t= 0x5,\n+\tMLX5_BLOCK_SIZE_4048B\t= 0x6,\n+};\n+\n+#define MLX5_BSF_SIZE_OFFSET\t\t30\n+#define MLX5_BSF_P_TYPE_OFFSET\t\t24\n+#define MLX5_ENCRYPTION_ORDER_OFFSET\t16\n+#define MLX5_BLOCK_SIZE_OFFSET\t\t24\n+\n+struct mlx5_wqe_umr_bsf_seg {\n+\t/*\n+\t * bs_bpt_eo_es contains:\n+\t * bs\tbsf_size\t\t2 bits at MLX5_BSF_SIZE_OFFSET\n+\t * bpt\tbsf_p_type\t\t2 bits at MLX5_BSF_P_TYPE_OFFSET\n+\t * eo\tencryption_order\t4 bits at MLX5_ENCRYPTION_ORDER_OFFSET\n+\t * es\tencryption_standard\t4 bits at offset 0\n+\t */\n+\tuint32_t bs_bpt_eo_es;\n+\tuint32_t raw_data_size;\n+\t/*\n+\t * bsp_res contains:\n+\t * bsp\tcrypto_block_size_pointer\t8 bits at MLX5_BLOCK_SIZE_OFFSET\n+\t * res\treserved 24 bits\n+\t */\n+\tuint32_t bsp_res;\n+\tuint32_t reserved0;\n+\tuint8_t xts_initial_tweak[16];\n+\t/*\n+\t * res_dp contains:\n+\t * res\treserved 8 bits\n+\t * dp\tdek_pointer\t\t24 bits at offset 0\n+\t */\n+\tuint32_t res_dp;\n+\tuint32_t reserved1;\n+\tuint64_t keytag;\n+\tuint32_t reserved2[4];\n+} __rte_packed;\n+\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-Wpedantic\"\n+#endif\n+\n+struct mlx5_umr_wqe {\n+\tstruct mlx5_wqe_cseg ctr;\n+\tstruct mlx5_wqe_umr_cseg ucseg;\n+\tstruct mlx5_wqe_mkey_cseg mkc;\n+\tunion {\n+\t\tstruct mlx5_wqe_dseg kseg[0];\n+\t\tstruct mlx5_wqe_umr_bsf_seg bsf[0];\n+\t};\n+} __rte_packed;\n+\n+struct mlx5_rdma_write_wqe {\n+\tstruct mlx5_wqe_cseg ctr;\n+\tstruct mlx5_wqe_rseg rseg;\n+\tstruct mlx5_wqe_dseg dseg[0];\n+} __rte_packed;\n+\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic error \"-Wpedantic\"\n+#endif\n+\n /* GGA */\n /* MMO metadata segment */\n \n@@ -1096,72 +1217,6 @@ struct mlx5_ifc_create_mkey_in_bits {\n \tu8 klm_pas_mtt[][0x20];\n };\n \n-enum {\n-\tMLX5_BSF_SIZE_16B = 0x0,\n-\tMLX5_BSF_SIZE_32B = 0x1,\n-\tMLX5_BSF_SIZE_64B = 0x2,\n-\tMLX5_BSF_SIZE_128B = 0x3,\n-};\n-\n-enum {\n-\tMLX5_BSF_P_TYPE_SIGNATURE = 0x0,\n-\tMLX5_BSF_P_TYPE_CRYPTO = 0x1,\n-};\n-\n-enum {\n-\tMLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0,\n-\tMLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1,\n-\tMLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2,\n-\tMLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3,\n-};\n-\n-enum {\n-\tMLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0,\n-};\n-\n-enum {\n-\tMLX5_BLOCK_SIZE_512B\t= 0x1,\n-\tMLX5_BLOCK_SIZE_520B\t= 0x2,\n-\tMLX5_BLOCK_SIZE_4096B\t= 0x3,\n-\tMLX5_BLOCK_SIZE_4160B\t= 0x4,\n-\tMLX5_BLOCK_SIZE_1MB\t= 0x5,\n-\tMLX5_BLOCK_SIZE_4048B\t= 0x6,\n-};\n-\n-#define MLX5_BSF_SIZE_OFFSET\t\t30\n-#define MLX5_BSF_P_TYPE_OFFSET\t\t24\n-#define MLX5_ENCRYPTION_ORDER_OFFSET\t16\n-#define MLX5_BLOCK_SIZE_OFFSET\t\t24\n-\n-struct mlx5_wqe_umr_bsf_seg {\n-\t/*\n-\t * bs_bpt_eo_es contains:\n-\t * bs\tbsf_size\t\t2 bits at MLX5_BSF_SIZE_OFFSET\n-\t * bpt\tbsf_p_type\t\t2 bits at MLX5_BSF_P_TYPE_OFFSET\n-\t * eo\tencryption_order\t4 bits at MLX5_ENCRYPTION_ORDER_OFFSET\n-\t * es\tencryption_standard\t4 bits at offset 0\n-\t */\n-\tuint32_t bs_bpt_eo_es;\n-\tuint32_t raw_data_size;\n-\t/*\n-\t * bsp_res contains:\n-\t * bsp\tcrypto_block_size_pointer\t8 bits at MLX5_BLOCK_SIZE_OFFSET\n-\t * res\treserved 24 bits\n-\t */\n-\tuint32_t bsp_res;\n-\tuint32_t reserved0;\n-\tuint8_t xts_initial_tweak[16];\n-\t/*\n-\t * res_dp contains:\n-\t * res\treserved 8 bits\n-\t * dp\tdek_pointer\t\t24 bits at offset 0\n-\t */\n-\tuint32_t res_dp;\n-\tuint32_t reserved1;\n-\tuint64_t keytag;\n-\tuint32_t reserved2[4];\n-} __rte_packed;\n-\n enum {\n \tMLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,\n", "prefixes": [ "v3", "15/15" ] }