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GET /api/patches/92758/?format=api
{ "id": 92758, "url": "http://patches.dpdk.org/api/patches/92758/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210504175500.3385811-15-matan@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210504175500.3385811-15-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210504175500.3385811-15-matan@nvidia.com", "date": "2021-05-04T17:54:59", "name": "[v3,14/15] common/mlx5: support register write access", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "56be27a1d2ecbcec82d8a2f7cdf82a9a3a68b2be", "submitter": { "id": 1911, "url": "http://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210504175500.3385811-15-matan@nvidia.com/mbox/", "series": [ { "id": 16811, "url": "http://patches.dpdk.org/api/series/16811/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16811", "date": "2021-05-04T17:54:45", "name": "mlx5 common part for crypto driver", "version": 3, "mbox": "http://patches.dpdk.org/series/16811/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92758/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92758/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5EE11A0A02;\n\tTue, 4 May 2021 19:57:26 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 86DB940697;\n\tTue, 4 May 2021 19:57:25 +0200 (CEST)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2074.outbound.protection.outlook.com [40.107.243.74])\n by mails.dpdk.org (Postfix) with ESMTP id 0AF414014E\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>, Dekel Peled <dekelp@nvidia.com>", "Date": "Tue, 4 May 2021 20:54:59 +0300", "Message-ID": "<20210504175500.3385811-15-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210504175500.3385811-1-matan@nvidia.com>", "References": "<20210429154335.2820028-1-matan@nvidia.com>\n <20210504175500.3385811-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "e87e45bf-158a-4653-8c4d-08d90f261228", "X-MS-TrafficTypeDiagnostic": "CH2PR12MB4231:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <CH2PR12MB4231CFCBA7723E581E0AD6CDDF5A9@CH2PR12MB4231.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:4125;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n VoSLM1ugWY0yk3hPpJ9XYoUS9s8fOcVjUCPeDiWVmO7RDCFs8+VX2aaSEi8eszXh9ijzO0lJ9rql6pZdgrADJKiB+fXucUhEG1fSXiZ62KH8Y9MrrwlNC0PB4XU1sHpWAaKFpnKhoB5O/T04tLBjvESMg+AWmth+xFpZmros6VCEnBenGq62uIuTiRgVUs646w6rX6UqK8LY52qVgybSBi0CMuV45NhqO0LHfTtP0tGP7Wrb5CjOsrSgvusFMhBYPS5Qv9ojw8McWzOXuiprqXtiS7fBQ6Kt7QThzx2uqhaLjkfHHAqsouyscscJg61k7/Z9EFbkzrKCaQl2dRDjcOPJstFk3HnaItt2sIw53Gqd+d1O3EB7OYWEC9TJWAJUzr3psc0y/lSC9eLleyHW3OoPck+HhyEN+Smve7sdkAGm242qh7GbRwfvTyNp9UKOIUFXm3V27nItwEimEaB7S1Ww0nqIwLL7cWG/fVyj9RSWF+ySfnK7h0Plxo9qAkB1hNaVP9iujstgR8oXsfJgGZ6DBdcznuymv8xc/3J9WQej9AuTiTvzLYL2R9QgAfyR2YwVEFDqAxxq4ze6jqREWm4O53N7a5GDOzPbqNr/mDzCmA/sM2Vma+X/IhDAPaOe4RYEpobw9ToBdXZnF920KrJFsY/nwLk0lYSpk9P4fus=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(396003)(136003)(39860400002)(376002)(346002)(36840700001)(46966006)(8676002)(2616005)(8936002)(82310400003)(186003)(6916009)(2906002)(7636003)(82740400003)(4326008)(83380400001)(356005)(107886003)(54906003)(1076003)(70206006)(36756003)(70586007)(426003)(336012)(7696005)(5660300002)(86362001)(26005)(36906005)(16526019)(55016002)(6666004)(36860700001)(478600001)(316002)(47076005)(6286002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 May 2021 17:57:23.6457 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e87e45bf-158a-4653-8c4d-08d90f261228", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT013.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB4231", "Subject": "[dpdk-dev] [PATCH v3 14/15] common/mlx5: support register write\n access", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Dekel Peled <dekelp@nvidia.com>\n\nThis patch adds support of write operation to NIC registers.\n\nSigned-off-by: Dekel Peled <dekelp@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 67 +++++++++++++++++++++++++++-\n drivers/common/mlx5/mlx5_devx_cmds.h | 4 ++\n drivers/common/mlx5/version.map | 1 +\n 3 files changed, 70 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex c0a0853c3a..0b421933ce 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -12,7 +12,6 @@\n #include \"mlx5_common_log.h\"\n #include \"mlx5_malloc.h\"\n \n-\n /**\n * Perform read access to the registers. Reads data from register\n * and writes ones to the specified buffer.\n@@ -61,7 +60,7 @@ mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,\n \tif (status) {\n \t\tint syndrome = MLX5_GET(access_register_out, out, syndrome);\n \n-\t\tDRV_LOG(DEBUG, \"Failed to access NIC register 0x%X, \"\n+\t\tDRV_LOG(DEBUG, \"Failed to read access NIC register 0x%X, \"\n \t\t\t \"status %x, syndrome = %x\",\n \t\t\t reg_id, status, syndrome);\n \t\treturn -1;\n@@ -74,6 +73,70 @@ mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,\n \treturn rc;\n }\n \n+/**\n+ * Perform write access to the registers.\n+ *\n+ * @param[in] ctx\n+ * Context returned from mlx5 open_device() glue function.\n+ * @param[in] reg_id\n+ * Register identifier according to the PRM.\n+ * @param[in] arg\n+ * Register access auxiliary parameter according to the PRM.\n+ * @param[out] data\n+ * Pointer to the buffer containing data to write.\n+ * @param[in] dw_cnt\n+ * Buffer size in double words (32bit units).\n+ *\n+ * @return\n+ * 0 on success, a negative value otherwise.\n+ */\n+int\n+mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,\n+\t\t\t uint32_t *data, uint32_t dw_cnt)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(access_register_in) +\n+\t\t MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};\n+\tint status, rc;\n+\tvoid *ptr;\n+\n+\tMLX5_ASSERT(data && dw_cnt);\n+\tMLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);\n+\tif (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {\n+\t\tDRV_LOG(ERR, \"Data to write exceeds max size\");\n+\t\treturn -1;\n+\t}\n+\tMLX5_SET(access_register_in, in, opcode,\n+\t\t MLX5_CMD_OP_ACCESS_REGISTER_USER);\n+\tMLX5_SET(access_register_in, in, op_mod,\n+\t\t MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE);\n+\tMLX5_SET(access_register_in, in, register_id, reg_id);\n+\tMLX5_SET(access_register_in, in, argument, arg);\n+\tptr = MLX5_ADDR_OF(access_register_in, in, register_data);\n+\tmemcpy(ptr, data, dw_cnt * sizeof(uint32_t));\n+\trc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));\n+\n+\trc = mlx5_glue->devx_general_cmd(ctx, in,\n+\t\t\t\t\t MLX5_ST_SZ_BYTES(access_register_in) +\n+\t\t\t\t\t dw_cnt * sizeof(uint32_t),\n+\t\t\t\t\t out, sizeof(out));\n+\tif (rc)\n+\t\tgoto error;\n+\tstatus = MLX5_GET(access_register_out, out, status);\n+\tif (status) {\n+\t\tint syndrome = MLX5_GET(access_register_out, out, syndrome);\n+\n+\t\tDRV_LOG(DEBUG, \"Failed to write access NIC register 0x%X, \"\n+\t\t\t \"status %x, syndrome = %x\",\n+\t\t\t reg_id, status, syndrome);\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+error:\n+\trc = (rc > 0) ? -rc : rc;\n+\treturn rc;\n+}\n+\n /**\n * Allocate flow counters via devx interface.\n *\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 811e7a1462..ce570ad28a 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -566,6 +566,10 @@ __rte_internal\n int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,\n \t\t\t\tuint32_t arg, uint32_t *data, uint32_t dw_cnt);\n \n+__rte_internal\n+int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id,\n+\t\t\t\t uint32_t arg, uint32_t *data, uint32_t dw_cnt);\n+\n __rte_internal\n struct mlx5_devx_obj *\n mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,\ndiff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map\nindex 04b2179b2c..c630696213 100644\n--- a/drivers/common/mlx5/version.map\n+++ b/drivers/common/mlx5/version.map\n@@ -53,6 +53,7 @@ INTERNAL {\n \tmlx5_devx_cmd_queue_counter_alloc; # WINDOWS_NO_EXPORT\n \tmlx5_devx_cmd_queue_counter_query; # WINDOWS_NO_EXPORT\n \tmlx5_devx_cmd_register_read;\n+\tmlx5_devx_cmd_register_write;\n \tmlx5_devx_cmd_wq_query; # WINDOWS_NO_EXPORT\n \n \tmlx5_devx_cq_create;\n", "prefixes": [ "v3", "14/15" ] }