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GET /api/patches/92753/?format=api
{ "id": 92753, "url": "http://patches.dpdk.org/api/patches/92753/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210504175500.3385811-10-matan@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210504175500.3385811-10-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210504175500.3385811-10-matan@nvidia.com", "date": "2021-05-04T17:54:54", "name": "[v3,09/15] common/mlx5: add crypto BSF struct and defines", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b0a5889d8a6c334c4db0d3dc70383d7ed1603fe9", "submitter": { "id": 1911, "url": "http://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210504175500.3385811-10-matan@nvidia.com/mbox/", "series": [ { "id": 16811, "url": "http://patches.dpdk.org/api/series/16811/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16811", "date": "2021-05-04T17:54:45", "name": "mlx5 common part for crypto driver", "version": 3, "mbox": "http://patches.dpdk.org/series/16811/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92753/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92753/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 102EAA0A02;\n\tTue, 4 May 2021 19:56:44 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id ED89F410F8;\n\tTue, 4 May 2021 19:56:43 +0200 (CEST)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2071.outbound.protection.outlook.com [40.107.93.71])\n by mails.dpdk.org (Postfix) with ESMTP id 48EF3406A2\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>, Dekel Peled <dekelp@nvidia.com>", "Date": "Tue, 4 May 2021 20:54:54 +0300", "Message-ID": "<20210504175500.3385811-10-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210504175500.3385811-1-matan@nvidia.com>", "References": "<20210429154335.2820028-1-matan@nvidia.com>\n <20210504175500.3385811-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "fcd071f2-73e6-4009-d6ab-08d90f25f8af", "X-MS-TrafficTypeDiagnostic": "PH0PR12MB5420:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <PH0PR12MB5420B7C9D2AA33C64940BD0EDF5A9@PH0PR12MB5420.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2043;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n OnqQhc9iLeJ57gtEKdry/Q7as25fbckofVJByLkvcBLhvM784S0OTi8/diddu7nrEEG9XshxTXs3RXiqNPPhA4rTon7XbouRMcXVCM9BIggIL7YJJGI+SzShJJ68I+on6NMjaIVyr9R1NfjcbSah1ZAATyQy1/P8h2vejk6X4YGeBWwFyKkHAA+0XLNoSuZOg7dc6yGuMyKIZXg3EjpvLZhhGiOtLDsQ/cGaOLNqhv0M+w1by9ABp1o/0mqOrltAciDxU1XHicZNWZAAZfkfiYjr/Gyjif3hiNJAwxz8abgI2xiNGXdj21ZxjnafTXIWU8egBYDq/rcmX8Y/xET/Gv4eMyFCO1zu1nNBVWQppc7FNvObWjUdwad4yd4fjehxaHCUDWbVbxXgYx84/ZI8DIF8iQ6z9NUy2AB7HF6vmOKaFSuEC3M+LLmywDDg7uX0evOE7jrpUDFOTOPdwmKIPVGp3c5pgFy1hCbzsTDqoECaxIVz2ocnxSfQgLBFsRxKy/rkyMPGDiEkIdXmNbo5a8+BqNAgN3tT2ZWYTQ4ZplFQgmMOXIWrW73PLWbUFV5UF8RXGJbZwI2DcyEYOZp3tyfKA9JQlx064lEsLt4WDZ7/fkEyd7nv2Bg5rFJEQZOG1wLVw9bXvmvxcrv2ZNYDK9eZ5k3tdUsKUq6o3XFFwdk=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(396003)(346002)(376002)(136003)(39860400002)(46966006)(36840700001)(186003)(1076003)(16526019)(6286002)(70206006)(107886003)(70586007)(36756003)(47076005)(7696005)(478600001)(55016002)(83380400001)(426003)(4326008)(8676002)(5660300002)(26005)(36860700001)(2616005)(86362001)(6666004)(36906005)(6916009)(316002)(8936002)(54906003)(2906002)(82740400003)(7636003)(356005)(82310400003)(336012);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 May 2021 17:56:40.8916 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n fcd071f2-73e6-4009-d6ab-08d90f25f8af", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT037.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH0PR12MB5420", "Subject": "[dpdk-dev] [PATCH v3 09/15] common/mlx5: add crypto BSF struct and\n defines", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Dekel Peled <dekelp@nvidia.com>\n\nThis patch adds the struct defining crypto BSF segment of UMR WQE,\nand the related value definitions and offsets.\n\nSigned-off-by: Dekel Peled <dekelp@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 66 ++++++++++++++++++++++++++++++++++\n 1 file changed, 66 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex a2437faec0..a9dcbfa63c 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1096,6 +1096,72 @@ struct mlx5_ifc_create_mkey_in_bits {\n \tu8 klm_pas_mtt[][0x20];\n };\n \n+enum {\n+\tMLX5_BSF_SIZE_16B = 0x0,\n+\tMLX5_BSF_SIZE_32B = 0x1,\n+\tMLX5_BSF_SIZE_64B = 0x2,\n+\tMLX5_BSF_SIZE_128B = 0x3,\n+};\n+\n+enum {\n+\tMLX5_BSF_P_TYPE_SIGNATURE = 0x0,\n+\tMLX5_BSF_P_TYPE_CRYPTO = 0x1,\n+};\n+\n+enum {\n+\tMLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0,\n+\tMLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1,\n+\tMLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2,\n+\tMLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3,\n+};\n+\n+enum {\n+\tMLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0,\n+};\n+\n+enum {\n+\tMLX5_BLOCK_SIZE_512B\t= 0x1,\n+\tMLX5_BLOCK_SIZE_520B\t= 0x2,\n+\tMLX5_BLOCK_SIZE_4096B\t= 0x3,\n+\tMLX5_BLOCK_SIZE_4160B\t= 0x4,\n+\tMLX5_BLOCK_SIZE_1MB\t= 0x5,\n+\tMLX5_BLOCK_SIZE_4048B\t= 0x6,\n+};\n+\n+#define MLX5_BSF_SIZE_OFFSET\t\t30\n+#define MLX5_BSF_P_TYPE_OFFSET\t\t24\n+#define MLX5_ENCRYPTION_ORDER_OFFSET\t16\n+#define MLX5_BLOCK_SIZE_OFFSET\t\t24\n+\n+struct mlx5_wqe_umr_bsf_seg {\n+\t/*\n+\t * bs_bpt_eo_es contains:\n+\t * bs\tbsf_size\t\t2 bits at MLX5_BSF_SIZE_OFFSET\n+\t * bpt\tbsf_p_type\t\t2 bits at MLX5_BSF_P_TYPE_OFFSET\n+\t * eo\tencryption_order\t4 bits at MLX5_ENCRYPTION_ORDER_OFFSET\n+\t * es\tencryption_standard\t4 bits at offset 0\n+\t */\n+\tuint32_t bs_bpt_eo_es;\n+\tuint32_t raw_data_size;\n+\t/*\n+\t * bsp_res contains:\n+\t * bsp\tcrypto_block_size_pointer\t8 bits at MLX5_BLOCK_SIZE_OFFSET\n+\t * res\treserved 24 bits\n+\t */\n+\tuint32_t bsp_res;\n+\tuint32_t reserved0;\n+\tuint8_t xts_initial_tweak[16];\n+\t/*\n+\t * res_dp contains:\n+\t * res\treserved 8 bits\n+\t * dp\tdek_pointer\t\t24 bits at offset 0\n+\t */\n+\tuint32_t res_dp;\n+\tuint32_t reserved1;\n+\tuint64_t keytag;\n+\tuint32_t reserved2[4];\n+} __rte_packed;\n+\n enum {\n \tMLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,\n", "prefixes": [ "v3", "09/15" ] }