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GET /api/patches/92749/?format=api
{ "id": 92749, "url": "http://patches.dpdk.org/api/patches/92749/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210504175500.3385811-6-matan@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210504175500.3385811-6-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210504175500.3385811-6-matan@nvidia.com", "date": "2021-05-04T17:54:50", "name": "[v3,05/15] common/mlx5: support general object DEK create op", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "88c6f88c47abba18f7e9a20cf1b2195ad0fa3b8a", "submitter": { "id": 1911, "url": "http://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210504175500.3385811-6-matan@nvidia.com/mbox/", "series": [ { "id": 16811, "url": "http://patches.dpdk.org/api/series/16811/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16811", "date": "2021-05-04T17:54:45", "name": "mlx5 common part for crypto driver", "version": 3, "mbox": "http://patches.dpdk.org/series/16811/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92749/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92749/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>, Dekel Peled <dekelp@nvidia.com>", "Date": "Tue, 4 May 2021 20:54:50 +0300", "Message-ID": "<20210504175500.3385811-6-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210504175500.3385811-1-matan@nvidia.com>", "References": "<20210429154335.2820028-1-matan@nvidia.com>\n <20210504175500.3385811-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", 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V2t4hr52WPcLGER8mGFkRDSIjfunH6RikBjEN1ffWOxirezuZ1+ECYzvSfM/YOqwYPHNA3ymipg1jU8kRXVqzu1PJKpZgFrbnpExll9Wn66Z4sV+/9xT8Qfs+G/toND0eUjklc1mWMoGAbkCe/4WafCjNnMPsnRGphQtmHNouA9GAtTL9il41X1uPMGPlK9s33zWk0Xl0F7B1RsbdkcA1LkFonr7z40NjQyYMi9vOfHAgKojHAKqcAB9LqjB/m/aolwoHjPfLhHTRZ0VEFB+zP2nDNtqQKgMZd7r/1YTgLEKV6R4qswC3lOMP3hIYIY0gkNFyjF7wuGYCgw6soZHYjXBPvor4lIgVqppiJn7gWJ6rnvLz4QVcKoZhd37xvvgqNY5eE6cVeSJxwhXu2K0qHd7x/PbDlt6HxMoyxaj5fX2u6otZVvE0qSkjDkmXhzgZN/4VUyK4oN4bGpQDe0G9GmGNpQIFkkCHi6RKg5llSOfwdp0P7mRv7aVDj36bN8Ftz3eMx2PMY/9H7DV249gI14DMdzgBzUW5KpvGXjcjGTPUiB4q3DH7FKD2/t//Tgqp7iZSq6XeTcqgRf2eScPtoTV2DftcpYofl0tFGKUNzIMtVu75kO5RG231aWht04RVQKUTm5zkyaEpDK+pB2pKQ==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(39850400004)(396003)(346002)(376002)(136003)(46966006)(36840700001)(55016002)(83380400001)(426003)(356005)(6286002)(478600001)(6916009)(107886003)(336012)(36906005)(316002)(54906003)(2616005)(26005)(16526019)(4326008)(186003)(2906002)(86362001)(82740400003)(6666004)(7696005)(5660300002)(8676002)(70586007)(36756003)(47076005)(82310400003)(36860700001)(1076003)(8936002)(7636003)(70206006);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 May 2021 17:56:08.5933 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f3591220-a566-441c-cece-08d90f25e56f", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT027.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR1201MB0093", "Subject": "[dpdk-dev] [PATCH v3 05/15] common/mlx5: support general object DEK\n create op", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Dekel Peled <dekelp@nvidia.com>\n\nData Encryption Keys (DEKs) are the keys used for data\nencryption/decryption operations.\n\nAdd reading of DEK support capability.\nAdd function to create general object type DEK, using DevX API.\n\nArrange common version.map file in alphabetical order.\n\nSigned-off-by: Dekel Peled <dekelp@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 53 +++++++++++++++++++++++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 17 +++++++++\n drivers/common/mlx5/mlx5_prm.h | 39 ++++++++++++++++++++\n drivers/common/mlx5/version.map | 55 ++++++++++++++++------------\n 4 files changed, 140 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 7ca767944e..742c82cca4 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -741,6 +741,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t\t\tMLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);\n \tattr->geneve_tlv_opt = !!(general_obj_types_supported &\n \t\t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);\n+\tattr->dek = !!(general_obj_types_supported &\n+\t\t MLX5_GENERAL_OBJ_TYPES_CAP_DEK);\n \t/* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */\n \tattr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);\n \tattr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);\n@@ -2397,3 +2399,54 @@ mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,\n \t*out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);\n \treturn 0;\n }\n+\n+/**\n+ * Create general object of type DEK using DevX API.\n+ *\n+ * @param[in] ctx\n+ * Context returned from mlx5 open_device() glue function.\n+ * @param [in] attr\n+ * Pointer to DEK attributes structure.\n+ *\n+ * @return\n+ * The DevX object created, NULL otherwise and rte_errno is set.\n+ */\n+struct mlx5_devx_obj *\n+mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};\n+\tstruct mlx5_devx_obj *dek_obj = NULL;\n+\tvoid *ptr = NULL, *key_addr = NULL;\n+\n+\tdek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),\n+\t\t\t 0, SOCKET_ID_ANY);\n+\tif (dek_obj == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate DEK object data\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\tptr = MLX5_ADDR_OF(create_dek_in, in, hdr);\n+\tMLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,\n+\t\t MLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,\n+\t\t MLX5_GENERAL_OBJ_TYPE_DEK);\n+\tptr = MLX5_ADDR_OF(create_dek_in, in, dek);\n+\tMLX5_SET(dek, ptr, key_size, attr->key_size);\n+\tMLX5_SET(dek, ptr, has_keytag, attr->has_keytag);\n+\tMLX5_SET(dek, ptr, key_purpose, attr->key_purpose);\n+\tMLX5_SET(dek, ptr, pd, attr->pd);\n+\tMLX5_SET64(dek, ptr, opaque, attr->opaque);\n+\tkey_addr = MLX5_ADDR_OF(dek, ptr, key);\n+\tmemcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);\n+\tdek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),\n+\t\t\t\t\t\t out, sizeof(out));\n+\tif (dek_obj->obj == NULL) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(ERR, \"Failed to create DEK obj using DevX.\");\n+\t\tmlx5_free(dek_obj);\n+\t\treturn NULL;\n+\t}\n+\tdek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);\n+\treturn dek_obj;\n+}\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 28ade5bbc4..b9ff7ab87d 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -139,6 +139,7 @@ struct mlx5_hca_attr {\n \tuint32_t reg_c_preserve:1;\n \tuint32_t crypto:1; /* Crypto engine is supported. */\n \tuint32_t aes_xts:1; /* AES-XTS crypto is supported. */\n+\tuint32_t dek:1; /* General obj type DEK is supported. */\n \tuint32_t regexp_num_of_engines;\n \tuint32_t log_max_ft_sampler_num:8;\n \tuint32_t geneve_tlv_opt;\n@@ -435,6 +436,18 @@ struct mlx5_devx_graph_node_attr {\n \tstruct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM];\n };\n \n+/* Encryption key size is up to 1024 bit, 128 bytes. */\n+#define MLX5_CRYPTO_KEY_MAX_SIZE\t128\n+\n+struct mlx5_devx_dek_attr {\n+\tuint32_t key_size:4;\n+\tuint32_t has_keytag:1;\n+\tuint32_t key_purpose:4;\n+\tuint32_t pd:24;\n+\tuint64_t opaque;\n+\tuint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE];\n+};\n+\n /* mlx5_devx_cmds.c */\n \n __rte_internal\n@@ -587,4 +600,8 @@ int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,\n __rte_internal\n struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx,\n \t\t\t\t\tuint32_t pd, uint32_t log_obj_size);\n+__rte_internal\n+struct mlx5_devx_obj *\n+mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr);\n+\n #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex a8fbfbb0f5..bc9f58ad03 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1109,6 +1109,8 @@ enum {\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)\n #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \\\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT)\n+#define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \\\n+\t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_DEK)\n \n enum {\n \tMLX5_HCA_CAP_OPMOD_GET_MAX = 0,\n@@ -2406,6 +2408,7 @@ struct mlx5_ifc_create_cq_in_bits {\n \n enum {\n \tMLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,\n+\tMLX5_GENERAL_OBJ_TYPE_DEK = 0x000c,\n \tMLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,\n \tMLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,\n \tMLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,\n@@ -2469,6 +2472,42 @@ struct mlx5_ifc_create_geneve_tlv_option_in_bits {\n \tstruct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;\n };\n \n+enum {\n+\tMLX5_CRYPTO_KEY_SIZE_128b = 0x0,\n+\tMLX5_CRYPTO_KEY_SIZE_256b = 0x1,\n+};\n+\n+enum {\n+\tMLX5_CRYPTO_KEY_PURPOSE_TLS\t= 0x1,\n+\tMLX5_CRYPTO_KEY_PURPOSE_IPSEC\t= 0x2,\n+\tMLX5_CRYPTO_KEY_PURPOSE_AES_XTS\t= 0x3,\n+\tMLX5_CRYPTO_KEY_PURPOSE_MACSEC\t= 0x4,\n+\tMLX5_CRYPTO_KEY_PURPOSE_GCM\t= 0x5,\n+\tMLX5_CRYPTO_KEY_PURPOSE_PSP\t= 0x6,\n+};\n+\n+struct mlx5_ifc_dek_bits {\n+\tu8 modify_field_select[0x40];\n+\tu8 state[0x8];\n+\tu8 reserved_at_48[0xc];\n+\tu8 key_size[0x4];\n+\tu8 has_keytag[0x1];\n+\tu8 reserved_at_59[0x3];\n+\tu8 key_purpose[0x4];\n+\tu8 reserved_at_60[0x8];\n+\tu8 pd[0x18];\n+\tu8 reserved_at_80[0x100];\n+\tu8 opaque[0x40];\n+\tu8 reserved_at_1c0[0x40];\n+\tu8 key[0x400];\n+\tu8 reserved_at_600[0x200];\n+};\n+\n+struct mlx5_ifc_create_dek_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_dek_bits dek;\n+};\n+\n enum {\n \tMLX5_VIRTQ_STATE_INIT = 0,\n \tMLX5_VIRTQ_STATE_RDY = 1,\ndiff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map\nindex 18dc96276d..42bb985fb1 100644\n--- a/drivers/common/mlx5/version.map\n+++ b/drivers/common/mlx5/version.map\n@@ -12,21 +12,24 @@ INTERNAL {\n \n \tmlx5_dev_to_pci_addr; # WINDOWS_NO_EXPORT\n \n+\tmlx5_devx_alloc_uar; # WINDOWS_NO_EXPORT\n+\n \tmlx5_devx_cmd_alloc_pd;\n \tmlx5_devx_cmd_create_cq;\n+\tmlx5_devx_cmd_create_dek_obj;\n \tmlx5_devx_cmd_create_flex_parser;\n+\tmlx5_devx_cmd_create_flow_hit_aso_obj;\n+\tmlx5_devx_cmd_create_flow_meter_aso_obj;\n+\tmlx5_devx_cmd_create_geneve_tlv_option;\n \tmlx5_devx_cmd_create_qp;\n \tmlx5_devx_cmd_create_rq;\n \tmlx5_devx_cmd_create_rqt;\n \tmlx5_devx_cmd_create_sq;\n-\tmlx5_devx_cmd_create_tir;\n \tmlx5_devx_cmd_create_td;\n+\tmlx5_devx_cmd_create_tir;\n \tmlx5_devx_cmd_create_tis;\n \tmlx5_devx_cmd_create_virtio_q_counters; # WINDOWS_NO_EXPORT\n \tmlx5_devx_cmd_create_virtq;\n-\tmlx5_devx_cmd_create_flow_hit_aso_obj;\n-\tmlx5_devx_cmd_create_flow_meter_aso_obj;\n-\tmlx5_devx_cmd_create_geneve_tlv_option;\n \tmlx5_devx_cmd_destroy;\n \tmlx5_devx_cmd_flow_counter_alloc;\n \tmlx5_devx_cmd_flow_counter_query;\n@@ -48,41 +51,49 @@ INTERNAL {\n \tmlx5_devx_cmd_queue_counter_query; # WINDOWS_NO_EXPORT\n \tmlx5_devx_cmd_register_read;\n \tmlx5_devx_cmd_wq_query; # WINDOWS_NO_EXPORT\n-\tmlx5_devx_get_out_command_status;\n-\tmlx5_devx_alloc_uar; # WINDOWS_NO_EXPORT\n \n \tmlx5_devx_cq_create;\n \tmlx5_devx_cq_destroy;\n+\n+\tmlx5_devx_get_out_command_status;\n+\n \tmlx5_devx_rq_create;\n \tmlx5_devx_rq_destroy;\n \tmlx5_devx_sq_create;\n \tmlx5_devx_sq_destroy;\n \n+\tmlx5_free;\n+\n \tmlx5_get_ifname_sysfs; # WINDOWS_NO_EXPORT\n \n \tmlx5_glue;\n \n+\tmlx5_malloc;\n+\tmlx5_malloc_mem_select;\n+\n+\tmlx5_memory_stat_dump; # WINDOWS_NO_EXPORT\n+\n \tmlx5_mp_init_primary; # WINDOWS_NO_EXPORT\n-\tmlx5_mp_uninit_primary; # WINDOWS_NO_EXPORT\n \tmlx5_mp_init_secondary; # WINDOWS_NO_EXPORT\n-\tmlx5_mp_uninit_secondary; # WINDOWS_NO_EXPORT\n \tmlx5_mp_req_mr_create; # WINDOWS_NO_EXPORT\n \tmlx5_mp_req_queue_state_modify;\n \tmlx5_mp_req_verbs_cmd_fd; # WINDOWS_NO_EXPORT\n+\tmlx5_mp_uninit_primary; # WINDOWS_NO_EXPORT\n+\tmlx5_mp_uninit_secondary; # WINDOWS_NO_EXPORT\n \n-\tmlx5_mr_btree_init;\n-\tmlx5_mr_btree_free;\n-\tmlx5_mr_btree_dump;\n \tmlx5_mr_addr2mr_bh;\n-\tmlx5_mr_release_cache;\n+\tmlx5_mr_btree_dump;\n+\tmlx5_mr_btree_free;\n+\tmlx5_mr_btree_init;\n+\tmlx5_mr_create_primary;\n \tmlx5_mr_dump_cache;\n-\tmlx5_mr_rebuild_cache;\n+\tmlx5_mr_flush_local_cache;\n+\tmlx5_mr_free;\n \tmlx5_mr_insert_cache;\n \tmlx5_mr_lookup_cache;\n \tmlx5_mr_lookup_list;\n-\tmlx5_mr_create_primary;\n-\tmlx5_mr_flush_local_cache;\n-\tmlx5_mr_free;\n+\tmlx5_mr_rebuild_cache;\n+\tmlx5_mr_release_cache;\n \n \tmlx5_nl_allmulti; # WINDOWS_NO_EXPORT\n \tmlx5_nl_devlink_family_id_get; # WINDOWS_NO_EXPORT\n@@ -102,20 +113,16 @@ INTERNAL {\n \tmlx5_nl_vlan_vmwa_create; # WINDOWS_NO_EXPORT\n \tmlx5_nl_vlan_vmwa_delete; # WINDOWS_NO_EXPORT\n \n+\tmlx5_pci_driver_register;\n+\n \tmlx5_os_alloc_pd;\n \tmlx5_os_dealloc_pd;\n \tmlx5_os_dereg_mr;\n \tmlx5_os_reg_mr;\n-\tmlx5_os_umem_reg;\n \tmlx5_os_umem_dereg;\n+\tmlx5_os_umem_reg;\n \n-\tmlx5_translate_port_name; # WINDOWS_NO_EXPORT\n-\n-\tmlx5_malloc_mem_select;\n-\tmlx5_memory_stat_dump; # WINDOWS_NO_EXPORT\n-\tmlx5_malloc;\n \tmlx5_realloc;\n-\tmlx5_free;\n \n-\tmlx5_pci_driver_register;\n+\tmlx5_translate_port_name; # WINDOWS_NO_EXPORT\n };\n", "prefixes": [ "v3", "05/15" ] }