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GET /api/patches/92748/?format=api
{ "id": 92748, "url": "http://patches.dpdk.org/api/patches/92748/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210504175500.3385811-5-matan@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210504175500.3385811-5-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210504175500.3385811-5-matan@nvidia.com", "date": "2021-05-04T17:54:49", "name": "[v3,04/15] common/mlx5: add HCA cap for AES-XTS crypto", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f3530af88e32cf99b20831bf1d3783bdf2506ff4", "submitter": { "id": 1911, "url": "http://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210504175500.3385811-5-matan@nvidia.com/mbox/", "series": [ { "id": 16811, "url": "http://patches.dpdk.org/api/series/16811/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16811", "date": "2021-05-04T17:54:45", "name": "mlx5 common part for crypto driver", "version": 3, "mbox": "http://patches.dpdk.org/series/16811/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92748/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92748/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EBC18A0A02;\n\tTue, 4 May 2021 19:56:06 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D4C004068E;\n\tTue, 4 May 2021 19:56:06 +0200 (CEST)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2049.outbound.protection.outlook.com [40.107.237.49])\n by mails.dpdk.org (Postfix) with ESMTP id 026304068E\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>, Dekel Peled <dekelp@nvidia.com>", "Date": "Tue, 4 May 2021 20:54:49 +0300", "Message-ID": "<20210504175500.3385811-5-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210504175500.3385811-1-matan@nvidia.com>", "References": "<20210429154335.2820028-1-matan@nvidia.com>\n <20210504175500.3385811-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "4bb89a94-eba6-45ec-4bad-08d90f25e0ed", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB4153:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB4153B6F7AABE95AB4C4FF92EDF5A9@DM6PR12MB4153.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:3826;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n qDlwM0464bS30uO7eRrv5xFF2kuZZ/zT9hHPnVXVyurKNm6BSay07xnmpQ9bW4sjPwAQ4lypSaatYXo5qJ4VZkF7B9vXNn7ET5c32QOG109NF4czGzzyEEf7XmxJ1H1wP7olzP44jn7C+KTuUD8hWoBFle3iRdNM/bMXCi2sK6luvTAns3tkdG1SVqiFpKYeMUCHhbf5wMP7cWdKge6JIAWPB8drhnyRMi8zkpnc/pRc0BEIndiZlyWwsGwem1mBaav/BiMz2txFlUqikjMbqolj3h7Y1T3irXOctPcwGFC4qtPh1E72+2S7pfWkz7pbqsNYts7pWzflOMtiIn0xLEQgRFwiBTjPFA1Xu2gW/P0BoauG3RGc/y2LaBZOzPevNB66CmjTtAn8jU8+E8dTm0NkjyZ+CBPIw3i2EHVUGyxDa7p4R2ogkQUXe+nCkFNUGKJp6qafxf3FAqx2PSY16FtNRICfRmTDv4Fy6x0fLuhD8DCHR0o+iL56yu9BGp8HhcncapjbbEOw65XsL5Y6mT3YtjOfar21lReF4XgeJTLY5Z9xqIjKerU9l06/sIvJHCrOb5KNjbbmCUaFSNSedyArMLmZJNvYC+j1jrwkiYWIGhMLM89yDZdb3xbp2aGMWIlshrkVTzoK42tKYkqBA6nc6BdC9mDWIkfV7iasNtI=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(376002)(136003)(39860400002)(396003)(346002)(36840700001)(46966006)(4326008)(2616005)(26005)(5660300002)(356005)(8936002)(478600001)(70586007)(70206006)(2906002)(36756003)(7636003)(86362001)(55016002)(16526019)(1076003)(82310400003)(186003)(83380400001)(6286002)(7696005)(36906005)(336012)(316002)(47076005)(6916009)(36860700001)(426003)(107886003)(82740400003)(54906003)(6666004)(8676002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 May 2021 17:56:01.0420 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4bb89a94-eba6-45ec-4bad-08d90f25e0ed", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT045.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4153", "Subject": "[dpdk-dev] [PATCH v3 04/15] common/mlx5: add HCA cap for AES-XTS\n crypto", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Dekel Peled <dekelp@nvidia.com>\n\nUpdate the PRM structure and HCA capabilities reading, to include\nrelevant capabilities for AES-XTS crypto.\n\nSigned-off-by: Dekel Peled <dekelp@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++\n drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++\n drivers/common/mlx5/mlx5_prm.h | 5 ++++-\n 3 files changed, 9 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex a0bf0d3009..7ca767944e 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -771,6 +771,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\tMLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);\n \tattr->umr_modify_entity_size_disabled =\n \t\tMLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);\n+\tattr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);\n+\tif (attr->crypto)\n+\t\tattr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);\n \tif (attr->qos.sup) {\n \t\tMLX5_SET(query_hca_cap_in, in, op_mod,\n \t\t\t MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 870bdb6b30..28ade5bbc4 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -137,6 +137,8 @@ struct mlx5_hca_attr {\n \tuint32_t qp_ts_format:2;\n \tuint32_t regex:1;\n \tuint32_t reg_c_preserve:1;\n+\tuint32_t crypto:1; /* Crypto engine is supported. */\n+\tuint32_t aes_xts:1; /* AES-XTS crypto is supported. */\n \tuint32_t regexp_num_of_engines;\n \tuint32_t log_max_ft_sampler_num:8;\n \tuint32_t geneve_tlv_opt;\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 2e5e42f6e9..a8fbfbb0f5 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1427,7 +1427,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 sq_ts_format[0x2];\n \tu8 rq_ts_format[0x2];\n \tu8 reserved_at_444[0x1C];\n-\tu8 reserved_at_460[0x10];\n+\tu8 reserved_at_460[0x8];\n+\tu8 aes_xts[0x1];\n+\tu8 crypto[0x1];\n+\tu8 reserved_at_46a[0x6];\n \tu8 max_num_eqs[0x10];\n \tu8 reserved_at_480[0x3];\n \tu8 log_max_l2_table[0x5];\n", "prefixes": [ "v3", "04/15" ] }