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GET /api/patches/92747/?format=api
{ "id": 92747, "url": "http://patches.dpdk.org/api/patches/92747/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210504175500.3385811-4-matan@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210504175500.3385811-4-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210504175500.3385811-4-matan@nvidia.com", "date": "2021-05-04T17:54:48", "name": "[v3,03/15] common/mlx5: optimize read of general obj type caps", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "372b41ec70cd0feb3ac09d38e3a61eb2735da9ae", "submitter": { "id": 1911, "url": "http://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210504175500.3385811-4-matan@nvidia.com/mbox/", "series": [ { "id": 16811, "url": "http://patches.dpdk.org/api/series/16811/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16811", "date": "2021-05-04T17:54:45", "name": "mlx5 common part for crypto driver", "version": 3, "mbox": "http://patches.dpdk.org/series/16811/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92747/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92747/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 47782A0A02;\n\tTue, 4 May 2021 19:55:54 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 34C49410E9;\n\tTue, 4 May 2021 19:55:54 +0200 (CEST)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2050.outbound.protection.outlook.com [40.107.243.50])\n by mails.dpdk.org (Postfix) with ESMTP id 6A78D40147\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>, Dekel Peled <dekelp@nvidia.com>", "Date": "Tue, 4 May 2021 20:54:48 +0300", "Message-ID": "<20210504175500.3385811-4-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210504175500.3385811-1-matan@nvidia.com>", "References": "<20210429154335.2820028-1-matan@nvidia.com>\n <20210504175500.3385811-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "5ae8b0ca-e8be-4481-ca8e-08d90f25dae9", "X-MS-TrafficTypeDiagnostic": "SN6PR12MB2733:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <SN6PR12MB27331383C9C733474DE62971DF5A9@SN6PR12MB2733.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:1775;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 29QrigdKbNBIVyI2ObXp/Eu1WY4CrarlJjUpI577FikUnam2dh6j/6R8TP8at0kC+ejZoFndWmp8pgPbjvCWpShPNj0ibaONcz7EgS/F930K2ZrIj/h5Hhvpfyj3uz21Y5cXWHdejX8NREuFbDKiqWCqB7m1GU7kxqQTRsy0OGsL2186hswS/jFIPfvD3fmwArK3j9i8MOAHiBAgLLc3OlqrvikDuvUCKJRzUB5Kcbit6eNKJzFLAhJegP4WWan7A9+OKOh7LbnZQx6C3wivTk4u0tfQa6xL38j2ovJmez4XICZRattVnzUHz5iOqxvzp9BYTqhlrd/E8jBOwTdJcuQKe9GzIgvtoclCwa2UPgzvycHZNBzkRSa/EvhwiCsYNt7R9uURb1dzXK0zOxBmHxlX97KOM9VlXapNJ93zwIm8yJde1nJ6sy8j1SJx8hwgZBWadAj9cyEleAk0X2xPPLIB6ZLGN99Ji3/dPqXrPPD9HCQl8rTFIPVYWRvK7yJRrGvyXlM+qviW1U7IQQ2D7dTkTUwYEjKrBUPgAqU3bwQmg12CEji/7LXBu8hTX5HnM8yhjfG5uczNOPcA4x0+N2NgDDIapAB9eOLjr6VgjNmq6f/qne1NwK6q9EmjXAllKwou9tBD1JxkXRSwkDUxY+OfoYmbz4HogErHoekuV7Y=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(39860400002)(376002)(396003)(346002)(136003)(36840700001)(46966006)(47076005)(316002)(8936002)(1076003)(336012)(70586007)(6916009)(70206006)(86362001)(82740400003)(186003)(478600001)(54906003)(36860700001)(55016002)(5660300002)(36906005)(7636003)(82310400003)(83380400001)(356005)(8676002)(6286002)(107886003)(4326008)(16526019)(36756003)(26005)(7696005)(426003)(2616005)(2906002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 May 2021 17:55:50.9507 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5ae8b0ca-e8be-4481-ca8e-08d90f25dae9", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT027.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN6PR12MB2733", "Subject": "[dpdk-dev] [PATCH v3 03/15] common/mlx5: optimize read of general\n obj type caps", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Dekel Peled <dekelp@nvidia.com>\n\nGeneral object types support is indicated in bitmap general_obj_types,\nwhich is part of HCA capabilities list.\nCurrently this bitmap is read multiple times, and each time a different\nbit is extracted.\n\nThis patch optimizes the code, reading the bitmap once into a local\nvariable, and then extracting the required bits.\n\nSigned-off-by: Dekel Peled <dekelp@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 21 ++++++++++++++++-----\n 1 file changed, 16 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 831175efc5..a0bf0d3009 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -647,6 +647,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tuint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};\n \tvoid *hcattr;\n \tint status, syndrome, rc, i;\n+\tuint64_t general_obj_types_supported = 0;\n \n \tMLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);\n \tMLX5_SET(query_hca_cap_in, in, op_mod,\n@@ -725,12 +726,22 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);\n \tattr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t regexp_num_of_engines);\n-\tattr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n-\t\t\t\t\t general_obj_types) &\n+\t/* Read the general_obj_types bitmap and extract the relevant bits. */\n+\tgeneral_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,\n+\t\t\t\t\t\t general_obj_types);\n+\tattr->vdpa.valid = !!(general_obj_types_supported &\n+\t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);\n+\tattr->vdpa.queue_counters_valid =\n+\t\t\t!!(general_obj_types_supported &\n+\t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);\n+\tattr->parse_graph_flex_node =\n+\t\t\t!!(general_obj_types_supported &\n+\t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);\n+\tattr->flow_hit_aso = !!(general_obj_types_supported &\n \t\t\t\tMLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);\n-\tattr->geneve_tlv_opt = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n-\t\t\t\t\t general_obj_types) &\n-\t\t\t\tMLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);\n+\tattr->geneve_tlv_opt = !!(general_obj_types_supported &\n+\t\t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);\n+\t/* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */\n \tattr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);\n \tattr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);\n \tattr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);\n", "prefixes": [ "v3", "03/15" ] }